CN101364539A - Gate layer manufacturing method, semiconductor device manufacturing method and semiconductor construction - Google Patents
Gate layer manufacturing method, semiconductor device manufacturing method and semiconductor construction Download PDFInfo
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- CN101364539A CN101364539A CNA2007100448130A CN200710044813A CN101364539A CN 101364539 A CN101364539 A CN 101364539A CN A2007100448130 A CNA2007100448130 A CN A2007100448130A CN 200710044813 A CN200710044813 A CN 200710044813A CN 101364539 A CN101364539 A CN 101364539A
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Abstract
A manufacturing method of a grid layer comprises the steps of providing a semiconductor substrate with a grid electrode insulating layer; forming a first polycrystalline silicon layer on the semiconductor substrate; forming a second polycrystalline silicon layer with randomly distributed crystal grains; and carrying out ion implantation doping to the second and the first polycrystalline silicon layers. The invention also provides a manufacturing method of a semiconductor device, and a semiconductor structure. The method can prevent or reduce doping ions from entering into or passing through the grid electrode insulating layer when carrying out ion implantation doping to the grid electrode layers.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacture method of grid layer, the manufacture method of semiconductor device and semiconductor structure.
Background technology
Along with the continuous progress of semiconductor fabrication process, integrated level is more and more higher, represents the critical size of grid of semiconductor fabrication process level also more and more littler; In metal oxide semiconductor transistor, the general material that adopts polysilicon as the manufacturing grid, and, be to reduce power consumption, raising response speed, usually polysilicon is mixed, form the polysilicon that mixes, to reduce the resistance of grid, for example, polysilicon gate for N type metal oxide semiconductor transistor (NMOS), mix N type impurity, the polysilicon gate for P-type mos transistor (PMOS) mixes p type impurity.
Utilize the manufacturing process of doped polycrystalline silicon formation grid as follows: at first on Semiconductor substrate, to deposit gate insulator, deposit spathic silicon layer on described gate insulator; Then, described polysilicon layer is carried out ion implantation doping, the impurity that mixes is used to improve the resistivity of polysilicon layer; Then, remove the part polysilicon layer, form grid by photoetching and etching technics;
Number of patent application be US 6949471 B2 U.S. Patent Publication a kind of manufacture method of grid, Fig. 1 to Fig. 3 is the generalized section of each step corresponding construction of manufacture method of the grid of described U.S. Patent Publication;
As shown in Figure 1, at first provide Semiconductor substrate 210, form gate insulator 212 on described Semiconductor substrate 210, form grid layers (Gate Layer) 214 on described gate insulator 212, the material of described grid layer 214 can be a polysilicon;
Described grid layer 214 is mixed, to reduce the resistance of described grid layer 214;
As shown in Figure 2, form mask layer 216 and 218 on described grid layer 214, wherein, described mask layer 216 can be a silica, and described mask layer 218 can be a silicon oxynitride;
As shown in Figure 3, by photoetching and the graphical described grid layer 214 of etching, form grid 220, and remove described mask layer 216 and 218.
The polysilicon that described employing is mixed forms in the technology of grid, and ion injects during doping energy and energy are all very big, and the energy of injection can reach 5KeV to 15KeV, and dosage can reach 2 * 10
15Atom/cm
2To 5 * 10
15Atom/cm
2, the ion of injection can enter or penetrate gate insulator, and the metal oxide semiconductor device threshold voltage shifts, leakage current increase etc. that cause formation are problem electrically.
Summary of the invention
The invention provides a kind of manufacture method of grid layer, the manufacture method and the semiconductor structure of semiconductor device, the present invention can avoid or reduce the problem that dopant ion entered or penetrated gate insulator to the ion implantation doping of grid layer the time.
The manufacture method of a kind of grid layer provided by the invention comprises:
Semiconductor substrate with gate insulator is provided;
On described Semiconductor substrate, form first polysilicon layer;
On described first polysilicon layer, form second polysilicon layer of crystal grain disorder distribution;
Described second polysilicon layer and first polysilicon layer are carried out ion implantation doping.
Optionally, the method that forms described second polysilicon layer is a low-pressure chemical vapor deposition.
Optionally, the reacting gas that forms described second polysilicon layer is SiH
4, Si
2H
6And H
2
Optionally, the technology that forms described second polysilicon layer is carried out or is carried out respectively in different process cavity with the technology original position that forms first polysilicon layer.
Optionally, carry out on described second polysilicon layer, forming amorphous silicon layer before the ion implantation doping.
Optionally, before carrying out ion implantation doping, on described second polysilicon layer, form the 3rd polysilicon layer.
Optionally, the technology that forms described the 3rd polysilicon layer is identical with the technology that forms first polysilicon layer.
Optionally, the technology that forms described the 3rd polysilicon layer can original position be carried out or carry out respectively in different process cavity with the technology that forms described second polysilicon layer.
Optionally, described second polysilicon layer is one or more layers.
Optionally, described second polysilicon layer is a multilayer, and along with the increase of the number of plies, crystallite dimension reduces.
Optionally, after carrying out ion implantation doping, described first polysilicon layer and second polysilicon layer are annealed.
The present invention also provides a kind of manufacture method of semiconductor device, comprising:
Semiconductor substrate with gate insulator is provided;
On described Semiconductor substrate, form first polysilicon layer;
On described first polysilicon layer, form second polysilicon layer of crystal grain disorder distribution;
Described second polysilicon layer and first polysilicon layer are carried out ion implantation doping;
Graphical described second polysilicon layer and first polysilicon layer form grid.
Optionally, the method that forms described second polysilicon layer is a low-pressure chemical vapor deposition.
Optionally, the reacting gas that forms described second polysilicon layer is SiH
4, Si
2H
6And H
2
Optionally, the technology that forms described second polysilicon layer is carried out or is carried out respectively in different process cavity with the technology original position that forms first polysilicon layer.
Optionally, this method further comprises: form metal silicide and the Semiconductor substrate of described grid both sides is mixed on described grid.
Optionally, before or after graphical described second polysilicon layer and first polysilicon layer, described second polysilicon and first polysilicon layer are annealed.
The present invention also provides a kind of semiconductor structure, comprising:
Semiconductor substrate with gate insulator;
First polysilicon layer on the described Semiconductor substrate;
Second polysilicon layer of the crystal grain disorder distribution on described first polysilicon layer.
Optionally, described second polysilicon layer is one or more layers.
Optionally, on described second polysilicon layer, also has the 3rd polysilicon layer.
Compared with prior art, the present invention has the following advantages:
By on first polysilicon layer, forming second polysilicon layer of crystal grain disorder distribution, to reduce or to eliminate the phenomenon that dopant ion entered or penetrated gate insulator when first polysilicon layer is carried out ion implantation doping; Because crystal grain disorder distribution in second polysilicon layer, the direction in crystal grain gap also has unordered distribution; Thereby, when first polysilicon layer is carried out ion implantation doping, the ion that injects is owing to be subjected to the stopping of crystal grain of the disorder distribution of this second polysilicon layer, when entering into first polysilicon layer, energy can reduce to some extent, thereby can reduce or the ion avoiding injecting enters into or pass gate insulator; Can suppress or eliminate threshold voltage shift, problem that leakage current is bigger, improve the stability of semiconductor device that forms, improve the yield of product;
In addition, this second polysilicon layer be positioned at first polysilicon layer above, first polysilicon layer that also promptly between second polysilicon layer and gate insulator, has columnar grain, has the good interface characteristic between this first polysilicon layer and the gate insulator, second polysilicon layer can directly not contact with gate insulator, thereby can not influence described interfacial characteristics, the semiconductor device of formation still has stability preferably;
Forming the technology of described second polysilicon layer and the technology of described first polysilicon layer of formation can original position carry out, can avoid the repeatedly carrying or the transmission of Semiconductor substrate, reduce contaminated probability, help to improve the stability of semiconductor device and the yield of formation, simultaneously, can also shorten the manufacturing cycle, reduce manufacturing cost.
Description of drawings
Fig. 1 to Fig. 3 is the generalized section of each step corresponding construction of embodiment of manufacture method of a kind of grid of prior art;
Fig. 4 to Fig. 7 is the generalized section of each step corresponding construction of first embodiment of the manufacture method of grid layer of the present invention;
Fig. 8 for the relevant generalized section of second embodiment of the manufacture method of grid layer of the present invention;
Fig. 9 for the relevant generalized section of the 3rd embodiment of the manufacture method of grid layer of the present invention;
Figure 10 for the relevant generalized section of the 4th embodiment of the manufacture method of grid layer of the present invention;
Figure 11 is the flow chart of embodiment of the manufacture method of semiconductor device of the present invention.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Continuous development along with semiconductor fabrication process, the size of grid is done littler and littler, is the quick response of the semiconductor device that guarantee to form and the characteristic of low-power consumption, needs to reduce the resistance of grid, wherein one of method is when forming polysilicon gate, and polysilicon is carried out ion implantation doping; Yet when ion injected, because the energy of ions of injecting is bigger, the ion that causes injecting can pass gate insulator, enters into conducting channel.
The invention provides a kind of manufacture method of grid layer, when forming the polycrystalline silicon grid layer of making grid, at least form in this grid layer that a crystal grain is unordered and arrange the polysilicon layer of (or distribution), this polysilicon layer can slow down the energy of ions of injection, avoids producing when ion injects the problem that penetrates gate insulator.
Below in conjunction with embodiment the manufacture method of described grid layer is described in detail.
Fig. 4 to Fig. 7 is the generalized section of each step corresponding structure of first embodiment of the manufacture method of grid layer of the present invention.
As shown in Figure 4, provide Semiconductor substrate 10, described Semiconductor substrate 10 can be a kind of in monocrystalline silicon, polysilicon, the amorphous silicon; Described Semiconductor substrate 10 also can have silicon on the insulating barrier (Silicon On Insulator, SOI) structure; In described Semiconductor substrate 10, can mix N type impurity or p type impurity.
Prerinse is carried out on described Semiconductor substrate 10 surfaces, removed oxide or other impurity on described Semiconductor substrate 10 surfaces.Because described Semiconductor substrate 10 is exposed in the air and can forms natural oxidizing layer on the surface, the thickness evenness of this natural oxidizing layer and rete characteristic are all relatively poor, for avoiding of the influence of this natural oxidizing layer, need this natural oxidizing layer is removed to the rete characteristic of the gate insulator of follow-up formation.Common removal method is a wet etching, and for example BOE or HF or RCA clean etc.
Then, form gate insulator 12 on described Semiconductor substrate 10, described gate insulator 12 is oxygen containing dielectric layer, and described oxygen containing dielectric layer comprises silica and silicon oxynitride; Wherein, the method that forms silica is high temperature furnace pipe oxidation, rapid thermal oxidation (Rapid ThermalOxidation, RTO) or the original position water vapour produce oxidation (In-Situ Stream Generation, ISSG) a kind of in, described silica is carried out nitrogen treatment can form silicon oxynitride, wherein the method for nitrogenize comprises a kind of in high temperature furnace pipe nitrogenize, rapid thermal treatment nitrogenize or the pecvd nitride.
As shown in Figure 5, form first polysilicon layer 14 on described gate insulator 12, the formation method of described first polysilicon layer 14 can be a Low Pressure Chemical Vapor Deposition, and reacting gas comprises SiH
4Or Si
2H
6, the uniformity for the rete of first polysilicon layer 14 that improve to form can also add N in reacting gas
2
Among the embodiment therein, the temperature of reaction is 700 to 740 degree, and the pressure of reaction chamber is 200 to 300T, and the reaction time is 10 to 50 seconds, can control the thickness of first polysilicon layer 14 of formation according to the time of reaction; First polysilicon layer 14 that forms has column structure, and the crystal grain gap is approximately perpendicular to the surface of Semiconductor substrate 10;
After forming first polysilicon layer 14, because the crystallite dimension of column is bigger, and the crystal grain gap is approximately perpendicular to the surface of Semiconductor substrate 10, if directly carry out the operation of ion implantation technology, the ion that injects has part and enters into this first polysilicon layer 14 along described crystal grain gap, and this crystal grain gap is less to the resistance of the ion that injects, makes the ion injection can further enter into gate insulator 12, even passes this gate insulator 12 and enter into conducting channel; Make the decreasing insulating of gate insulator 12, and cause the problem such as threshold voltage shift, leakage current increase of the semiconductor device of formation;
For avoiding described problem, present embodiment formed one second polysilicon layer 16 again on described first polysilicon layer before carrying out ion implantation doping, as shown in Figure 6, and the crystal grain disorder distribution of this second polysilicon layer 16;
Because crystal grain disorder distribution in this second polysilicon layer 16, the direction in crystal grain gap is also no longer the same with first polysilicon layer 14, is approximately perpendicular to the surface of Semiconductor substrate 10, but also has unordered distribution; Thereby, when first polysilicon layer 14 is carried out ion implantation doping, the ion that injects is owing to be subjected to the stopping of crystal grain of the disorder distribution of this second polysilicon layer 16, when entering into first polysilicon layer 14, energy can reduce to some extent, thereby can reduce or the ion avoiding injecting enters or pass gate insulator 12; The also i.e. effect of this second polysilicon layer 16 with buffering;
In addition, this second polysilicon layer 16 be positioned at first polysilicon layer 14 above, first polysilicon layer 14 that also promptly between second polysilicon layer 16 and gate insulator 12, has columnar grain, has the good interface characteristic between this first polysilicon layer 14 and the gate insulator 12, second polysilicon layer 16 can directly not contact with gate insulator 12, thereby can not influence described interfacial characteristics, the semiconductor device of formation still has stability preferably;
Among the embodiment therein, the method that forms described second polysilicon layer 16 is a Low Pressure Chemical Vapor Deposition, and reacting gas comprises SiH
4, Si
2H
6And H
2, the temperature of reaction is 700 to 740 degree, the pressure of reaction chamber is 200 to 300T, reaction time is 10 to 30 seconds, can control the thickness of second polysilicon layer 16 of formation according to the time of reaction, after the reaction, the crystal grain disorder distribution in second polysilicon layer 16 of formation;
For improving the uniformity of the rete that forms second polysilicon layer 16, in reacting gas, also can add N
2
In addition, the technology that forms described second polysilicon layer 16 can original position be carried out or carry out respectively in different process cavity with the technology that forms described first polysilicon layer 14;
If original position is carried out in same process cavity, can avoid the repeatedly carrying or the transmission of Semiconductor substrate 10, reduce contaminated probability, help to improve the stability of semiconductor device and the yield of formation; Simultaneously, also can shorten the manufacturing cycle, reduce manufacturing cost;
As shown in Figure 7, form described second polysilicon layer 16 after, described second polysilicon layer 16 and first polysilicon layer 14 are carried out ion implantation doping, the impurity that mixes can be impurity such as phosphorus, arsenic, boron; The energy that ion injects is 5KeV to 15KeV;
Because the buffering or the barrier effect of unordered crystal grain in second polysilicon layer 16, make the ion that injects decrease through second polysilicon layer, 16 back energy, the ion of injection can be entered under the situation of first polysilicon layer 14, reduce to enter gate insulator 12 as much as possible or do not enter gate insulator 12;
In a further embodiment, can carry out selective doping to second polysilicon layer 16 and first polysilicon layer 14, such as, the ion that carries out N type impurity in the zone of needs being made NMOS injects, the ion that carries out p type impurity in the zone of needs being made PMOS injects, described selective doping need define doped regions by photoetching process, repeats no more here;
After finishing ion implantation doping process, described second polysilicon layer 16 and first polysilicon layer 14 are carried out annealing process, pass through annealing process, can make crystal grain crystallization again in described second polysilicon layer 16, formation is similar to the columnar grain in described first polysilicon layer 14, perhaps form with first polysilicon layer 14 in identical columnar grain, thereby make this second polysilicon layer 16 and first polysilicon layer 14 have roughly the same characteristic, common grid layer as the formation grid.
In addition, this annealing process also can make the ion that is injected in second polysilicon layer 16 and first polysilicon layer 14 be activated.
Fig. 8 for the relevant generalized section of second embodiment of the manufacture method of grid layer of the present invention;
As shown in Figure 8, after forming described second polycrystal layer 16, carry out before the ion injection, can also on described second polycrystal layer 16, form the 3rd polysilicon layer 18, described the 3rd polysilicon layer 18 can adopt identical manufacturing process manufacturing with described first polysilicon layer 14, thickness can be different, and the crystal grain in promptly described the 3rd polysilicon layer 18 also has column structure; Then described the 3rd polysilicon layer 18, second polysilicon layer 16 and first polysilicon layer 14 are carried out ion implantation doping and annealing.Described second polysilicon layer 16 can play buffering or barrier effect to the ion that injects when carrying out ion implantation doping;
But described the 3rd polysilicon layer 18, second polysilicon layer 16 carry out or carry out respectively in different process cavity with first polysilicon layer, 14 original positions;
In addition, the thickness of described the 3rd polysilicon layer 18, second polysilicon layer 16 and first polysilicon layer 14 can adjusting according to different semiconductor device.
Fig. 9 for the relevant generalized section of the 3rd embodiment of the manufacture method of grid layer of the present invention, as shown in Figure 9, after forming described second polysilicon layer 16, carry out can also on described second polysilicon layer 16, forming amorphous silicon 17 before ion injects; Then described amorphous silicon layer 17, second polysilicon layer 16, first polysilicon layer 14 are carried out ion implantation doping and annealing.Described amorphous silicon layer 17 and described second polysilicon layer 16 are in the effect of carrying out can playing buffering to the ion that injects or stopping when ion injects.
Figure 10 for the relevant generalized section of the 4th embodiment of the manufacture method of dividing grid layer of the present invention, described second polysilicon layer 16 can be multilayer, Figure 10 provides described second polysilicon layer 16 and is two-layer schematic diagram, be that described second polysilicon layer 16 comprises 16a and 16b, crystal grain among wherein said second polysilicon layer 16b and the 16a all is in disordered state, and the crystallite dimension among the described 16a is less than the crystallite dimension among the described 16b;
Described second polysilicon layer 16 can play buffering or barrier effect to the ion that injects when carrying out ion implantation doping;
But described second polysilicon layer 16 carries out or carries out respectively in different process cavity with first polysilicon layer, 14 original positions.
The present invention also provides a kind of manufacture method of semiconductor device, and Figure 11 is the flow chart of embodiment of the manufacture method of semiconductor device of the present invention.
As shown in figure 11,
Step S100 provides the Semiconductor substrate with gate insulator.
Step S110 forms first polysilicon layer on described Semiconductor substrate.
Crystal grain in described first polysilicon layer has column structure.
Step S120, second polysilicon layer of formation crystal grain disorder distribution on described first polysilicon layer.
The method that forms described second polysilicon layer is a low-pressure chemical vapor deposition;
The reacting gas that forms described second polysilicon layer is SiH
4, Si
2H
6And H
2
The technology that forms described second polysilicon layer is carried out or is carried out respectively in different process cavity with the technology original position that forms first polysilicon layer.
Step S130 carries out ion implantation doping to described second polysilicon layer and first polysilicon layer.
Because the crystal grain that has disorder distribution in described second polysilicon layer, when being mixed, described first polysilicon layer can play buffering or barrier effect to dopant ion, the ion that reduces or avoid injecting enters gate insulator or passes gate insulator, causes the electrical drift of the semiconductor device of formation.
Described first polysilicon layer and second polysilicon layer are annealed; By annealing make in described second polysilicon layer crystal grain again crystallization be column structure, thereby make second polysilicon layer and first polysilicon layer have roughly the same characteristic; This first polysilicon layer and second polysilicon layer are all the grid layer that forms grid.
Step S140, graphical described second polysilicon layer and first polysilicon layer form grid.
By photoetching and graphical described second polysilicon layer of etching technics and first polysilicon layer, can form grid.
In other embodiments, can before graphical, described second polysilicon layer and first polysilicon layer not annealed yet, and after graphical, described second polysilicon layer and first polysilicon layer are annealed, repeat no more here.
Further, can on described grid, form metal silicide, and the Semiconductor substrate of described grid both sides is being mixed, form source electrode and drain electrode, thereby form metal oxide semiconductor transistor with grid, source electrode and drain electrode.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (20)
1. the manufacture method of a grid layer is characterized in that, comprising:
Semiconductor substrate with gate insulator is provided;
On described Semiconductor substrate, form first polysilicon layer;
On described first polysilicon layer, form second polysilicon layer of crystal grain disorder distribution;
Described second polysilicon layer and first polysilicon layer are carried out ion implantation doping.
2. the manufacture method of grid layer as claimed in claim 1 is characterized in that: the method that forms described second polysilicon layer is a low-pressure chemical vapor deposition.
3. the manufacture method of grid layer as claimed in claim 1 is characterized in that: the reacting gas that forms described second polysilicon layer is SiH
4, Si
2H
6And H
2
4. as the manufacture method of the described grid layer of arbitrary claim in the claim 1 to 3, it is characterized in that: the technology that forms described second polysilicon layer is carried out or is carried out respectively in different process cavity with the technology original position that forms first polysilicon layer.
5. the manufacture method of grid layer as claimed in claim 1 is characterized in that: carry out forming amorphous silicon layer before the ion implantation doping on described second polysilicon layer.
6. the manufacture method of grid layer as claimed in claim 1 is characterized in that: formed the 3rd polysilicon layer before carrying out ion implantation doping on described second polysilicon layer.
7. the manufacture method of grid layer as claimed in claim 6 is characterized in that: the technology that forms described the 3rd polysilicon layer is identical with the technology that forms first polysilicon layer.
8. as the manufacture method of claim 6 or 7 described grid layers, it is characterized in that: the technology that forms described the 3rd polysilicon layer can original position be carried out or carry out respectively in different process cavity with the technology that forms described second polysilicon layer.
9. the manufacture method of grid layer as claimed in claim 1 is characterized in that: described second polysilicon layer is one or more layers.
10. the manufacture method of grid layer as claimed in claim 1 is characterized in that: described second polysilicon layer is a multilayer, and along with the increase of the number of plies, crystallite dimension reduces.
11. the manufacture method of grid layer as claimed in claim 1 is characterized in that: after carrying out ion implantation doping, described first polysilicon layer and second polysilicon layer are annealed.
12. the manufacture method of a semiconductor device is characterized in that, comprising:
Semiconductor substrate with gate insulator is provided;
On described Semiconductor substrate, form first polysilicon layer;
On described first polysilicon layer, form second polysilicon layer of crystal grain disorder distribution;
Described second polysilicon layer and first polysilicon layer are carried out ion implantation doping;
Graphical described second polysilicon layer and first polysilicon layer form grid.
13. the manufacture method of semiconductor device as claimed in claim 12 is characterized in that: the method that forms described second polysilicon layer is a low-pressure chemical vapor deposition.
14. the manufacture method of semiconductor device as claimed in claim 12 is characterized in that: the reacting gas that forms described second polysilicon layer is SiH
4, Si
2H
6And H
2
15. the manufacture method of semiconductor device as claimed in claim 12 is characterized in that: the technology that forms described second polysilicon layer is carried out or is carried out respectively in different process cavity with the technology original position that forms first polysilicon layer.
16. the manufacture method of semiconductor device as claimed in claim 12 is characterized in that, this method further comprises: form metal silicide and the Semiconductor substrate of described grid both sides is mixed on described grid.
17. the manufacture method of semiconductor device as claimed in claim 12 is characterized in that, this method further comprises: before or after graphical described second polysilicon layer and first polysilicon layer, described second polysilicon and first polysilicon layer are annealed.
18. a semiconductor structure is characterized in that, comprising:
Semiconductor substrate with gate insulator;
First polysilicon layer on the described Semiconductor substrate;
Second polysilicon layer of the crystal grain disorder distribution on described first polysilicon layer.
19. semiconductor structure as claimed in claim 18 is characterized in that: described second polysilicon layer is one or more layers.
20. semiconductor structure as claimed in claim 18 is characterized in that: on described second polysilicon layer, also have the 3rd polysilicon layer.
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|---|---|---|---|
| CN 200710044813 CN101364539B (en) | 2007-08-09 | 2007-08-09 | Gate layer manufacturing method, semiconductor device manufacturing method and semiconductor construction |
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|---|---|---|---|
| CN 200710044813 CN101364539B (en) | 2007-08-09 | 2007-08-09 | Gate layer manufacturing method, semiconductor device manufacturing method and semiconductor construction |
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|---|---|
| CN101364539A true CN101364539A (en) | 2009-02-11 |
| CN101364539B CN101364539B (en) | 2013-05-29 |
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ID=40390827
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|---|---|---|---|
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104217940A (en) * | 2014-09-24 | 2014-12-17 | 上海华力微电子有限公司 | Preparation method of polycrystalline silicon film |
| CN105957887A (en) * | 2012-07-18 | 2016-09-21 | 英飞凌科技股份有限公司 | Method of Manufacturing Semiconductor Devices Using Ion Implantation and semiconductor device |
| CN109727907A (en) * | 2017-10-30 | 2019-05-07 | 台湾积体电路制造股份有限公司 | Silicon-on-insulator substrate, semiconductor device and its manufacturing method |
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| US6281559B1 (en) * | 1999-03-03 | 2001-08-28 | Advanced Micro Devices, Inc. | Gate stack structure for variable threshold voltage |
| CN1377067A (en) * | 2001-03-22 | 2002-10-30 | 三菱电机株式会社 | Manufacturing method for semiconductor device and semiconductor device |
| CN1964066A (en) * | 2005-11-09 | 2007-05-16 | 台湾积体电路制造股份有限公司 | Gate electrode and mos transistor including gate and method of fabricating the same |
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2007
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6281559B1 (en) * | 1999-03-03 | 2001-08-28 | Advanced Micro Devices, Inc. | Gate stack structure for variable threshold voltage |
| CN1377067A (en) * | 2001-03-22 | 2002-10-30 | 三菱电机株式会社 | Manufacturing method for semiconductor device and semiconductor device |
| CN1964066A (en) * | 2005-11-09 | 2007-05-16 | 台湾积体电路制造股份有限公司 | Gate electrode and mos transistor including gate and method of fabricating the same |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105957887A (en) * | 2012-07-18 | 2016-09-21 | 英飞凌科技股份有限公司 | Method of Manufacturing Semiconductor Devices Using Ion Implantation and semiconductor device |
| CN105957887B (en) * | 2012-07-18 | 2019-06-18 | 英飞凌科技股份有限公司 | Use the method and semiconductor devices of ion implanting manufacturing semiconductor devices |
| CN104217940A (en) * | 2014-09-24 | 2014-12-17 | 上海华力微电子有限公司 | Preparation method of polycrystalline silicon film |
| CN109727907A (en) * | 2017-10-30 | 2019-05-07 | 台湾积体电路制造股份有限公司 | Silicon-on-insulator substrate, semiconductor device and its manufacturing method |
| CN109727907B (en) * | 2017-10-30 | 2021-07-27 | 台湾积体电路制造股份有限公司 | Silicon-on-insulator substrate, semiconductor device and method for manufacturing the same |
| US11164945B2 (en) | 2017-10-30 | 2021-11-02 | Taiwan Semiconductor Manufacturing Company Ltd. | SOI substrate, semiconductor device and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101364539B (en) | 2013-05-29 |
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