CN101651096B - Method for manufacturing gate layer - Google Patents
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- CN101651096B CN101651096B CN2008101184045A CN200810118404A CN101651096B CN 101651096 B CN101651096 B CN 101651096B CN 2008101184045 A CN2008101184045 A CN 2008101184045A CN 200810118404 A CN200810118404 A CN 200810118404A CN 101651096 B CN101651096 B CN 101651096B
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Abstract
A method for forming a gate layer comprises the following steps of: providing a substrate of a polysilicon layer; carrying out a plasma doping process, and adding nitrogen to the polysilicon layer; carrying out an ion implantation doping process, and adding impurities capable of reducing resistivity of the polysilicon layer to the polysilicon layer; and carrying out an annealing process of the polysilicon layer undergoing plasma doping and ion implantation doping. The method has the advantages of inhibiting enlargement of the size of polysilicon crystal grains doped by impurity ions for improving the resistivity, and improving physical and electric performances of the formed gate.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacture method of grid layer.
Background technology
Along with the continuous progress of semiconductor fabrication process, integrated level is more and more higher, and the size of grid is also more and more littler; In metal oxide semiconductor transistor, the general material that adopts polysilicon as the manufacturing grid, and, be to reduce power consumption, raising response speed, usually polysilicon is mixed, form the polysilicon that mixes, to reduce the resistance of grid, for example, polysilicon gate for N type metal oxide semiconductor transistor (NMOS), mix N type impurity, the polysilicon gate for P-type mos transistor (PMOS) mixes p type impurity.
At number of patent application is in the United States Patent (USP) of US6949471B2, discloses a kind of manufacture method of grid, and Fig. 1 to Fig. 3 is the generalized section of each step corresponding construction of manufacture method of the grid of described U.S. Patent Publication.
As shown in Figure 1, at first provide substrate 210, form gate dielectric layer 212 on described substrate 210, form grid layers (Gate Layer) 214 on described gate dielectric layer 212, the material of described grid layer 214 can be a polysilicon;
Described grid layer 214 is mixed, to reduce the resistivity of described grid layer 214;
As shown in Figure 2, form mask layer 216 and 218 on described grid layer 214, wherein, described mask layer 216 can be a silica, and described mask layer 218 can be a silicon oxynitride;
As shown in Figure 3, by photoetching and the graphical described grid layer 214 of etching, form grid 220, and remove described mask layer 216 and 218.
Wherein, described doping process generally adopts ion implantation technology, and after ion injects, activates the foreign ion that mixes by annealing process.Yet, in the grid layer of polysilicon, mix foreign ion and annealed after, can cause the crystallite dimension of polysilicon to increase, and the crystallite dimension increase brings a series of problem can for the device that forms, for example, can influence grid physics and electrology characteristic, can cause the overlap capacitance (overlap capacitance) of source and drain areas and grid overlapping region etc.
Summary of the invention
The invention provides a kind of formation method of grid layer, can suppress to mix the increase of the polysilicon grain size of foreign ion.
The formation method of a kind of grid layer provided by the invention comprises:
Substrate with polysilicon layer is provided;
Carry out plasma doping technology, in described polysilicon layer, mix nitrogen and mix;
Carry out ion implantation doping process, in described polysilicon layer, mix the impurity that reduces this polysilicon layer resistivity;
Polysilicon layer to described plasma doping of executed and ion implantation doping is carried out annealing process.
Optionally, carry out the step of described plasma doping technology earlier, carry out the step of described ion implantation doping process again; Perhaps carry out the step of described ion implantation doping process earlier, carry out the step of described plasma doping technology again.
Optionally, if carry out the step of described plasma doping technology earlier, carry out the step of described ion implantation doping process again; Then between the step of the step of described plasma doping technology and described ion implantation doping process, also comprise the step of described polysilicon layer being carried out nitrogen doping after-baking.
Optionally, described plasma doping technology is decoupled plasma nitrogen treatment process, low temperature plasma nitrogen treatment process or remote plasma nitrogen treatment process.
Optionally, reacting gas is N in the described plasma doping technology
2, N
2O, NO or NH
3In a kind of or the combination.
Optionally, also be mixed with inert gas in the described reacting gas.
Optionally, described plasma doping technological reaction gas is N
2, wherein said N
2Flow be 200sccm to 500sccm.
Optionally, described annealing process is rapid thermal annealing or boiler tube annealing, and annealing temperature is 1000 ℃ to 1100 ℃.
Optionally, the described impurity that reduces this polysilicon layer resistivity is phosphorus or arsenic or boron.
The present invention also provides a kind of formation method of grid layer, comprising:
Substrate is provided;
On described substrate, form polysilicon layer, and original position is mixed the impurity that reduces this polysilicon layer resistivity to described polysilicon layer execution ion implantation doping process in described polysilicon layer;
Carry out plasma doping technology, in described polysilicon layer, mix nitrogen and mix;
Polysilicon layer to the described plasma doping technology of executed is carried out annealing process.
Optionally, described plasma doping technology is decoupled plasma nitrogen treatment process, low temperature plasma nitrogen treatment process or remote plasma nitrogen treatment process.
Optionally, reacting gas is N in the described plasma doping technology
2, N
2O, NO or NH
3In a kind of or the combination.
Compared with prior art, one of them of technique scheme has the following advantages at least:
Pass through plasma doping, make in the grid layer of the implanted polysilicon of nitrogen containing plasma, this nitrogen impurity is in subsequent annealing technology, nitrogen can infiltrate or enter in the polysilicon grain, make and form the cavity in the polysilicon grain, and be decomposed into less crystal grain, form bigger crystal grain thereby suppress polysilicon grain;
In addition, method by plasma doping is mixed nitrogen impurity in polysilicon layer, on the one hand the damage that polysilicon layer is caused is less or can not cause damage, and in doping process, the nitrogen ion can not penetrate polysilicon layer, enter into gate dielectric layer, or penetrate described gate dielectric layer, thus less to the damage of polysilicon layer and gate dielectric layer;
In addition, the method that using plasma mixes, more help suppressing the size of crystal grain in the polysilicon layer, after the using plasma doping method, can the crystallite dimension of polysilicon layer almost change behind the impurity that reduce resistivity so that the difference of crystallite dimension and the crystallite dimension size of the polysilicon layer that does not mix the impurity that reduces resistivity fully of polysilicon layer with the impurity (for example phosphorus) that reduces resistivity less than dust, is equivalent to mix;
In addition,, in polysilicon layer, mix nitrogen impurity, can be suppressed in the ion implantation doping process of the follow-up reduction resistivity that polysilicon layer is carried out, penetrate described polysilicon layer or gate dielectric layer by the method for plasma doping.
Description of drawings
Fig. 1 to Fig. 3 is the generalized section of each step corresponding construction of the manufacture method of existing a kind of grid;
Fig. 4 is the flow chart of embodiment one of the manufacture method of grid layer of the present invention;
Fig. 5 to Fig. 7 is the generalized section of each step corresponding structure of embodiment one of the manufacture method of grid layer of the present invention;
Fig. 8 is the flow chart of embodiment two of the manufacture method of grid layer of the present invention;
Fig. 9 is the flow chart of embodiment three of the manufacture method of grid layer of the present invention;
Figure 10 is the flow chart of embodiment four of the manufacture method of grid layer of the present invention.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, when the embodiment of the invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
In the manufacturing process of the grid of semiconductor device, usually need in polysilicon gate, mix impurity, reduce the resistivity of grid, to improve the electric property of the semiconductor device that forms.For example, mix N type impurity in nmos device, for example phosphorus mixes p type impurity in the PMOS device, and for example boron etc. all is the resistivity for the grid that reduces the MOS device.The technology of mixing the impurity that reduces resistivity in grid is generally in the grid layer formation process or carry out after forming.Yet, in polycrystalline silicon grid layer, mix the impurity that reduces resistivity after, can make the crystallite dimension of polycrystalline silicon grid layer become big after annealed, particularly, after the polysilicon that is used for the grid layer mixes phosphorus, annealed for the NNOS device, can make crystallite dimension increase 10 to 50 dusts, in addition bigger.And the crystallite dimension increase brings a series of problem can for the MOS device, for example, can influence grid physics and electrology characteristic, can cause the overlap capacitance (overlap capacitance) of source and drain areas and grid overlapping region etc.Thereby, when reducing the resistance rate, also wish can not can to cause the increase of crystallite dimension by mixing.
Based on this, the present invention proposes a kind of formation method of grid layer.In the formation method of grid layer of the present invention, method by plasma doping is mixed nitrogen impurity in polycrystalline silicon grid layer, suppress the growth of crystal grain in the polycrystalline silicon grid layer by nitrogen impurity, thereby reduce the crystallite dimension of doped polycrystalline silicon grid, with physics and the electrology characteristic that improves polysilicon gate.
Be described in detail below in conjunction with embodiment and accompanying drawing formation method grid layer of the present invention; should be noted that; following description is particularly only introduced in order to be more readily understood method of the present invention the description of some ins and outs, and it should not limit the protection range of claim of the present invention improperly.Those skilled in the art can make corresponding modification, change and replacement according to the instruction of specification of the present invention and embodiment.
Embodiment one
Fig. 4 is the flow chart of first embodiment of the manufacture method of grid layer of the present invention.
Please refer to Fig. 4, step S100 is for providing the substrate with polysilicon layer.
Step S110 mixes nitrogen impurity for carrying out plasma doping technology in described polysilicon layer.
Step S120 mixes the impurity that reduces this polysilicon layer resistivity for carrying out ion implantation doping process in described polysilicon layer.
Step S130 carries out annealing process to the polysilicon layer of described plasma doping of executed and ion implantation doping.
Be described in detail below in conjunction with the flow chart of generalized section the first above-mentioned embodiment.
Please refer to Fig. 5, substrate 10 is provided, on described substrate 10, have gate dielectric layer 12 and polysilicon layer 14 successively.
Wherein, substrate 10 can be a semi-conducting material, for example can be a kind of in monocrystalline silicon, polysilicon, the amorphous silicon, described substrate 10 also can be a kind of in silicon Germanium compound, the silicon gallium compound, described substrate 10 can also comprise silicon on epitaxial loayer or the insulating barrier (Silicon On Insulator, SOI) structure.
Described gate dielectric layer 12 can be a silica, and its formation method is that furnace oxidation, rapid thermal annealing oxidation or original position steam produce oxidation (ISSG).Certainly, described gate dielectric layer 12 also can be other material, for example silicon oxynitride.Here repeat no more.
Described polysilicon layer 14 can form by chemical vapor deposition method.Its thickness can be decided according to the needs of the electrology characteristic of the grid that forms.Here be not described in detail.
Then, please refer to Fig. 6, carry out plasma doping technology, in described polysilicon layer 14, mix nitrogen and mix.
In plasma doping technology, described substrate 10 is placed nitrogenous plasma environment, the nitrogen ion in the described plasma environment can be implanted in the polysilicon layer 14 of substrate 10, in described polysilicon layer 14, mix nitrogen impurity.
Wherein, described nitrogenous plasma acts on nitrogenous gas by microwave or radio frequency or ultraviolet source and produces, and described nitrogenous gas comprises N
2O, NO, NH
3, N
2In a kind of or the combination.In described nitrogenous gas, can mix inert gas as diluent gas, for example, mix He or Ar as diluent gas.
Wherein, described plasma doping technology can be decoupled plasma nitrogen treatment process (Decoupled Plasma Nitridation, DPN), low temperature plasma nitrogen treatment process (LowTemperature Plasma Nitridation) or remote plasma nitrogen treatment process (RemotePlasma Nitridation, RPN).
As an example, pecvd nitride described in the present embodiment adopts DPN technology, and reacting gas adopts N
2In DPN technology, substrate 10 placed processing chamber after, in processing chamber, feed nitrogenous gas, described nitrogenous gas is N
2, N
2With the mist of He or N2 and Ar, then with action of radio in described nitrogen, make its ionization, produce nitrogen containing plasma.In the implanted described polysilicon layer 14 of described nitrogen containing plasma, in described polysilicon layer 14, mix nitrogen impurity.This nitrogen impurity is in subsequent annealing technology, and nitrogen can infiltrate or enter in the polysilicon grain, makes to form the cavity in the polysilicon grain, and is decomposed into less crystal grain, forms bigger crystal grain thereby suppress polysilicon grain.
The power of radio frequency source is 500 to 2500W in the technology of DPN described in the present embodiment, and the pressure of process cavity is 10 to 100mTorr, N
2Flow is 200sccm to 500sccm, and temperature is less than 70 ℃.By adjusting radio-frequency power, process chamber pressure, N in the DPN technology
2May command nitrogen containing plasmas such as flow and temperature, time are implanted the degree of depth or concentration in the described polysilicon layer 14, thereby can control the distribution of nitrogen impurity in polysilicon layer 14 comparatively accurately.More help improving the electric property or the physical property of the grid of formation.
In other embodiments, described plasma doping technology also can be RPN, described RPN technology produces nitrogen gas plasma by microwave action in nitrogenous gas, and with in nitrogenous base in the described nitrogen gas plasma or the nitrogen base implanted polysilicon layer 14, repeats no more here.
In the above embodiments, the method by plasma doping can be incorporated into nitrogen impurity in the polysilicon layer 14, and in subsequent annealing technology, the nitrogen impurity that is incorporated in the polysilicon layer 14 can suppress grain growth.
In addition, the above-mentioned method of passing through plasma doping is mixed nitrogen impurity in polysilicon layer 14, method with respect to the ion injection, on the one hand the damage that polysilicon layer 14 is caused is less or can not cause damage, and in doping process, the nitrogen ion can not penetrate polysilicon layer 14, enters into gate dielectric layer 14, or it is penetrate described gate dielectric layer, thereby less to the damage of polysilicon layer 14 and gate dielectric layer 12.
In addition, the method that using plasma mixes, more help suppressing the size of crystal grain in the polysilicon layer 14, after the using plasma doping method, can the crystallite dimension of polysilicon layer 14 almost change behind the impurity that reduce resistivity so that the difference of crystallite dimension and the crystallite dimension size of the polysilicon layer 14 that does not mix the impurity that reduces resistivity fully of polysilicon layer 14 with the impurity (for example phosphorus) that reduces resistivity less than 10 dusts, is equivalent to mix.
In addition, method by plasma doping, in polysilicon layer 14, mix nitrogen impurity, can be suppressed in the ion implantation doping process of the follow-up reduction resistivity that polysilicon layer 14 is carried out described polysilicon layer 14 of the ion penetration of injection or gate dielectric layer 12.
Finish after the described plasma doping, as shown in Figure 7, described polysilicon layer 14 is carried out ion implantation doping process,, improve the performance of the grid that forms to reduce the resistivity of described polysilicon layer 14.The foreign ion that mixes is according to the difference of the MOS device that forms and difference for example, is mixed N type impurity in being used to form the grid layer of nmos device, and for example phosphorus or arsenic mix p type impurity in being used to form the grid layer of PMOS device, for example boron.Is those skilled in the art's technology known by ion implantation technology to the technology that polysilicon layer 14 mixes the impurity that is used to improve resistivity, is not described in detail here.
Finish after the described ion implantation doping, described nitrogen mixes and the polysilicon layer of ion implantation doping 14 is carried out annealing process to carrying out, described annealing can activate by the ion injection and be incorporated into the foreign ion of polysilicon layer 14, and described foreign ion is distributed again; Also can repair the damage that in ion implantation technology, polysilicon layer 14 is caused on the other hand.In annealing process, nitrogen impurity can suppress crystallite dimension increase in the polysilicon layer 14.
Described annealing process can be rapid thermal annealing (RTA).For example, can be the rapid thermal annealing (soak anneal) that peak temperature continues for some time.Annealing temperature can be 1000 ℃ to 1100 ℃.Certainly, described annealing process can be the boiler tube annealing process also, repeats no more here.
In addition, in described plasma, mix between the step and step of nitrogen impurity, can also comprise the step of described polysilicon layer being carried out nitrogen doping after-baking described polysilicon layer execution ion implantation doping process.Please refer to the following examples two.
Embodiment two
Fig. 8 is the flow chart of second embodiment of the manufacture method of grid layer of the present invention.
Please refer to Fig. 8, step S200 is for providing the substrate with polysilicon layer.
Step S210 is for carrying out plasma doping technology, and nitrogen impurity mixes in described polysilicon layer.
Step S220 carries out nitrogen doping after-baking technology to described polysilicon layer, and wherein, described heat treatment can be rapid thermal annealing or boiler tube annealing process.
Step S230 mixes the impurity that reduces this polysilicon layer resistivity for carrying out ion implantation doping process in described polysilicon layer.
Step S240 carries out annealing process to the polysilicon layer of described plasma doping doping of executed and ion implantation doping.
In the step of the above embodiments two, remove between the step of the step of described plasma impurity and ion implantation doping process, comprise to the step of described polysilicon layer execution nitrogen doping after-baking and because outside the accommodation that this nitrogen doping after-baking is done, other step of this second embodiment and concrete process detail can be identical with embodiment one, are not described in detail here.
In addition, also can carry out ion implantation doping process earlier, carry out described plasma impurity technology again.Particularly, please refer to flow chart shown in Figure 9 among the embodiment three.
Embodiment three
Fig. 9 is the flow chart of the 3rd embodiment of the manufacture method of grid layer of the present invention.
Please refer to Fig. 9, step S300 is for providing the substrate with polysilicon layer.
Step S310 mixes the impurity that reduces this polysilicon layer resistivity for carrying out ion implantation doping process in described polysilicon layer.
Step S320 mixes nitrogen impurity for carrying out plasma doping technology in described polysilicon layer.
Step S330 carries out annealing process to the polysilicon layer of the described plasma doping technology of executed.
In the step of the above embodiments three, except adjusting described polysilicon layer is carried out the step of ion implantation doping process with the order of the step of carrying out plasma impurity and the accommodation that order adjustment is brought thus, other step of the 3rd embodiment and concrete process detail can be identical with embodiment one, are not described in detail here.
In addition, described polysilicon layer is mixed the technology of the impurity that reduces resistivity and can also carry out with the depositing operation original position of polysilicon layer, concrete, ask the flow chart shown in Figure 10 among the embodiment four.
Embodiment four
Figure 10 is the flow chart of manufacture method of the grid layer of the fourth embodiment of the present invention.
Please refer to Figure 10, step S400 is for providing substrate.
Step S410 is for to form polysilicon layer on described substrate, and original position is carried out doping process to described polysilicon layer.
Wherein, the method that forms described polysilicon layer can add AsH for those skilled in the art's low-pressure chemical vapor deposition known (LPCVD) technology in the mist of low-pressure chemical vapor deposition (LPCVD) technology
3, PH
3Or B
2H
6Can carry out in-situ doped to polysilicon.Here repeat no more.Certainly, also can adopt other method to form described polysilicon layer.
Step S420 mixes nitrogen impurity for carrying out plasma doping technology in described polysilicon layer.Wherein the plasma doping in this step can be identical with the concrete processing step of plasma doping described in the embodiment one, repeats no more here.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (12)
1. the manufacture method of a grid layer is characterized in that, comprising:
Substrate with polysilicon layer is provided;
Carry out plasma doping technology, in described polysilicon layer, mix nitrogen and mix;
Carry out ion implantation doping process, in described polysilicon layer, mix the impurity that reduces this polysilicon layer resistivity;
Polysilicon layer to described plasma doping of executed and ion implantation doping is carried out annealing process.
2. the manufacture method of grid layer as claimed in claim 1 is characterized in that: carry out the step of described plasma doping technology earlier, carry out the step of described ion implantation doping process again; Perhaps carry out the step of described ion implantation doping process earlier, carry out the step of described plasma doping technology again.
3. the manufacture method of grid layer as claimed in claim 1 is characterized in that: if carry out the step of described plasma doping technology earlier, carry out the step of described ion implantation doping process again; Then between the step of the step of described plasma doping technology and described ion implantation doping process, also comprise the step of described polysilicon layer being carried out nitrogen doping after-baking.
4. as the manufacture method of claim 1 or 2 or 3 described grid layers, it is characterized in that: described plasma doping technology is decoupled plasma nitrogen treatment process, low temperature plasma nitrogen treatment process or remote plasma nitrogen treatment process.
5. the manufacture method of grid layer as claimed in claim 4 is characterized in that: reacting gas is N in the described plasma doping technology
2, N
2O, NO or NH
3In a kind of or the combination.
6. the manufacture method of grid layer as claimed in claim 5 is characterized in that: also be mixed with inert gas in the described reacting gas.
7. the manufacture method of grid layer as claimed in claim 5 is characterized in that: described plasma doping technological reaction gas is N
2, wherein said N
2Flow be 200sccm to 500sccm.
8. as the manufacture method of claim 1 to 3 or the described grid layer of 5 to 7 arbitrary claims, it is characterized in that: described annealing process is rapid thermal annealing or boiler tube annealing, and annealing temperature is 1000 ℃ to 1100 ℃.
9. as the manufacture method of claim 1 to 3 or the described grid layer of 5 to 7 arbitrary claims, it is characterized in that: the described impurity that reduces this polysilicon layer resistivity is phosphorus or arsenic or boron.
10. the manufacture method of a grid layer is characterized in that, comprising:
Substrate is provided;
On described substrate, form polysilicon layer, and original position is mixed the impurity that reduces this polysilicon layer resistivity to described polysilicon layer execution ion implantation doping process in described polysilicon layer;
Carry out plasma doping technology, in described polysilicon layer, mix nitrogen and mix;
Polysilicon layer to the described plasma doping technology of executed is carried out annealing process.
11. the manufacture method of grid layer as claimed in claim 10 is characterized in that: described plasma doping technology is decoupled plasma nitrogen treatment process, low temperature plasma nitrogen treatment process or remote plasma nitrogen treatment process.
12. the manufacture method of grid layer as claimed in claim 11 is characterized in that: described etc.
Reacting gas is N in the gas ions doping process
2, N
2O, NO or NH
3In a kind of or the combination.
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