CN106558555A - The forming method of fin field effect pipe - Google Patents
The forming method of fin field effect pipe Download PDFInfo
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- CN106558555A CN106558555A CN201510631672.7A CN201510631672A CN106558555A CN 106558555 A CN106558555 A CN 106558555A CN 201510631672 A CN201510631672 A CN 201510631672A CN 106558555 A CN106558555 A CN 106558555A
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- plasma doping
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
Abstract
A kind of forming method of fin field effect pipe, including：The first side wall is formed in the first fin of Part II sidewall surfaces；The second side wall is formed in the second fin of Part II sidewall surfaces；The first plasma doping process is carried out to the second fin of Part I, the dopant ion type of the first plasma doping process is identical with the dopant ion type of the second well region；The second plasma doping process is carried out to the first fin of Part I, the dopant ion type of the second plasma doping process is identical with the dopant ion type of the first well region；Process with after the process of the second plasma doping the first plasma doping is carried out, the first fin and the second fin are made annealing treatment；Remove the first side wall and the second side wall；Remove the first hard mask layer and the second hard mask layer；Dielectric layer is formed in substrate surface, dielectric layer covers the first fin of Part I side wall and the second fin of Part I side wall.The present invention improves the electric property of the fin field effect pipe to be formed.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of formation side of fin field effect pipe
Method.
Background technology
With the continuous development of semiconductor process technique, semiconductor technology node follows the development of Moore's Law
Trend constantly reduces.In order to adapt to the reduction of process node, it has to constantly shorten MOSFET field effects
The channel length of pipe.The shortening of channel length increases MOSFET fields with the tube core density for increasing chip
The benefits such as the switching speed of effect pipe.
However, with the shortening of device channel length, the distance between device source electrode and drain electrode also shortens therewith,
So grid is deteriorated to the control ability of raceway groove, the difficulty of grid voltage pinch off (pinch off) raceway groove
Also it is increasing so that sub-threshold leakage (subthreshold leakage) phenomenon, i.e., so-called short channel
Effect (SCE：Short-channel effects) easily occur.
Therefore, the requirement scaled in order to preferably adapt to device size, semiconductor technology are gradually opened
The transistor transient begun from planar MOSFET transistor to the three-dimensional with more high effect, such as fin
Formula field effect transistor (FinFET).In FinFET, grid at least can enter from both sides to ultra-thin body (fin)
Row control, with control ability of the grid more much better than than planar MOSFET devices to raceway groove, can be fine
Suppression short-channel effect；And FinFET is relative to other devices, with more preferable existing integrated circuit
The compatibility of manufacturing technology.
However, the electric property of the fin field effect pipe of prior art formation has much room for improvement.
The content of the invention
The problem that the present invention is solved is to provide a kind of forming method of fin field effect pipe, improves the fin for being formed
The electric property of formula field effect transistor.
To solve the above problems, the present invention provides a kind of forming method of fin field effect pipe, including：Carry
For the substrate including first area and second area, in the first area substrate, the first well region is formed with,
The second well region is formed with the second area substrate, the first area substrate surface is formed with the first fin
Portion, the first fin top surface are formed with the first hard mask layer, the second area substrate surface shape
Into there is the second fin, the second fin top surface is formed with the second hard mask layer, wherein, described
One fin is included positioned at first fin of Part I of substrate surface and positioned at the first fin of Part I top
First fin of Part II on portion surface, second fin include the Part I positioned at substrate surface
Two fins and the second fin of Part II positioned at Part I the second fin top surface；Described
Two part the first fin sidewall surfaces form the first side wall；In the Part II the second fin sidewall surfaces
Form the second side wall；The first plasma doping process is carried out to the second fin of the Part I, it is described
The dopant ion type of the first plasma doping process is identical with the dopant ion type of the second well region；It is right
The first fin of the Part I carries out the second plasma doping process, second plasma doping
The dopant ion type of process is identical with the dopant ion type of the first well region；Carry out first grade from
After daughter doping treatment and the second plasma doping are processed, first fin and the second fin are entered
Row annealing；Remove first side wall and the second side wall；Remove first hard mask layer and second
Hard mask layer；Dielectric layer is formed in the substrate surface, the dielectric layer covers the first fin of Part I
Side wall and the second fin of Part I side wall.
Optionally, before the first plasma doping process is carried out, to the Part I second
Fin enters line width cutting process, reduces Part I the second fin width size；Carrying out described second
Before plasma doping process, enter line width cutting process to the first fin of the Part I, reduce
Part I the first fin width size.
Compared with prior art, technical scheme has advantages below：
In the technical scheme of the forming method of the fin field effect pipe that the present invention is provided, in Part II first
Fin sidewall surfaces form the first side wall, form the second side wall in the second fin of Part II sidewall surfaces；
Then the first plasma doping process is carried out to the second fin of Part I, first plasma is mixed
The dopant ion type for living together reason is identical with the dopant ion type of the second well region in second area substrate；It is right
The first fin of Part I carries out the second plasma doping process, and second plasma doping is processed
Dopant ion type it is identical with the dopant ion type of the first well region in the substrate of first area；Then to
One fin and made annealing treatment with the second fin so that the doping in the process of the first plasma doping from
Son is diffused in the second fin of Part I and concentration redistribution, the shape in the second fin of Part I
Into the 3rd well region so that the dopant ion in the process of the second plasma doping is in the first fin of Part I
Inside be diffused and redistribute with concentration, the 4th well region is formed in the first fin of Part I.Then, go
Except first side wall, the second side wall, the first hard mask layer and the second hard mask layer；In substrate surface
Dielectric layer is formed, the dielectric layer exposes Part II the first fin sidewall surfaces and Part II second
Fin sidewall surfaces.
In the present invention, the method for using plasma doping treatment forms the 3rd well region and the 4th well region, makes
Obtain the first fin and the second fin keeps good pattern and higher lattice quality, and avoid to second
The first fin and the second fin of Part II is divided to cause the raceway groove in unnecessary doping, therefore the first fin
There is the channel region in higher carrier mobility, and the second fin also there is higher carrier to move in area
Shifting rate.Meanwhile, the first well region and the 4th well region can constitute SSRW structures, play the first fin of prevention
The effect of break-through between interior source region and drain region, and stop the ion in substrate into the first fin of Part II
Diffusion, prevents the first fin threshold voltage shift.Second well region and the 3rd well region can constitute SSRW knots
Structure, plays a part of to prevent break-through between source region and drain region in the second fin, and stops the ion in substrate
To Part II the second fin internal diffusion, the second fin threshold voltage shift is prevented.
Further, before the first plasma doping process is carried out, the second fin of Part I is carried out
Width cutting is processed, and reduces Part I the second fin width size so that at the first plasma doping
Dopant ion during reason is easier to be doped the second fin of Part I, and follow-up in the second fin
The second grid structure that portion surface is formed is higher to the control ability of the second fin of Part I, so that
The ability of the 3rd well region prevention source region and drain region break-through in the second fin of Part I is higher.Entering
Before the process of the second plasma doping of row, enter line width cutting process to the first fin of Part I, subtract
Little Part I the first fin width size so that the doping in the second plasma doping processing procedure from
Son is easier to be doped the first fin of Part I, and follow-up the first of the formation of the first fin portion surface
Grid structure is higher to the control ability of the first fin of Part I, so that being located at Part I first
The ability of the 4th well region prevention source region and drain region break-through in fin is higher.
Description of the drawings
The cross-section structure of the fin field effect pipe forming process that Fig. 1 to Figure 12 is provided for one embodiment of the invention
Schematic diagram；
The section of the fin field effect pipe forming process that Figure 13 to Figure 14 is provided for another embodiment of the present invention
Structural representation.
Specific embodiment
The electric property of the fin field effect pipe formed from background technology, prior art has much room for improvement.
It has been investigated that, the fin bottom of fin field effect pipe is distant with grid structure, grid knot
Structure is weaker to the control ability of the bottom of fin, and the doping content of the fin is less, channel region
Space-charge region broadening under the electric field, source region are connected with drain region space-charge region, result in fin field effect
There is the punch through (punch through) between source region and drain region in the bottom of pipe, cause fin field effect
The electric property of pipe is low.And in order to improve the electric property of fin field effect pipe, it will usually in substrate
Doping dopant, the dopant in the substrate is easily spread to fin, and diffuses to the dopant in fin
Concentration distribution inequality causes threshold voltage to change, and this is also to cause fin field effect pipe electric property low
One of the reason for lower.For especially for SRAM device, if the dopant in substrate is spread to fin,
Can then cause the mismatch (Mismatch) between device to be deteriorated, for example, pull up (PU) transistor AND gate pull-up
Electrical parameter mismatch between transistor, between drop-down (PD) transistor AND gate pull-down transistor is poor so that
The uniformity of SRAM device is deteriorated.
In order to solve the above problems, a kind of solution is proposed, the shape in positioned at the fin in isolation structure
Into the super steep trap (SSRW, Super Step Retrograde Well) that drives in the wrong direction, mixing in the super steep retrograde trap
Heteroion is identical with the dopant ion type of well region in substrate, and the super steep dopant ion concentration driven in the wrong direction in trap
More than the dopant ion concentration of well region in substrate.The super steep trap that drives in the wrong direction can be good at preventing source region and leakage
The break-through in area, and prevent the dopant in substrate from diffusing in fin so that have in whole fin height
Uniform threshold value and avoid threshold voltage that fluctuation occurs.
It is common, adopt the mode of ion implantation technology to be doped fin bottom to form SSRW knots
Structure.However, ion implantation technology can cause implant damage to the surface of fin, cause the pattern of fin not
Good and generation lattice damage so that the carrier mobility in channel region is reduced, and causes fin field effect pipe
Degraded performance.Also, when forming the SSRW structures using ion implantation technology, it is easily caused in fin
Do not expect in region, to inject ion in portion, such as the region in fin as channel region is filled with ion, makes
The carrier mobility for obtaining channel region is low.
To solve the above problems, the present invention provides a kind of forming method of fin field effect pipe, at second
The first fin sidewall surfaces are divided to form the first side wall；Second is formed in the second fin of Part II sidewall surfaces
Side wall；Carry out the first plasma doping process to the second fin of the Part I, first grade from
The dopant ion type of daughter doping treatment is identical with the dopant ion type of the second well region；To described first
The first fin of part carries out the second plasma doping process, and what second plasma doping was processed mixes
Heteroion type is identical with the dopant ion type of the first well region；Carrying out first plasma doping
Process after processing with the second plasma doping, first fin and the second fin are carried out annealing treatment
Reason；Remove first side wall and the second side wall；Remove the first hard mask layer and the second hard mask layer；
Substrate surface forms dielectric layer, and the dielectric layer covers the first fin of Part I side wall and Part I the
Two fin side walls.
The present invention forms the 4th trap using the method that the second plasma doping is processed in Part I fin
Area, it is to avoid the implant damage that ion implantation technology is introduced so that the first fin keep good pattern and compared with
High lattice quality, improves the carrier mobility of channel region in the first fin, and the first well region and the 4th
Well region constitutes SSRW structures, prevents the break-through in source region and drain region in the first fin, it is to avoid the first fin
There is drift in threshold voltage.Likewise, using the method for the first plasma doping process in Part I
The 3rd well region is formed in second fin so that the second fin keeps good pattern and higher lattice quality,
The carrier mobility of channel region in the second fin is improved, and the second well region and the 3rd well region constitute SSRW
Structure, prevents the break-through in source region and drain region in the second fin, it is to avoid the threshold voltage of the second fin occurs drift
Move.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings
The specific embodiment of the present invention is described in detail.
The cross-section structure of the fin field effect pipe forming process that Fig. 1 to Figure 12 is provided for one embodiment of the invention
Schematic diagram.
With reference to Fig. 1, there is provided substrate 101, the substrate 101 includes first area I and second area II,
101 surface of first area I substrates is formed with some the first discrete fins 102, the second area
101 surface of II substrates is formed with some the second discrete fins 103.
The first area I is NMOS area or PMOS area, and the second area II is NMOS
Region or PMOS area.The present embodiment so that the fin field effect pipe that formed is as cmos device as an example, institute
It is NMOS area to state first area I, and the first area I is the region of nmos device to be formed,
The second area II is PMOS area, and the second area II is the region of PMOS device to be formed,
The first area I and second area II are adjacent region.
In other embodiments, the first area can also be PMOS area, corresponding described second
Region is NMOS area.Or, the first area and second area are NMOS area, accordingly
The fin field effect pipe of formation is nmos device.Or, the first area and second area are
PMOS area, the fin field effect pipe being correspondingly formed are PMOS device.
The material of the substrate 101 be silicon, germanium, SiGe, carborundum, GaAs or gallium indium, institute
It can also be the silicon substrate or the germanium substrate on insulator on insulator to state substrate 101.In the present embodiment,
The substrate 101 is silicon substrate.
The first well region (not shown) is formed with the first area I substrates 101, in first well region
Doped with p-type ion, for example, B, Ga or In.The is formed with second area II substrates 101
Doped with N-type ion, for example, P, As or Sb in two well regions (not shown), second well region.
The material of first fin 102 includes silicon, germanium, SiGe, carborundum, GaAs or gallium
Indium；The material of second fin 103 includes silicon, germanium, SiGe, carborundum, GaAs or gallium
Indium.In the present embodiment, the material of first fin 102 is silicon, the material of second fin 103
For silicon.
First fin 102 includes the first fin of Part I 102 positioned at 101 surface of substrate, is located at
First fin of Part II 102 of 102 top surface of the first fin of Part I.Second fin 103
Including the second fin of Part I 103 positioned at 101 surface of substrate, positioned at the second fin of Part I 103
Second fin of Part II 103 of top surface.Wherein, the first fin of the Part I 102 and second
The thickness ratio of the first fin of part 102 is 1/4 to 2/3；The second fin of the Part I 103 and second
The thickness ratio of the second fin of part 103 is 1/4 to 2/3.In the present embodiment, first fin 102 is pushed up
Portion is flushed with the top of the second fin 103, and the thickness of the first fin of the Part I 102 and first
Divide the thickness of the second fin 103 identical.
The processing step for forming the substrate 101, the first fin 102 and the second fin 103 includes：Carry
For initial substrate；The first hard mask layer 104 positioned at first area I is formed in the initial substrate surface
With the second hard mask layer 105 positioned at second area II；It is hard with first hard mask layer 104 and second
Mask layer 105 is initial substrate described in mask etching, and the initial substrate after etching is located at as substrate 101
The projection on 101 surface of first area I substrate as the first fin 102, positioned at second area II substrates 101
The projection on surface is used as the second fin 103.
In one embodiment, form the shape of first hard mask layer 104 and the second hard mask layer 105
Can also include into technique：Self-alignment duplex pattern (SADP, Self-aligned Double Patterned)
Technique, triple graphical (the Self-aligned Triple Patterned) techniques of autoregistration or autoregistration quadruple
Graphical (Self-aligned Double Double Patterned) technique.The Dual graphing technique bag
Include LELE (Litho-Etch-Litho-Etch) techniques or LLE (Litho-Litho-Etch) technique.
In the present embodiment, after first fin 102 and the second fin 103 is formed, reservation is located at
First hard mask layer 104 of 102 top surface of the first fin, retains positioned at 103 top surface of the second fin
The second hard mask layer 105.The material of first hard mask layer 104 is silicon nitride, and described second covers firmly
The material of film layer 105 is silicon nitride.Subsequently when flatening process is carried out, first hard mask layer 104
Can be used as the stop position of flatening process with 105 top surface of the second hard mask layer；Also, it is described
First hard mask layer 104 can also play a part of protect 102 top surface of the first fin, described second
Hard mask layer 105 can also play a part of to protect 103 top surface of the second fin.
In the present embodiment, the top dimension of first fin 102 is less than bottom size, second fin
The top dimension in portion 103 is less than bottom size.In other embodiments, the side wall of first fin is also
Can be perpendicular with substrate surface, i.e., the top dimension of the first fin is equal to bottom size, second fin
The side wall in portion can also be perpendicular with substrate surface, i.e., the top dimension of the second fin is equal to bottom size.
With reference to Fig. 2, oxidation processes are carried out to 102 surface of the first fin and 103 surface of the second fin,
Liner oxidation layer 106 is formed on 102 surface of the first fin and 103 surface of the second fin.
Due to first fin 102, the second fin 103 be by etching to initial substrate after formed, institute
State corner angle of first fin 102 generally with protrusion and surface has defect, second fin 103 leads to
Often there are the corner angle of protrusion and surface has defect, device is affected fin field effect Guan Houhui is subsequently formed
Performance.
Therefore, the present embodiment carries out oxidation processes and is formed linearly to the first fin 102 and the second fin 103
Oxide layer 106, in oxidation processes, due to the specific surface of the faceted portions of the protrusion of the first fin 102
It is bigger, it is easier to be oxidized, after subsequently removing the liner oxidation layer 106, not only the first fin 102
The defect layer on surface is removed, and protrusion faceted portions are also removed, and make the table of first fin 102
Face is smooth, and lattice quality improves, it is to avoid 102 drift angle point discharge problem of the first fin, is conducive to improving
The performance of fin field effect pipe；Likewise, after follow-up removal liner oxidation layer 106, the second fin
The defect layer on 103 surfaces is also removed, and protrusion faceted portions are also removed, and make second fin 103
Surface it is smooth, lattice quality improve, it is to avoid 103 drift angle point discharge problem of the second fin, be conducive to
Improve the performance of fin field effect pipe.
The oxidation processes can adopt the mixed of oxygen plasma oxidation technology or sulphuric acid and hydrogen peroxide
Close solution oxide technique.The oxidation processes can be also aoxidized to 101 surface of substrate so that formation
Liner oxidation layer 106 is also located at 101 surface of substrate.In the present embodiment, using ISSG, (situ steam is given birth to
Into In-situ Stream Generation) oxidation technology enters to the first fin 102 and the second fin 103
Row oxidation processes, form the liner oxidation layer 106, due to the first fin 102 and the second fin 103
Material is silicon, and the material of the liner oxidation layer 106 being correspondingly formed is silicon oxide.
With reference to Fig. 3, expendable film is formed on 101 surface of the substrate, and the expendable film also covers the first fin
103 side wall of 102 side wall of portion and the second fin, at the top of the expendable film higher than at the top of the first fin 102 and
At the top of second fin 103；Planarize the expendable film；It is etched back to remove positioned at the first fin of Part II
The expendable film of 103 sidewall surfaces of 102 sidewall surfaces and the second fin of Part II, in the substrate 101
Surface forms sacrifice layer 108.
In the present embodiment, the expendable film is covered in 106 surface of liner oxidation layer, and the expendable film top
Portion is higher than at the top of the first hard mask layer 104 and the second hard mask layer 105.The expendable film is to be subsequently formed
Sacrifice layer positioned at 101 surface of substrate provides Process ba- sis, is subsequently etched back to remove the sacrifice of segment thickness
Film forms sacrifice layer.
The material of the material of the expendable film and the first fin 102, the second fin 103 and substrate 101 is not
Together, and the expendable film material to be easy to removed material so that the follow-up technique for removing sacrifice layer
Will not the first fin 102 and the second fin 103 be caused to damage.The material of the expendable film be amorphous carbon,
Silicon oxide, silicon nitride, silicon oxynitride, carborundum, silicon oxide carbide or carbon silicon oxynitride.Using chemical gas
Mutually deposition, physical vapour deposition (PVD) or atom layer deposition process form the expendable film.In the present embodiment, institute
The material for stating expendable film is silicon oxide, forms the expendable film using chemical vapor deposition method.
In the present embodiment, the expendable film is planarized using chemical mechanical milling tech, and is planarized described
The stop position of expendable film is at the top of the first hard mask layer 104 and at the top of the second hard mask layer 105.
Mutually tied with wet-etching technology using dry etch process, wet-etching technology or dry etch process
The technique of conjunction, is etched back to remove positioned at 102 sidewall surfaces of the first fin of Part II and Part II second
The expendable film of 103 sidewall surfaces of fin.
The sacrifice layer 108 of formation covers 102 sidewall surfaces of the first fin of Part I, exposes second
Point 102 sidewall surfaces of the first fin, are follow-up to form the in 102 sidewall surfaces of the first fin of Part II
One side wall provides basis.The sacrifice layer 108 covers 103 sidewall surfaces of the second fin of Part I, cruelly
Expose 103 sidewall surfaces of the second fin of Part II, be subsequently in 103 side wall of the second fin of Part II
Surface forms the second side wall and provides basis.
It should be noted that the present embodiment is using depositing operation and is etched back to technique, in substrate surface shape
Into sacrifice layer.In other embodiments, additionally it is possible to directly formed in substrate surface using spin coating process
The sacrifice layer, the material of the sacrifice layer is organic rotary coating (ODL) material or bottom anti-reflective
Penetrate (BARC) material.
With reference to Fig. 4, formed and cover 108 surface of sacrifice layer, 102 side wall table of the first fin of Part II
Face, 103 sidewall surfaces of the second fin of Part II, 104 surface of the first hard mask layer and second are covered firmly
The side wall film 109 on 105 surface of film layer.
The side wall film 109 covers the first of 102 sidewall surfaces of the first fin of Part II to be subsequently formed
Side wall, the second side wall for covering 103 sidewall surfaces of the second fin of Part II provide Process ba- sis.Subsequently
The first side wall formed on the basis of the side wall film 109 needs to have the first fin of Part II 102
Enough protective effects, can stop the plasma in the second follow-up plasma doping processing procedure,
Plasma is avoided to cause unnecessary doping to the first fin of Part II 102.If the side wall film 109
Thickness it is blocked up, then be subsequently etched back to the side wall film 109 and formed needed for the first side wall and the second side wall
Process time is long.For this purpose, the thickness of the side wall film 109 is 3 nanometers to 10 nanometers.The present embodiment
In, the thickness of the side wall film 109 is 7 nanometers to 8 nanometers so that the first side wall for being subsequently formed and
Second side wall has sufficiently strong protective capability, and the process time being etched back to needed for side wall film 109 is moderate.
The material of the side wall film 109 is different from the material of sacrifice layer 108, and the side wall film 109
Material is also different from the material of the first fin 102, the second fin 103.The material of the side wall film 109 is
Silicon oxide, silicon nitride, carborundum, carbonitride of silicium, carbon silicon oxynitride, silicon oxynitride, boron nitride or carbon
Boron nitride；The side wall film 109 is single layer structure or laminated construction.
In the present embodiment, the material of the side wall film 109 is silicon nitride.It is in due to the present embodiment, described
Liner oxidation layer 106, the liner oxidation layer 106 are formed between side wall film 109 and the first fin 102
Material lattice constant between nitridation silicon crystal lattice constant and silicon crystal lattice constant, therefore the liner oxidation
Layer 106 can play transitional function, it is to avoid the excessive problem of the stress that causes as lattice paprmeter is mutated.
In other embodiments, when the first fin and the second fin portion surface do not form liner oxidation layer, then institute
State side wall film the silicon nitride film on silicon oxide film surface is also located at for laminated construction, including silicon oxide film.
With reference to Fig. 5, the side wall for being located at 108 surface of partial sacrificial layer is removed using etching without mask etching technique
Film 109 (referring to Fig. 4), forms the first side wall 119 positioned at 102 sidewall surfaces of the first fin of Part II,
Form the second side wall 129 positioned at 103 sidewall surfaces of the second fin of Part II.
In the present embodiment, using dry etch process, etching is removed at the top of the first hard mask layer 104
The side wall film 109 of 105 top surface of surface and the second hard mask layer, also etching are removed positioned at partial sacrificial layer
The side wall film 109 on 108 surfaces, forms first side wall 119 and the second side wall 129.In the dry method
In etching process, also etching is removed and is covered positioned at 104 top surface of the first hard mask layer and second firmly
The liner oxidation layer 106 of 105 top surface of film layer.
The material of first side wall 119 is silicon oxide, silicon nitride, carborundum, carbonitride of silicium, carbon nitrogen
Silicon oxide, silicon oxynitride, boron nitride or boron carbonitrides；First side wall 119 is single layer structure or folded
Rotating fields.The material of second side wall 129 be silicon oxide, silicon nitride, carborundum, carbonitride of silicium,
Carbon silicon oxynitride, silicon oxynitride, boron nitride or boron carbonitrides；Second side wall 129 is single layer structure
Or laminated construction.
In the present embodiment, the material of first side wall 119 is silicon nitride, second side wall 129
Material is silicon nitride.The thickness of first side wall 119 is 3 nanometers to 10 nanometers so that first
Side wall 119 has stronger protective effect to the first fin of Part II 102, effectively stops follow-up work
Plasma during skill causes unnecessary doping to the first fin of Part II 102；Described second
The thickness of side wall 129 is 3 nanometers to 10 nanometers, effectively stop grade during subsequent technique from
Daughter causes unnecessary doping to the second fin of Part II 103.
It should be noted that being that first side wall 119 is formed in the processing step with along with the present embodiment
With the second side wall 129, in other embodiments, additionally it is possible to successively formed successively first side wall and
Second side wall.
With reference to Fig. 6, the sacrifice layer 108 (referring to Fig. 5) is removed.
In the present embodiment, etching removes the sacrifice layer 108, also etching remove positioned at 101 surface of substrate,
103 sidewall surfaces of 102 sidewall surfaces of the first fin of Part I and the second fin of Part I it is linear
Oxide layer 106 (referring to Fig. 5), exposes 102 sidewall surfaces of the first fin of Part I, also exposes
103 sidewall surfaces of the second fin of Part I.
Mutually tied with wet-etching technology using dry etch process, wet-etching technology or dry etch process
The technique of conjunction, etching remove the sacrifice layer 108 and the liner oxidation layer 106.Positioned at Part II
The liner oxidation layer of 102 sidewall surfaces of the first fin is used as the first linear oxide sidewall spacers 116, the First Line
Property oxide layer 116 be located between the first side wall 119 and the first fin of Part II 102.Positioned at second
The liner oxidation layer of point 103 sidewall surfaces of the second fin as the second liner oxidation side wall 126, described second
Liner oxidation side wall 126 is located between the second side wall 129 and the second fin of Part II 103.
With reference to Fig. 7, formed and cover 101 surface of first area I substrates and the first fin of Part I
First graph layer 110 of 102 sidewall surfaces；With first graph layer 110 as mask, to described first
The second fin of part 103 carries out the first plasma doping process.
In the present embodiment, the material of first graph layer 110 is photoresist.First graph layer 110
104 surface of first side wall 119 and the first hard mask layer is covered also.At first plasma doping
The dopant ion type of reason is identical with the dopant ion type of the second well region.In the present embodiment, described second
Region II is PMOS area, and the dopant ion of second well region is N-type ion, accordingly, described
First plasma doping process dopant ion be N-type ion, the N-type ion be P, As or
Sb。
To the effect that the second fin of Part I 103 carries out the first plasma doping process it is：One side
Face, subsequently after making annealing treatment to the second fin of Part I 103, positioned at Part I second
Dopant ion in fin 103 is spread again, so as to the is formed in the second fin of Part I 103
Three well regions, the 3rd well region can be formed with the source region or drain region that are subsequently formed in the second fin 103
PN junction, forms reverse isolation between the source region and drain region, so as to improve wearing between source region and drain region
Be powered pressure.On the other hand, in the present embodiment, the dopant ion that first plasma doping is processed is dense
Dopant ion concentration of the degree more than second well region, that is to say, that the dopant ion concentration of the 3rd well region
It is more than the dopant ion concentration of the second well region, so as to form the super steep trap that drives in the wrong direction in second area II, described super
Funny retrograde trap can improve the punchthrough issues between source region and drain region, also, can also prevent second area
Dopant ion in II substrates 101 is to 103 internal diffusion of the second fin of Part II, it is to avoid PMOS device
Generation threshold voltage shift.
Meanwhile, compared to ion implantation technology for, the plasma that first plasma doping is processed
Body is less to the bombarding energy of the second fin of Part I 103, therefore at first plasma doping
The lattice damage that reason is caused to the second fin of Part I 103 is little so that the second fin of Part I 103
Remain good performance.Also, ion implantation technology can be subject to injection shadow effect (shadow
Effect) the impact of problem so that the unimplanted ion of some regions in the second fin of Part I；And the
One plasma doping treatment can then avoid the injection shadow effect problem, first plasma
Plasma direction of advance in doping treatment is affected very little by 110 height of the first graph layer, passes through
The first plasma plasma direction of advance is adjusted, 103 quilt of the second fin of Part I is enabled to
Fully adulterate, so as to improve the performance of the 3rd well region being subsequently formed.
In the first plasma doping processing procedure is carried out, second side wall 129 is to Part II
Two fins 103 have enough protective effects, it is to avoid cause unnecessary to the second fin of Part II 103
Doping so that the channel region of PMOS device has higher carrier mobility.
In the present embodiment, the technological parameter that first plasma doping is processed includes：The gas of offer
Including PH3, dopant dose is 1E19atom/cm2To 6E21atom/cm2, radio-frequency power be 500 watts extremely
1500 watts, chamber pressure is 2 millitorrs to 100 millitorrs.After the first plasma doping process is carried out,
In the second fin of the Part I 103, dopant ion is P ion, and dopant ion concentration is 1E19
atom/cm3To 6E21atom/cm3。
After carrying out first plasma doping and processing, using wet method degumming process or cineration technics,
Remove first graph layer 110.
With reference to Fig. 8, formed and cover 101 surface of second area II substrates and the second fin of Part I
The second graph layer 111 in portion 103；With the second graph layer 111 as mask, carry out second grade from
Daughter doping treatment.
In the present embodiment, the material of the second graph layer 111 is photoresist.The second graph layer 110
105 surface of second side wall 129 and the second hard mask layer is covered also.
Dopant ion type and the dopant ion type of the first well region that second plasma doping is processed
It is identical.In the present embodiment, the first area I is NMOS area, the doping of first well region from
Son is p-type ion, and accordingly, the dopant ion that second plasma doping is processed is p-type ion,
The p-type ion is B, Ga or In.
To the effect that the first fin of Part I 103 carries out the second plasma doping process it is：One side
Face, subsequently after making annealing treatment to the first fin of Part I 102, positioned at Part I first
Dopant ion in fin 102 is spread again, so as to the is formed in the first fin of Part I 102
Four well regions, the 4th well region can be formed with the source region or drain region that are subsequently formed in the first fin 102
PN junction, forms reverse isolation between the source region and drain region, so as to improve wearing between source region and drain region
Be powered pressure.On the other hand, in the present embodiment, the dopant ion that second plasma doping is processed is dense
Dopant ion concentration of the degree more than first well region, that is to say, that the dopant ion of the 4th well region
Dopant ion concentration of the concentration more than the first well region, it is so as to form the super steep trap that drives in the wrong direction in first area I, described
The punchthrough issues that the super steep trap that drives in the wrong direction can improve between source region and drain region, and also it is prevented from first area I
Dopant ion in substrate 101 is to 102 internal diffusion of the first fin of Part II, it is to avoid nmos device is sent out
Raw threshold voltage shift.
Meanwhile, compared to ion implantation technology for, the plasma that second plasma doping is processed
Body is less to the bombarding energy of the first fin of Part I 102, therefore at second plasma doping
The lattice damage that reason is caused to the first fin of Part I 102 is little so that the first fin of Part I 102
Remain good performance.Also, the process of the second plasma doping can avoid injecting shadow effect
Problem, the plasma direction of advance during second plasma doping is processed are subject to second graph layer 111
The impact very little of height, processes plasma direction of advance, energy by adjusting the second plasma doping
Enough so that the first fin of Part I 102 is fully adulterated, so as to improve the 4th well region being subsequently formed
Performance.
In the second plasma doping processing procedure is carried out, first side wall 119 is to Part II
One fin 102 provides enough protective effects, it is to avoid cause unnecessary to the first fin of Part II 102
Doping so that formed nmos device channel region there is higher carrier mobility.
In the present embodiment, the technological parameter that second plasma doping is processed includes：The gas of offer
Including BF3Or B2H6, dopant dose is 1E19atom/cm2To 5E21atom/cm2, radio-frequency power is
200 watts to 1000 watts, chamber pressure is 2 millitorrs to 10 millitorrs.Carrying out at the second plasma doping
After reason, in the first fin of the Part I 102, dopant ion is B ions, and dopant ion concentration is
1E19atom/cm3To 5E21atom/cm3。
After carrying out second plasma doping and processing, removed photoresist using wet method or cineration technics, gone
Except the second graph layer 111.
It should be noted that the present embodiment is carrying out second etc. after first carrying out the first plasma doping process
As a example by gas ions doping treatment, in other embodiments, it is also possible to first carry out at the second plasma doping
The first plasma is carried out after reason.
In another embodiment, using without mask etching technique, first side wall and second are successively formed
Side wall；First side wall, the second side wall are formed, the first plasma doping process is carried out and carries out
The processing step of two plasma doping treatments can also include：After the side wall film is formed, formed
Cover first graph layer on the first area side wall film surface；With first graph layer as mask, adopt
The side wall film for being located at second area partial sacrifice layer surface is removed with etching without mask etching technique, institute is formed
State the second side wall；Etching removes the sacrifice layer positioned at second area, exposes the second fin of Part I side
Wall surface；First plasma doping process is carried out to the second fin of the Part I；Remove described
One graph layer；Formed and cover second area substrate surface, the second fin of Part I and the second side wall
Second graph layer；Removed positioned at first area partial sacrifice layer surface using etching without mask etching technique
Side wall film, forms second side wall；Etching removes the sacrifice layer positioned at first area, exposes described
Part I the first fin sidewall surfaces；The second plasma is carried out to the first fin of the Part I to mix
Live together reason；Remove the second graph layer.
With reference to Fig. 9, it is processed with the second plasma doping the first plasma doping process is carried out
Afterwards, annealing 112 is carried out to first fin 102 and the second fin 103.
It is described annealing 112 effect be：Make the dopant ion in the first fin of Part I 102
Spread again and concentration redistribution, so as to form the 4th well region in the first fin of Part I 102；
Make the dopant ion in the second fin of Part I 103 spread again and concentration redistribution, so as to
The 3rd well region is formed in the second fin of Part I 103.
Dopant ion concentration of the dopant ion concentration of the 4th well region more than the first well region, the described 3rd
Dopant ion concentration of the dopant ion concentration of well region more than the second well region.In the present embodiment, in order to prevent
Dopant ion in the first fin of Part I 102 prevents the second fin of Part I 103 to external diffusion
Interior dopant ion to external diffusion, before the annealing 112 is carried out, in first fin 102
103 sidewall surfaces deposit passivation layer 113 of sidewall surfaces and the second fin, the passivation layer 113 can stop
Dopant ion outwardly spreads, and reduces the dopant ion concentration loss in the first fin of Part I 102,
Reduce the dopant ion concentration loss in the second fin of Part I 103.
In the present embodiment, the material of the passivation layer 113 is silicon oxide, using chemical vapor deposition method
Form the passivation layer 113.
With reference to Figure 10, deielectric-coating 114 is formed on 101 surface of the substrate, the deielectric-coating 114 is covered
102 sidewall surfaces of the first fin of Part I, 103 sidewall surfaces of the second fin of Part I, the first side
129 sidewall surfaces of 119 sidewall surfaces of wall and the second side wall, and be higher than first at the top of the deielectric-coating 114
At the top of fin 102 and at the top of the second fin 103.
In the present embodiment, the dielectric layer 114 is located at 113 surface of passivation layer, and deielectric-coating 114 is follow-up shape
Isolation structure into fin field effect pipe provides Process ba- sis.The material of deielectric-coating 114 is insulant,
For example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxide carbide, carbonitride of silicium or carbon silicon oxynitride.This
In embodiment, the material of deielectric-coating 114 is silicon oxide.
In order to improve filling perforation (gap-filling) ability of deielectric-coating 114 so that the dielectric layer being subsequently formed
Contact closely, and avoid the medium being subsequently formed with 102 bottom of the first fin, 103 bottom of the second fin
Cavity is formed in layer, is formed using mobility chemical vapor deposition (FCVD, Flowable CVD) technique
The deielectric-coating 114.During mobility chemical vapor deposition method is carried out, substrate 101 is maintained at
Within the scope of predetermined temperature, the pre-reaction material material of mobility chemical vapor deposition method is enable to flow
Be filled into opening in, so as to formed filling full gate mouth precursor material layer.Particularly, relatively low lining
101 temperature of bottom (being less than 150 DEG C) can keep stream of the pre-reaction material material in substrate 101 and opening
Dynamic property and viscosity.As pre-reaction material material has certain mobility and viscosity, will with flowing
Property pre-reaction material material be packed into opening in after, open bottom carried out without cavity filling, so as to keep away
Exempt to produce cavity in open bottom.
In the present embodiment, after deielectric-coating 114 is formed, also including step：To the deielectric-coating 114
Annealing cured is carried out, the annealing cured is carried out under oxygen-containing atmosphere.In cured process
In, chemical bond restructuring in deielectric-coating 114, the Si-O keys, O-Si-O keys in deielectric-coating 114 increase, and
It is improved the consistency of deielectric-coating 114.In the present embodiment, the process temperature of the annealing cured
Spend for 650 degrees Celsius to 1100 degrees Celsius.
With reference to Figure 11, the deielectric-coating 114 (referring to Figure 10) is planarized；It is etched back to remove segment thickness
Deielectric-coating 114, forms dielectric layer 115 on 101 surface of the substrate.
In the present embodiment, the stop position for planarizing the deielectric-coating 114 is pushed up for the first hard mask layer 104
Portion surface.Specifically, using chemical mechanical milling tech, remove higher than first hard mask layer 104
The deielectric-coating 114 of top surface.
The dielectric layer 114 covers 102 sidewall surfaces of the first fin of Part I and the second fin of Part I
103 sidewall surfaces of portion.Carved using dry etch process, wet-etching technology or dry etching and wet method
The technique that erosion combines, is etched back to remove the deielectric-coating 114 of segment thickness.The dielectric layer 115 is used for shape
Into the isolation structure of fin field effect pipe, as the cavity in the deielectric-coating 114 that is previously formed is few, and it is situated between
114 formation process of plasma membrane have higher filling perforation performance, therefore in the present embodiment fin field effect pipe every
There are stronger electrical isolation capabilities from structure.
The dielectric layer 114 exposes 129 sidewall surfaces of 119 sidewall surfaces of the first side wall and the second side wall,
The first side wall 119 is removed for subsequent etching and the second side wall 129 provides Process ba- sis.
Also include step：Remove the passivation layer 113 higher than 114 top surface of dielectric layer；Remove positioned at first
First hard mask layer 104 of 102 top surface of fin；Remove the positioned at 103 top surface of the second fin
Two hard mask layers 105.In the present embodiment, to avoid subsequently removing the first side wall 119 and the second side wall 129
Technique to causing at the top of the first fin 102 and at the top of the second fin 103 to damage, only remove segment thickness
The first hard mask layer 104 and the second hard mask layer 105.
With reference to Figure 12, the 129 (reference of first side wall 119 (referring to Figure 11) and the second side wall is removed
Figure 11).
In the present embodiment, first side wall 119 and the second side wall are removed using wet-etching technology etching
129, the etch liquids that wet-etching technology is adopted are for phosphoric acid solution.First side wall 119 is removed in etching
During the second side wall 129, also etching removes remaining first hard mask layer 104 (referring to Figure 11)
With remaining second hard mask layer 105 (referring to Figure 11).Also etching removes the first linear oxide sidewall spacers 116
(referring to Figure 11) and the second liner oxidation side wall 126 (referring to Figure 11), exposes the Part II
103 sidewall surfaces of one fin, 102 sidewall surfaces and the second fin of Part II.
In the present embodiment, 102 bottom of the first fin of Part II, institute at the top of the dielectric layer 115, are less than
State.In other embodiments, it is described
Can also flush with the first fin of Part II bottom at the top of dielectric layer, can also at the top of the dielectric layer
It is enough to flush with the second fin of Part II bottom.
It is plasma doping process that the present embodiment forms the method for the 4th well region in the first fin 102,
Avoid the implant damage problem of ion implantation technology introducing so that the first fin 102 keeps good shape
Looks and with higher lattice quality so that the anti-punch through effect that the 4th well region is played is higher.And also avoid
To unnecessary doping being carried out higher than first fin 102 at the top of dielectric layer 115, improve NMOS
Device channel region carrier mobility.
The dopant ion concentration of the 4th well region more than the first well region dopant ion concentration, so as to
The super steep trap that drives in the wrong direction is formed in nmos device, the super steep trap that drives in the wrong direction can improve to form the first fin 102
Punch through voltage between interior source region and drain region, is prevented with this between source region and drain region in the first fin 102
Generation break-through, and prevent the dopant ion in substrate 101 to 102 internal diffusion of the first fin, prevent NMOS
The threshold voltage shift of device so that the mismatch (Mismatch) of device is good, therefore semiconductor device is equal
Even property improves, can for example improve pull up in SRAM device (PU) transistor AND gate pull up transistor between,
Electrical parameter mismatch between drop-down (PD) transistor AND gate pull-down transistor, wherein, electrical parameter can
For threshold voltage (Vt), saturation current (Idast) etc..
It is plasma doping process that the present embodiment forms the method for the 3rd well region in the second fin 103,
Avoid the implant damage problem of ion implantation technology introducing so that the second fin 103 keeps good shape
Looks and with higher lattice quality so that the anti-punch through effect that the 3rd well region is played is higher.And also avoid
To unnecessary doping being carried out higher than second fin 103 at the top of dielectric layer 115, improve PMOS
Device channel region carrier mobility.
The dopant ion concentration of the 3rd well region more than the second well region dopant ion concentration, so as to
The super steep trap that drives in the wrong direction is formed in PMOS device, the super steep trap that drives in the wrong direction can improve to form the second fin 103
Punch through voltage between interior source region and drain region, is prevented with this between source region and drain region in the second fin 103
Generation break-through, and prevent the dopant ion in substrate 101 to 103 internal diffusion of the second fin, prevent PMOS
The threshold voltage shift of device so that the mismatch (Mismatch) of device is good, therefore semiconductor device is equal
Even property improves, can for example improve pull up in SRAM device (PU) transistor AND gate pull up transistor between,
Electrical parameter mismatch between drop-down (PD) transistor AND gate pull-down transistor, wherein, electrical parameter can
For threshold voltage (Vt), saturation current (Idast) etc..
Follow-up processing step also includes：The first grid structure of first fin 102 is developed across,
The first grid structure covers 102 atop part of the first fin and side wall；In the first grid structure
Source region is formed in first fin 102 of side, in the first fin 102 of the opposite side relative with the side
Interior formation drain region；It is developed across the second grid structure of second fin 103, the second grid knot
Structure covers 103 atop part of the second fin and side wall；In the second fin of the second grid structure side
Source region is formed in 103, drain region is formed in the second fin 102 of the opposite side relative with the side.
The section of the fin field effect pipe forming process that Figure 13 to Figure 14 is provided for another embodiment of the present invention
Structural representation.
From unlike previous embodiment, the present embodiment the second fin of Part I is carried out the first grade from
Before daughter doping treatment, enter line width cutting process to the second fin of the Part I, reduce first
Part the second fin width size；Second plasma doping process is being carried out to the first fin of Part I
Before, enter line width cutting process to the first fin of the Part I, reduce the first fin of Part I
Width dimensions.
Hereinafter the forming method of the fin field effect pipe provided to the present embodiment is described in detail.
With reference to referring to figs. 1 to Fig. 7 and Figure 13, to the second fin of Part I 103 and Part I
First fin 102 carries out oxidation processes, and first fin of Part I 102 of partial width is converted into
Second fin of Part I 103 of partial width is converted into the second oxide layer 113 by one oxide layer 112.
The technique that the oxidation processes are adopted is dry oxygen technique or wet oxygen technique.In the present embodiment, using ISSG
Technique carries out the oxidation processes, and ISSG technological parameters include：O is provided2And H2, O2Flow is 1sccm
To 30sccm, H2Flow is 1.5sccm to 15sccm, and chamber temp taken the photograph for 700 degrees Celsius to 1200
Family name's degree.
The width dimensions of first oxide layer 112 are 1 nanometer to 2 nanometers；Second oxide layer 113
Width dimensions be 1 nanometer to 2 nanometers.Wherein, width dimensions are referred to and are cutd open illustrated in fig. 13
On the structural representation of face, positioned at 112 broad-ruler of the first oxide layer of 102 one side of the first fin of Part I
It is very little, and positioned at 113 width dimensions of the second oxide layer of 103 one side of the second fin of Part I.
With reference to Figure 14, etching removes first oxide layer 112 (referring to Figure 13) and the second oxide layer 113
(referring to Figure 13).
In the present embodiment, using wet-etching technology, etching removes first oxide layer 112 and second
Oxide layer 113, the etch liquids that wet-etching technology is adopted are for hydrofluoric acid solution.
Follow-up processing step includes：First plasma is carried out to the second fin of the Part I 103
Doping treatment, the doping of the dopant ion type that first plasma doping is processed and the second well region from
Subtype is identical；Second plasma doping process, institute are carried out to the first fin of the Part I 102
The dopant ion type for stating the process of the second plasma doping is identical with the dopant ion type of the first well region；
Process and after the second plasma doping is processed first plasma doping is carried out, to described the
One fin 102 and the second fin 103 are made annealing treatment；Remove first side wall 119 and the second side
Wall 129；Remove first hard mask layer 104 and the second hard mask layer 105；In 101 table of the substrate
Face forms dielectric layer, and the dielectric layer covers 102 side wall of the first fin of Part I and Part I second
103 side wall of fin.
As the width dimensions of the second fin of Part I 103 reduce so that at the first plasma doping
The dopant ion of reason is more easy to be doped the second fin of Part I 103 so that the second fin of Part I
Dopant ion concentration distribution in portion 103 is evenly.Also, the second fin of Part I 103 is being entered
After row annealing, the dopant ion in the second fin of Part I 103 is spread again with concentration again
Distribution, so as to form the 3rd well region in the second fin 103, due to the second fin of Part I 103
Width dimensions reduce so that control of the follow-up second grid structure formed in second area II to the 3rd well region
Ability processed is higher so that what the 3rd well region played a part of prevents punch through between source region and drain region more aobvious
Write.Therefore, the present embodiment can further improve the punch through voltage between source region and drain region, so as to enter one
Step improves the electric property of the fin field effect pipe for being formed.
As the width dimensions of the first fin of Part I 102 reduce so that at the second plasma doping
The dopant ion of reason is more easy to be doped the first fin of Part I 102 so that the first fin of Part I
Dopant ion concentration distribution in portion 102 is evenly.Also, the first fin of Part I 102 is being entered
After row annealing, the dopant ion in the first fin of Part I 102 is spread again with concentration again
Distribution, so as to form the 4th well region in the first fin 102, due to the first fin of Part I 102
Width dimensions reduce so that control of the follow-up first grid structure formed in first area I to the 4th well region
Ability is higher so that what the 4th well region played a part of prevents punch through between source region and drain region more notable.
Therefore, the present embodiment can further improve the punch through voltage between source region and drain region, so as to further change
The electric property of the kind fin field effect pipe for being formed.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (20)
1. a kind of forming method of fin field effect pipe, it is characterised in that include：
Offer includes the substrate of first area and second area, is formed with first in the first area substrate
Well region, is formed with the second well region in the second area substrate, the first area substrate surface is formed with
First fin, the first fin top surface are formed with the first hard mask layer, the second area substrate
Surface is formed with the second fin, and the second fin top surface is formed with the second hard mask layer, wherein,
First fin is included positioned at first fin of Part I of substrate surface and positioned at Part I first
First fin of Part II of fin top surface, second fin include positioned at substrate surface first
The second fin of part and the second fin of Part II positioned at Part I the second fin top surface；
The first side wall is formed in the first fin of Part II sidewall surfaces；
The second side wall is formed in the second fin of Part II sidewall surfaces；
The first plasma doping process, first plasma are carried out to the second fin of the Part I
The dopant ion type of body doping treatment is identical with the dopant ion type of the second well region；
The second plasma doping process, second plasma are carried out to the first fin of the Part I
The dopant ion type of body doping treatment is identical with the dopant ion type of the first well region；
After the first plasma doping process and the process of the second plasma doping is carried out, to institute
State the first fin and the second fin is made annealing treatment；
Remove first side wall and the second side wall；
Remove first hard mask layer and the second hard mask layer；
Form dielectric layer in the substrate surface, the dielectric layer cover the first fin of Part I side wall and
The second fin of Part I side wall.
2. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that described first etc.
Dopant ion concentration of the dopant ion concentration of gas ions doping treatment more than second well region；It is described
The dopant ion concentration of the second plasma doping process is dense more than the dopant ion of first well region
Degree.
3. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that firstth area
Domain is NMOS area, and the dopant ion that second plasma doping is processed is p-type ion；Institute
It is PMOS area to state second area, and the dopant ion that first plasma doping is processed is N-type
Ion.
4. the forming method of fin field effect pipe as claimed in claim 3, it is characterised in that described first etc.
The technological parameter of gas ions doping treatment includes：The gas of offer includes PH3, dopant dose is 1E19
atom/cm2To 6E21atom/cm2, radio-frequency power is 500 watts to 1500 watts, and chamber pressure is 2
Millitorr is to 100 millitorrs.
5. the forming method of fin field effect pipe as claimed in claim 3, it is characterised in that described second etc.
The technological parameter of gas ions doping treatment includes：The gas of offer includes BF3Or B2H6, dopant dose
For 1E19atom/cm2To 5E21atom/cm2, radio-frequency power is 200 watts to 1000 watts, chamber pressure
It is by force 2 millitorrs to 10 millitorrs.
6. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that carry out it is described
Before the process of first plasma doping, enter line width cutting process to the second fin of the Part I,
Reduce Part I the second fin width size；Before the second plasma doping process is carried out,
Enter line width cutting process to the first fin of the Part I, reduce the first fin width of Part I
Size.
7. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that to described first
The second fin of part, the first fin of Part I enter the processing step of line width cutting process to be included：It is right
The second fin of the Part I and the first fin of Part I carry out oxidation processes, by partial width
The first fin of Part I is converted into the first oxide layer, and second fin of Part I of partial width is turned
Turn to the second oxide layer；Etching removes first oxide layer and the second oxide layer.
8. the forming method of fin field effect pipe as claimed in claim 7, it is characterised in that at the oxidation
The technological parameter of reason includes：O is provided2And H2, O2Flow is 1sccm to 30sccm, H2Flow is
1.5sccm to 15sccm, chamber temp are 700 degrees Celsius to 1200 degrees Celsius.
9. the forming method of fin field effect pipe as claimed in claim 7, it is characterised in that first oxygen
The width dimensions for changing layer are 1 nanometer to 2 nanometers；The width dimensions of second oxide layer are 1 nanometer
To 2 nanometers.
10. the forming method of fin field effect pipe as claimed in claim 1, it is characterised in that described annealing treatment
The annealing temperature of reason is 900 degrees Celsius to 1100 degrees Celsius.
The forming method of 11. fin field effect pipes as claimed in claim 1, it is characterised in that first side
The material of wall be silicon oxide, silicon nitride, carborundum, carbonitride of silicium, carbon silicon oxynitride, silicon oxynitride,
Boron nitride or boron carbonitrides；The material of second side wall is silicon oxide, silicon nitride, carborundum, carbon
Silicon nitride, carbon silicon oxynitride, silicon oxynitride, boron nitride or boron carbonitrides.
The forming method of 12. fin field effect pipes as claimed in claim 1, it is characterised in that form described the
The processing step of one side wall and the second side wall includes：Sacrifice layer is formed in the substrate surface, it is described sacrificial
Domestic animal layer covers Part I the first fin sidewall surfaces and Part I the second fin sidewall surfaces；
The sacrificial layer surface, Part II the second fin sidewall surfaces, the first fin of Part II side wall table
Face, the first hard mask layer surface and the second hard mask layer surface form side wall film；Using carving without mask
Etching technique etching removes the side wall film positioned at partial sacrifice layer surface, is formed positioned at the first fin of Part II
First side wall of portion's sidewall surfaces, forms the second side wall positioned at Part II the second fin sidewall surfaces；
Remove the sacrifice layer.
The forming method of 13. fin field effect pipes as claimed in claim 12, it is characterised in that the sacrifice layer
Material be silicon oxide, amorphous carbon, organic rotary coating material or bottom anti-reflective material.
The forming method of 14. fin field effect pipes as claimed in claim 12, it is characterised in that applied using rotation
Coating process forms the sacrifice layer；Or, using depositing operation and it is etched back to technique and forms described sacrificial
Domestic animal layer.
The forming method of 15. fin field effect pipes as claimed in claim 12, it is characterised in that using without mask
Etching technics, while forming first side wall and the second side wall.
The forming method of the 16. fin field effect pipes as described in claim 1 or 15, it is characterised in that described
The processing step of one plasma doping treatment includes：Formed cover the first area substrate surface with
And the first graph layer of Part I the first fin sidewall surfaces；With first graph layer as mask,
Carry out first plasma doping to process；Remove first graph layer.
The forming method of the 17. fin field effect pipes as described in claim 1 or 15, it is characterised in that described
The processing step of two plasma doping treatments includes：Formed cover the second area substrate surface with
And the second graph layer of the second fin of Part I；With the second graph layer as mask, carry out described
The process of second plasma doping；Remove the second graph layer.
The forming method of 18. fin field effect pipes as claimed in claim 12, it is characterised in that using without mask
Etching technics, successively forms first side wall and the second side wall；Formed first side wall, second
Side wall, the technique step for carrying out the first plasma doping process, carrying out the second plasma doping process
Suddenly include：After the side wall film is formed, formed and cover the of the first area side wall film surface
One graph layer；Removed positioned at second area partial sacrifice layer surface using etching without mask etching technique
Side wall film, forms second side wall；Etching removes the sacrifice layer positioned at second area, exposes the
A part of second fin sidewall surfaces；The first plasma is carried out to the second fin of the Part I to mix
Live together reason；Remove first graph layer；Formed and cover second area substrate surface, Part I the
The second graph layer of two fins and the second side wall；Using removing positioned at the without mask etching technique etching
The side wall film of one region partial sacrifice layer surface, forms second side wall；Etching is removed positioned at first
The sacrifice layer in region, exposes the Part I the first fin sidewall surfaces；To the Part I
First fin carries out the second plasma doping process；Remove the second graph layer.
The forming method of 19. fin field effect pipes as claimed in claim 1, it is characterised in that formation is given an account of
Matter layer, removal first side wall and the second side wall, removal first hard mask layer and second are covered firmly
The processing step of film layer includes：Deielectric-coating is formed in the substrate surface, the deielectric-coating covers first
Part the first fin side wall, the second fin of Part I side wall, the first side wall surface and the second side wall
Surface, higher than at the top of the first hard mask layer at the top of the deielectric-coating；Remove higher than the first hard mask layer top
Deielectric-coating at the top of portion and the second hard mask layer；Remove first hard mask layer and the second hard mask layer；
The deielectric-coating for being etched back to remove segment thickness forms dielectric layer, and the dielectric layer exposes the first side wall side
Wall surface and the second side wall sidewall surfaces；Remove first side wall and the second side wall.
The forming method of 20. fin field effect pipes as claimed in claim 1, it is characterised in that described being formed
Before first side wall and the second side wall, formed and cover the first fin sidewall surfaces and the second fin side
The liner oxidation layer of wall surface, wherein, positioned at the liner oxidation of Part II the first fin sidewall surfaces
Layer is located at the first side wall and second as the first linear oxide sidewall spacers, the first linear oxide sidewall spacers
Between point the first fin, the liner oxidation layer positioned at Part II the second fin sidewall surfaces is used as second
Linear side wall, the second liner oxidation side wall are located between the second fin of the second side wall and Part II.
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| CN201510631672.7A CN106558555A (en) | 2015-09-29 | 2015-09-29 | The forming method of fin field effect pipe |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112447519A (en) * | 2019-09-04 | 2021-03-05 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN112864227A (en) * | 2021-03-30 | 2021-05-28 | 长江存储科技有限责任公司 | Fin type field effect transistor and manufacturing method thereof |
| CN113889527A (en) * | 2021-09-06 | 2022-01-04 | 上海集成电路装备材料产业创新中心有限公司 | Fin transistor with optimized fin appearance and manufacturing method |
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| CN113889527A (en) * | 2021-09-06 | 2022-01-04 | 上海集成电路装备材料产业创新中心有限公司 | Fin transistor with optimized fin appearance and manufacturing method |
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