CN104347416A - Finned field-effect transistor (FET) and forming method thereof - Google Patents
Finned field-effect transistor (FET) and forming method thereof Download PDFInfo
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- CN104347416A CN104347416A CN201310338358.0A CN201310338358A CN104347416A CN 104347416 A CN104347416 A CN 104347416A CN 201310338358 A CN201310338358 A CN 201310338358A CN 104347416 A CN104347416 A CN 104347416A
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- 230000005669 field effect Effects 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000000463 material Substances 0.000 claims description 111
- 230000003647 oxidation Effects 0.000 claims description 73
- 238000007254 oxidation reaction Methods 0.000 claims description 73
- 230000015572 biosynthetic process Effects 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000004062 sedimentation Methods 0.000 claims description 8
- 239000007864 aqueous solution Substances 0.000 claims description 6
- 238000011065 in-situ storage Methods 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 229910052732 germanium Inorganic materials 0.000 claims description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 5
- OQNXPQOQCWVVHP-UHFFFAOYSA-N [Si].O=[Ge] Chemical compound [Si].O=[Ge] OQNXPQOQCWVVHP-UHFFFAOYSA-N 0.000 claims description 4
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 claims description 4
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 239000004065 semiconductor Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000002353 field-effect transistor method Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000005265 energy consumption Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 230000027756 respiratory electron transport chain Effects 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention relates a finned field-effect transistor (FET) and a forming method thereof. The finned FET comprises a substrate, oxide fin parts, second fin parts, gate oxide layers and a grid electrode, wherein the oxide fin parts are located on the substrate; the second fin parts are located on the oxide fin parts, and the width of the second fin parts is greater than that of the oxide fin parts; the gate oxide layers are located on the exposed surfaces of the second fin parts; the grid electrode spans the oxide fin parts and the second fin parts. The finned FET provided by the invention has the advantages that the relative area of the grid electrode and the second fin parts is large, the power consumption is low, and the thickness of the gate oxide layers is uniform.
Description
Technical field
The present invention relates to semiconductor applications, be related specifically to a kind of fin formula field effect transistor and forming method thereof.
Background technology
Along with the development of semiconductor technology, the critical size of semiconductor device is constantly reducing.When the critical size of device continues to reduce, conventional MOS field-effect transistor can cause the shortcomings such as short-channel effect because critical size is too little.Fin formula field effect transistor (FinFET) is owing to having larger channel region; And grid is relative with two side with the upper surface of fin, increase the relative area of grid and fin, grid well can control the channel region formed in fin, can effectively overcome short-channel effect and be widely used.
In prior art, the formation method of fin formula field effect transistor comprises:
With reference to figure 1, provide substrate 10.
With reference to figure 2, described substrate 10 forms fin 11.
The method forming described fin 11 is: in described substrate 10, form patterned mask layer, the position of described patterned mask layer definition fin; Then with described patterned mask layer for mask, the described substrate 10 of etched portions thickness, forms fin 11, and removes described patterned mask layer.
After forming fin 11, use sedimentation, described fin 11 and substrate 10 form gate dielectric layer (not shown).
With reference to figure 3, described gate dielectric layer forms grid 20, described grid 20 is across described fin 11.
After forming grid 20, also comprise and form source electrode and drain electrode (not shown).
When the critical size of fin formula field effect transistor continues to reduce, the fin formula field effect transistor formed by said method has following shortcoming:
The first, grid 20 is still less with the relative area of fin 11, and grid 20 well can not control the channel region formed in fin 11.
The second, power consumption is large.The channel region formed in fin 11 increases, and can improve the drive current of fin formula field effect transistor, but after drive current is increased to certain value, can increase the power consumption of described fin formula field effect transistor on the contrary; Electric current between source electrode and drain electrode by substrate 10 and mutual conduction, can increase the power consumption of described fin formula field effect transistor further.
3rd, along with the reduction of fin 11 width, the uneven thickness one of the gate dielectric layer using sedimentation to be formed at fin 11 upper surface and sidewall.
Summary of the invention
The problem that the present invention solves is in prior art, the grid of fin formula field effect transistor with the relative area of fin is less, power consumption greatly and the uneven thickness one of gate dielectric layer.
For solving the problem, the invention provides a kind of formation method of fin formula field effect transistor, comprising: substrate is provided; Form the first fin and the second fin from the bottom to top successively on the substrate, the width of the first fin is less than the width of the second fin; Be oxidized described first fin and form oxidation fin; Be oxidized the surface that described second fin exposes, the surface exposed at described second fin forms grid oxide layer; After forming oxidation fin and grid oxide layer, form the grid across described oxidation fin and the second fin.
Optionally, the method forming the first fin and the second fin comprises: form the first fin material layer on the substrate, and the first fin material layer is formed the second fin material layer; Patterned mask layer is formed at described second fin material layer upper surface; With described patterned mask layer for mask, etch described second fin material layer and the first fin material layer, form the second identical fin of width and the first fin; First fin described in lateral etching part, makes the width of the first fin be less than the width of the second fin.
Optionally, the material of described first fin is silicon, and the material of described second fin is SiGe, and described in lateral etching part, the method for the first fin is: use CF
4, O
2and N
2plasma plasma etching is carried out to described first fin; Or, use HNO
3with the aqueous solution of HF, wet etching is carried out to described first fin.
Optionally, the material of described first fin is SiGe, and the material of described second fin is silicon, and described in lateral etching part, the method for the first fin is: use CF
4plasma plasma etching is carried out to described first fin; Or, use the aqueous solution of HCl to carry out wet etching to described first fin.
Optionally, the method forming the first fin material layer comprises: use sedimentation or epitaxial growth method, form the first fin material layer on the substrate.
Optionally, the method forming the second fin material layer comprises: use sedimentation or epitaxial growth method, described first fin material layer forms the second fin material layer.
Optionally, also comprise: during formation first fin material layer, use and in-situ doped first kind doping is carried out to described first fin material layer; Or, after forming the first fin material layer, before forming the second fin material layer, first kind doping is carried out to described first fin material layer.
Optionally, also comprise: during formation second fin material layer, use in-situ doped, carry out Second Type doping to the second fin material layer, Second Type is identical with the first kind, and the concentration of Second Type doping is less than the concentration of first kind doping; Or after forming the second fin material layer, carry out Second Type doping to the second fin material layer, Second Type is identical with the first kind, and the concentration of Second Type doping is less than the concentration of first kind doping.
Optionally, also comprise before forming described grid: form side wall at described first fin sidewall, the height of described side wall is less than or equal to the height of described first fin.
The present invention also provides a kind of fin formula field effect transistor, comprising: substrate; Be positioned at described suprabasil oxidation fin; Be positioned at the second fin on described oxidation fin, the width of described second fin is greater than the width of described oxidation fin; Be positioned at the grid oxide layer on the surface that described second fin exposes; Across the grid of described oxidation fin and the second fin.
Optionally, the material of described oxidation fin is silica, germanium oxide or silicon germanium oxide.
Optionally, the material of described second fin is germanium, SiGe or silicon.
Optionally, oxidation fin has first kind doping, and the second fin has Second Type doping, and Second Type is identical with the first kind, and the concentration of Second Type doping is less than the concentration of first kind doping.
Optionally, also comprise: the side wall being positioned at described oxidation fin sidewall, the height of described side wall is less than or equal to the height of described oxidation fin.
Compared with prior art, technical scheme of the present invention has the following advantages:
The second fin that fin formula field effect transistor comprises oxidation fin and is positioned on described oxidation fin, and the width of described oxidation fin is less than the width of described second fin, this fin formula field effect transistor at least has the following advantages:
The first, the relative area of grid and the second fin is improved.In prior art, the surface that fin exposes only has upper surface and the two side of fin.In the technical program, because the width being oxidized fin is less than the width of the second fin, so the surface that described second fin exposes not only comprises upper surface and the two side of the second fin, also comprise not by the lower surface that described oxidation fin covers, the surface area that described second fin exposes increases.After forming grid, because grid and the lower surface of the second fin do not covered by described oxidation fin also have relative area, the relative area of grid and the second fin increases, and grid well can control the channel region formed in the second fin.
The second, power consumption is little.Fin formula field effect transistor can by the height of adjustment second fin, and then regulate the drive current of described fin formula field effect transistor, described drive current is made to be a preferred values, the better operating state of described fin formula field effect transistor can either be kept, the power consumption of described fin formula field effect transistor can not be made again to increase; And described oxidation fin makes described second fin and described substrate be spaced from each other, prevent source electrode and drain electrode between electric current by described substrate conducting, reduce the power consumption of described fin formula field effect transistor.
3rd, the surface that the technical program adopts described second fin of oxidation to expose, the surface exposed at described second fin forms grid oxide layer, and the thickness of grid oxide layer is homogeneous.
Accompanying drawing explanation
Fig. 1 to Fig. 3 is the perspective view of each production phase of preparing fin formula field effect transistor method in prior art;
Fig. 4 to Figure 11 is the perspective view of each production phase of preparing fin formula field effect transistor method in first embodiment of the invention;
Figure 12 is the perspective view of each production phase of preparing fin formula field effect transistor method in second embodiment of the invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
First embodiment
The present embodiment provides a kind of formation method of fin formula field effect transistor, and the method comprises:
With reference to figure 4, provide substrate 110.
In a particular embodiment, the material of described substrate 110 can be the semi-conducting material of the routines such as silicon, germanium, SiGe, silicon-on-insulator (silicon on insulator is called for short SOI).
Then, described substrate 110 forms oxidation fin and the second fin from the bottom to top successively.
The method forming described oxidation fin and the second fin comprises:
With reference to figure 5, sedimentation or epitaxial growth method is used to form the first fin material layer 120 in described substrate 110.
In a particular embodiment, the material of described first fin material layer 120 is silicon.
In a particular embodiment, during formation first fin material layer 120, use and in-situ doped first kind doping is carried out to described first fin material layer 120; Or, after forming the first fin material layer 120, first kind doping is carried out to described first fin material layer 120.
With reference to figure 6, sedimentation or epitaxial growth method is used to form the second fin material layer 130 on described first fin material layer 120.
In a particular embodiment, the material of described second fin material layer 130 is SiGe.The electron transfer rate of channel region that the channel region formed due to SiGe is formed than silicon is large, after forming the second fin by described second fin material layer 130, described second fin operationally can form channel region, electron transfer rate in channel region can increase, and can reduce the power consumption of fin formula field effect transistor.
In a particular embodiment, during formation second fin material layer 130, use in-situ doped, carry out Second Type doping to the second fin material layer 130, Second Type is identical with the first kind, and the concentration of Second Type doping is less than the concentration of first kind doping; Or after forming the second fin material layer 130, carry out Second Type doping to the second fin material layer 130, Second Type is identical with the first kind, and the concentration of Second Type doping is less than the concentration of first kind doping.
After forming oxidation fin by described first fin material layer 120, if oxidation fin is not fully oxidized, and do not form side wall at the sidewall of described oxidation fin, the voltage be applied on grid may make to form inversion layer in described oxidation fin.The inversion layer formed in described oxidation fin can make the drive current of fin formula field effect transistor increase, if described drive current is excessive, can improve the power consumption of described fin formula field effect transistor.
Secondly, if form inversion layer in described oxidation fin, this inversion layer can cause effectively separating described substrate 110 and the second fin, is difficult to effectively stop the electric current between source electrode and drain electrode to carry out conducting by described substrate 110, can increase the power consumption of described fin formula field effect transistor.
Because the threshold voltage of fin formula field effect transistor is relevant with the impurity concentration of adulterating in fin, the impurity concentration in fin is higher, and the threshold voltage of fin formula field effect transistor is higher.When the voltage that grid applies reaches threshold voltage, make to form inversion layer in fin, this inversion layer is as channel region.Because described first fin material layer 120 has first kind doping, described second fin material layer 130 has Second Type doping, the described first kind is identical with described Second Type, and the concentration of described first kind doping is greater than the concentration of described Second Type doping.Can ensure like this, even if oxidation fin is not fully oxidized, also can make not form inversion layer in described oxidation fin by regulating the voltage on grid, and in the second fin, form inversion layer to form channel region, and then ensure to obtain leakage current fin formula field effect transistor little, low in energy consumption.
In other embodiments, described first fin material layer 120 has first kind doping, and described second fin material layer 130 is doping not.
In other embodiments, described first fin material layer 120 and described second fin material layer 130 all do not adulterate.
The fin formula field effect transistor of the present embodiment can by the height regulating the height of the second fin material layer 130 to regulate the second fin, and then regulate the drive current of described fin formula field effect transistor, described drive current is made to be a preferred values, the better operating state of described fin formula field effect transistor can either be kept, the power consumption of described fin formula field effect transistor can not be made again to increase.
With reference to figure 7, described second fin material layer 130 forms patterned mask layer 140.Described patterned mask layer 140 defines the position of the second fin.
The material of described patterned mask layer 140 can be the material known in the art such as silicon nitride, silicon oxynitride.
With reference to figure 8, with described patterned mask layer 140 for mask, etch described second fin material layer 130 and described first fin material layer 120, be etched to described first fin material layer 120 lower surface, form the second fin 131 and the first fin 121; Then described patterned mask layer 140 is removed.
With reference to figure 9, described second fin 131 forms mask layer 141; After forming described mask layer 141, the first fin 121 described in lateral etching part.
Because the material of described first fin material layer 120 is silicon, the material of described second fin material layer 130 is SiGe.Described in lateral etching part, the method for the first fin 121 can be: use CF
4, O
2and N
2plasma plasma etching is carried out to described first fin 121; Or, use HNO
3with the aqueous solution of HF, wet etching is carried out to described first fin 121.When using said method to etch described first fin 121, described first fin 121 has very high etching selection ratio with described second fin 131, so substantially only can etch described first fin 121, its width is reduced.
After first fin 121 described in lateral etching part, the width of the first fin 121 is less than the width of described second fin 131, the surface that second fin 131 is exposed not only comprises upper surface and the two side of the second fin 131, but also comprises not by the second fin 131 lower surface that described first fin 121 covers.
With reference to Figure 10, after the first fin 121 described in lateral etching part, remove described mask layer 141.Then, be oxidized described first fin 121, form oxidation fin 122; Be oxidized the surface that described second fin 131 exposes; The surface exposed at described second fin 131 forms grid oxide layer 132.
The precedence being oxidized the step on the surface of described first fin 121 and described second fin 131 exposure of oxidation can be exchanged, and also can carry out in same step.
The method being oxidized the surface of described first fin 121 and described second fin 131 exposure of oxidation in same step is thermal oxidation method.
Width due to the first fin 121 is less than the width of described second fin 131, and described grid oxide layer 132 covers the upper surface of described second fin 131, two side and not by lower surface that described first fin 121 covers.
With reference to Figure 11, form the grid 150 across described oxidation fin 122 and the second fin 131.
In a particular embodiment, after forming grid 150, also comprise: form source electrode and drain electrode (not shown in Figure 11).
Described grid 150 is formed on described grid oxide layer 132.
In prior art, the surface that fin exposes only has upper surface and the two side of fin.In the present embodiment, because the width being oxidized fin 122 is less than the width of the second fin 131, so the surface that described second fin 131 exposes not only comprises upper surface and the two side of the second fin 131, also comprise not by the lower surface that described oxidation fin 122 covers, the surface area that described second fin 131 exposes increases.After forming grid 150, because grid 150 and the lower surface of the second fin 131 do not covered by described oxidation fin 122 also have relative area, the relative area of grid 150 and the second fin 131 increases, and grid 150 well can control the channel region formed in the second fin 131.
Above embodiment is with the material of described first fin material layer 120 for silicon, and the material of described second fin material layer 130 is SiGe is that the formation method of example to described fin formula field effect transistor is described.
In other embodiments, the material of described first fin material layer 120 is SiGe, and the material of described second fin material layer 130 is silicon.Accordingly, described in lateral etching part, the method for the first fin 121 is: use CF
4plasma plasma etching is carried out to described first fin 121; Or, use the aqueous solution of HCl to carry out wet etching to described first fin 121.
In other embodiments, the material of described first fin material layer 120 and described second fin material layer 130 also can be other semi-conducting materials known in the art, as long as when meeting the first fin 121 described in lateral etching part, described first fin 121 has very high etching selection ratio with described second fin 131.
Second embodiment
The difference of the present embodiment and the first embodiment is:
With reference to Figure 12, also comprise before forming described grid 150:
Form side wall 143 at described oxidation fin 122 sidewall, the height of described side wall 143 equals the height of described oxidation fin 122.
In other embodiments, the height of described side wall 143 also can be less than the height of described oxidation fin 122.
The method forming described side wall 143 comprises:
Described substrate 110, described oxidation fin 122 and described second fin 131 form spacer material layer;
Utilize back carving technology to etch described spacer material layer, expose upper surface and the sidewall of described second fin 131, the sidewall of described oxidation fin 122 forms side wall 143.
Described side wall 143 serves the effect of dielectric layer, electric capacity between described grid 150 and described oxidation fin 122 is reduced, weaken the electric field strength between described grid 150 and described oxidation fin 122, even if oxidation fin is not fully oxidized, be also difficult to form inversion layer in described oxidation fin 122.And then ensure to obtain leakage current fin formula field effect transistor little, low in energy consumption.
The method that described substrate 110 is formed oxidation fin 122 and the second fin 131 from the bottom to top successively can with reference to the first embodiment.
3rd embodiment
The present embodiment provides a kind of fin formula field effect transistor, and with reference to Figure 11, described fin formula field effect transistor comprises:
Substrate 110;
Be positioned at the oxidation fin 122 in described substrate 110;
Be positioned at the second fin 131 on described oxidation fin 122, the width of described second fin 131 is greater than the width of described oxidation fin 122;
Be positioned at the grid oxide layer 132 on the surface that described second fin 131 exposes;
Across the grid 150 of described oxidation fin 122 and the second fin 131.
In a particular embodiment, the material of described oxidation fin 122 is silica, germanium oxide or silicon germanium oxide.The material of described second fin 131 is germanium, SiGe or silicon.The material of described grid oxide layer 132 is the oxide that the material of described second fin 131 is corresponding, and namely the material of described second fin 131 is germanium, and the material of described grid oxide layer 132 is just germanium oxide; The material of described second fin 131 is SiGe, and the material of described grid oxide layer 132 is just silicon germanium oxide; The material of described second fin 131 is silicon, and the material of described grid oxide layer 132 is just silica.
In a particular embodiment, described oxidation fin 122 has first kind doping, described second fin 131 has Second Type doping, and the described first kind is identical with described Second Type, and the concentration of described first kind doping is greater than the concentration of described Second Type doping.
In other embodiments, described oxidation fin 122 has the first doping, and described second fin 131 is doping not.
In other embodiments, described oxidation fin 122 and described second fin 131 all do not adulterate.
4th embodiment
The present embodiment provides a kind of fin formula field effect transistor, and with reference to Figure 12, described fin formula field effect transistor comprises:
Substrate 110;
Be positioned at the oxidation fin 122 in described substrate 110;
Be positioned at the side wall 143 of described oxidation fin 122 sidewall, the height of described side wall 143 equals the height of described oxidation fin 122;
Be positioned at the second fin 131 on described oxidation fin 122, the width of described second fin 131 is greater than the width of described oxidation fin 122;
Be positioned at the grid oxide layer 132 on the surface that described second fin 131 exposes;
Across the grid 150 of described oxidation fin 122 and the second fin 131.
In other embodiments, the height of described side wall 143 also can be less than the height of described oxidation fin 122.
The material of described oxidation fin 122, described second fin 131 and described grid oxide layer 132 can with reference to the 3rd embodiment.The doping of described oxidation fin 122 and the second fin 131 can with reference to the 3rd embodiment.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (14)
1. a formation method for fin formula field effect transistor, is characterized in that, comprising:
Substrate is provided;
Form the first fin and the second fin from the bottom to top successively on the substrate, the width of the first fin is less than the width of the second fin;
Be oxidized described first fin and form oxidation fin;
Be oxidized the surface that described second fin exposes, the surface exposed at described second fin forms grid oxide layer;
After forming oxidation fin and grid oxide layer, form the grid across described oxidation fin and the second fin.
2. the formation method of fin formula field effect transistor as claimed in claim 1, is characterized in that, forms the
The method of one fin and the second fin comprises:
Form the first fin material layer on the substrate, the first fin material layer is formed the second fin material layer;
Patterned mask layer is formed at described second fin material layer upper surface;
With described patterned mask layer for mask, etch described second fin material layer and the first fin material layer, form the second identical fin of width and the first fin;
First fin described in lateral etching part, makes the width of the first fin be less than the width of the second fin.
3. the formation method of fin formula field effect transistor as claimed in claim 2, it is characterized in that, the material of described first fin is silicon, and the material of described second fin is SiGe, and described in lateral etching part, the method for the first fin is:
Use CF
4, O
2and N
2plasma plasma etching is carried out to described first fin; Or,
Use HNO
3with the aqueous solution of HF, wet etching is carried out to described first fin.
4. the formation method of fin formula field effect transistor as claimed in claim 2, it is characterized in that, the material of described first fin is SiGe, and the material of described second fin is silicon, and described in lateral etching part, the method for the first fin is:
Use CF
4plasma plasma etching is carried out to described first fin; Or,
The aqueous solution of HCl is used to carry out wet etching to described first fin.
5. the formation method of fin formula field effect transistor as claimed in claim 2, it is characterized in that, the method forming the first fin material layer comprises:
Use sedimentation or epitaxial growth method, form the first fin material layer on the substrate.
6. the formation method of the fin formula field effect transistor as described in claim 2 or 5, is characterized in that, the method forming the second fin material layer comprises:
Use sedimentation or epitaxial growth method, described first fin material layer forms the second fin material layer.
7. the formation method of fin formula field effect transistor as claimed in claim 2, is characterized in that, also comprise:
During formation first fin material layer, use and in-situ doped first kind doping is carried out to described first fin material layer; Or,
After forming the first fin material layer, before forming the second fin material layer, first kind doping is carried out to described first fin material layer.
8. the formation method of fin formula field effect transistor as claimed in claim 7, is characterized in that, also comprise:
During formation second fin material layer, use in-situ doped, carry out Second Type doping to the second fin material layer, Second Type is identical with the first kind, and the concentration of Second Type doping is less than the concentration of first kind doping; Or,
After forming the second fin material layer, carry out Second Type doping to the second fin material layer, Second Type is identical with the first kind, and the concentration of Second Type doping is less than the concentration of first kind doping.
9. the formation method of fin formula field effect transistor as claimed in claim 1, is characterized in that, also comprise before forming described grid:
Form side wall at described first fin sidewall, the height of described side wall is less than or equal to the height of described first fin.
10. a fin formula field effect transistor, is characterized in that, comprising:
Substrate;
Be positioned at described suprabasil oxidation fin;
Be positioned at the second fin on described oxidation fin, the width of described second fin is greater than the width of described oxidation fin;
Be positioned at the grid oxide layer on the surface that described second fin exposes;
Across the grid of described oxidation fin and the second fin.
11. fin formula field effect transistors as claimed in claim 10, is characterized in that, the material of described oxidation fin is silica, germanium oxide or silicon germanium oxide.
12. fin formula field effect transistors as described in claim 10 or 11, it is characterized in that, the material of described second fin is germanium, SiGe or silicon.
13. fin formula field effect transistors as claimed in claim 10, it is characterized in that, oxidation fin has first kind doping, and the second fin has Second Type doping, Second Type is identical with the first kind, and the concentration of Second Type doping is less than the concentration of first kind doping.
14. fin formula field effect transistors as claimed in claim 10, is characterized in that, also comprise:
Be positioned at the side wall of described oxidation fin sidewall, the height of described side wall is less than or equal to the height of described oxidation fin.
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