CN101399191B - Method for manufacturing grillage layer and fabricating method for semiconductor device - Google Patents
Method for manufacturing grillage layer and fabricating method for semiconductor device Download PDFInfo
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- CN101399191B CN101399191B CN200710046795XA CN200710046795A CN101399191B CN 101399191 B CN101399191 B CN 101399191B CN 200710046795X A CN200710046795X A CN 200710046795XA CN 200710046795 A CN200710046795 A CN 200710046795A CN 101399191 B CN101399191 B CN 101399191B
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Abstract
The invention provides a method for manufacturing a grid layer, and the method comprises the following steps: a semiconductor substrate which has a grid dielectric layer is provided; a poly-silicon layer is formed on the grid dielectric layer; a silicon oxide layer is formed on the surface of the poly-silicon layer; ion implantation doping is carried out on the poly-silicon layer. The invention also provides a method for manufacturing a semiconductor device. The method has relatively simple process and can prevent or eliminate implanted ion from penetrating or entering the grid oxide layer when the poly-silicon layer is doped.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, the particularly a kind of manufacture method of grid layer and the manufacture method of semiconductor device.
Background technology
In the metal oxide semiconductor transistor, generally adopt polysilicon as the material of making grid.For reducing power consumption, improve the response speed of the metal oxide semiconductor transistor that forms, usually the polysilicon layer of making grid is mixed, to reduce its resistivity.For example, in the polysilicon gate of N type metal oxide semiconductor transistor (NMOS), mix phosphorus, in the polysilicon gate of P-type mos transistor (PMOS), mix boron etc.
In polysilicon layer, mix impurity and form the manufacturing process of grid generally as follows: at first on Semiconductor substrate, deposit grid oxic horizon; Then, deposit spathic silicon layer on described grid oxic horizon; Then described polysilicon layer is carried out ion implantation doping; Follow, graphical described polysilicon layer forms polysilicon gate again.
Yet; in doping process to polysilicon layer; the energy that mixes is bigger; the impurity that mixes usually can pass polysilicon layer and enter grid oxic horizon; even pass grid oxic horizon and enter into Semiconductor substrate, the metal oxide semiconductor transistor threshold voltage that causes forming produces problems such as drift, leakage current increase.
The patent No. is that the Chinese patent of ZL97120453.5 discloses a kind of P of having
+The manufacture method of the metal oxide semiconductor transistor of polysilicon gate, in its disclosed patent, by mixing in polysilicon gate that phosphonium ion pins down and fixing boron ion, and the probability of reduction boron ion penetration grid oxic horizon, simultaneously before polysilicon layer being carried out the boron doping, form metal silicide layer on described polysilicon layer, stop, its concrete technology as shown in Figures 1 to 4.
As shown in Figure 1, provide Semiconductor substrate 1, in described Semiconductor substrate 1, form field oxide (figure does not show), on described Semiconductor substrate 1, form grid oxic horizon 5; Then, on described grid oxic horizon 5, form amorphous silicon layer 7, with SiH
4And PH
3Reaction produces phosphorous diffusion and injects described amorphous silicon layer 7 to form the N type amorphous silicon layer of light dope.
As shown in Figure 2, on described amorphous silicon layer 7, form metal silicide layer 9.For example, described metal silicide layer 9 can be a tungsten silicide.
As shown in Figure 3, the method for injecting with ion forms P
+Silicon layer 7a, this process is for using BF
2Pass through metal silicide layer 9 and form P
+Silicon layer 7a, the energy of injection are 20 to 180KeV, then described silicon layer 7a are imposed heat treatment, make amorphous silicon change polysilicon into.
As shown in Figure 4, by the graphical metal silicide layer 9 of chemical wet etching, P
+Polysilicon layer 7a and grid oxic horizon 5 form grid structure.
In the described method, suppress boron ion penetration grid oxic horizon by phosphonium ion in polysilicon gate and the metal silicide layer that on described polysilicon layer, forms, yet, this method has increased technology that the polysilicon layer phosphonium ion is mixed and the technology that forms metal silicide, makes that the technology that forms polysilicon gate is comparatively complicated.
Summary of the invention
The invention provides a kind of manufacture method of grid layer and the manufacture method of semiconductor device, technology of the present invention is comparatively simple, and can suppress or eliminate the ion penetration that injects or enter grid oxic horizon when polysilicon layer is mixed.
The manufacture method of a kind of grid layer provided by the invention comprises:
Semiconductor substrate with gate dielectric layer is provided;
Form polysilicon layer on described gate dielectric layer, described polysilicon layer comprises first polysilicon layer and second polysilicon layer of the crystal grain disorder distribution that forms on described first polysilicon layer;
Form silicon oxide layer on described polysilicon layer surface;
Described polysilicon layer is carried out ion implantation doping, form the grid layer.
Optionally, the method that forms described silicon oxide layer is an oxidizing process.
Optionally, described oxidizing process is that furnace oxidation, rapid thermal annealing oxidation, original position water vapour produce a kind of in the oxidation.
Optionally, described oxidizing process is the rapid thermal annealing oxidation, and the temperature of annealing is 900 to 1200 ℃.
Optionally, the method that forms described silicon oxide layer is chemical vapour deposition (CVD).
Optionally, the thickness of described silicon oxide layer be 10 to
Optionally, described silicon oxide layer is at least one deck.
Optionally, before described polysilicon layer surface forms the silicon oxide layer step, nitriding process is carried out on described polysilicon layer surface.
Optionally, described gate dielectric layer is silica or silicon oxynitride.
Optionally, further comprise: after finishing ion implantation doping described first polysilicon layer and second polysilicon layer are carried out annealing process.
Optionally, described polysilicon layer is a multilayer, and along with the increase of the number of plies, crystallite dimension reduces.
The present invention also provides a kind of manufacture method of grid layer, comprising:
Semiconductor substrate with gate dielectric layer is provided;
On described gate dielectric layer, form silicon layer, described silicon layer is the stacked structure of polysilicon layer and amorphous silicon layer, wherein, amorphous silicon layer is positioned at the top of described polysilicon layer, and described polysilicon layer comprises first polysilicon layer and second polysilicon layer of the crystal grain disorder distribution that forms on described first polysilicon layer;
Form silicon oxide layer in described silicon surface;
Described silicon layer is carried out ion implantation doping;
Described silicon layer is carried out annealing process.
Optionally, the method that forms described silicon oxide layer is an oxidizing process.
Optionally, described oxidizing process is that furnace oxidation, rapid thermal annealing oxidation, original position water vapour produce a kind of in the oxidation.
Optionally, the method that forms described silicon oxide layer is a chemical vapour deposition technique.
Optionally, described silicon layer is the stacked structure of polysilicon layer and amorphous silicon layer, and wherein, amorphous silicon layer is positioned at the top of described polysilicon layer.
The present invention also provides a kind of manufacture method of semiconductor device, comprising:
Semiconductor substrate with gate dielectric layer is provided;
On described gate dielectric layer, form silicon layer, described silicon layer is the stacked structure of polysilicon layer and amorphous silicon layer, wherein, amorphous silicon layer is positioned at the top of described polysilicon layer, and described polysilicon layer comprises first polysilicon layer and second polysilicon layer of the crystal grain disorder distribution that forms on described first polysilicon layer;
Form silicon oxide layer in described silicon surface;
Described silicon layer is carried out ion implantation doping;
Graphical described silicon layer forms grid;
Semiconductor substrate to described grid both sides is mixed, and forms source electrode and drain electrode.
Optionally, the method that forms described silicon oxide layer is an oxidizing process.
Optionally, described oxidizing process is that furnace oxidation, rapid thermal annealing oxidation, original position water vapour produce a kind of in the oxidation.
Optionally, the method that forms described silicon oxide layer is a chemical vapour deposition technique.
Optionally, described silicon layer is the stacked structure of polysilicon layer and amorphous silicon layer, and wherein, amorphous silicon layer is positioned at the top of described polysilicon layer.
Compared with prior art, the present invention has the following advantages:
Form barrier layer or resilient coating by surface at the polysilicon layer that is used to form the grid layer or amorphous silicon layer or polysilicon layer, amorphous silicon layer stack layer, can suppress the follow-up ion that injects when ion injects of carrying out in polysilicon layer or amorphous silicon layer or polysilicon layer, amorphous silicon layer stack layer injects or passes gate dielectric layer to gate dielectric layer, help improving formation semiconductor device electrically, improve the yield that semiconductor device is made.
If forming the method for silicon oxide layer is oxidation technology, then when forming silicon oxide layer, the high temperature of oxidation technology is also heat-treated polysilicon layer or amorphous silicon layer or polysilicon layer, amorphous silicon layer stack layer, repairs lattice defect.
In addition, the technology that forms silicon oxide layer is simple, and the silicon oxide layer that forms exerts an influence to the polysilicon layer that is used to form the grid layer or amorphous silicon layer or polysilicon layer, amorphous silicon layer stack layer.
Description of drawings
Fig. 1 to Fig. 4 is the generalized section of each step corresponding construction of the manufacture method of existing a kind of metal oxide semiconductor transistor with P+ polysilicon gate;
Fig. 5 is the flow chart of first embodiment of the manufacture method of grid layer of the present invention;
Fig. 6 is the generalized section with Semiconductor substrate of gate dielectric layer;
Fig. 7 is the cross-sectional view that is formed with the Semiconductor substrate of polysilicon layer;
Fig. 8 is the generalized section of the structure after the polysilicon layer surface forms silicon oxide layer;
The generalized section of Fig. 9 for polysilicon layer is carried out ion implantation doping;
The cross-sectional view that has the Semiconductor substrate of two-layer polysilicon layer among second embodiment of Figure 10 for the manufacture method of grid layer of the present invention;
Figure 11 is the generalized section of the structure after second polysilicon layer surface forms silicon oxide layer among second embodiment of the manufacture method of grid layer of the present invention;
The cross-sectional view that has the Semiconductor substrate of polysilicon layer and amorphous silicon layer among the 3rd embodiment of Figure 12 for the manufacture method of grid layer of the present invention;
Figure 13 is the generalized section of the structure after the amorphous silicon layer surface of Figure 12 forms silicon oxide layer;
The structural representation that has the Semiconductor substrate of amorphous silicon layer among the 4th embodiment of Figure 14 for the manufacture method of grid layer of the present invention;
Figure 15 is the generalized section of the structure after the amorphous silicon layer surface of Figure 14 forms silicon oxide layer;
Figure 16 is the flow chart of embodiment of the manufacture method of semiconductor device of the present invention;
Figure 17 is the cross-sectional view of the device behind the grid that forms behind the graphical polysilicon layer;
Figure 18 is the cross-sectional view with semiconductor device of source electrode and drain electrode.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Fig. 5 is the flow chart of first embodiment of the manufacture method of grid layer of the present invention.Fig. 6 to 9 is the generalized section of the structure relevant with first embodiment of the manufacture method of grid layer of the present invention.
As shown in Figure 5, step S100 provides the Semiconductor substrate with gate dielectric layer.
Fig. 6 is the generalized section with Semiconductor substrate of gate dielectric layer.As shown in Figure 6, provide Semiconductor substrate 10, on described Semiconductor substrate 10, have gate dielectric layer 12.
Described Semiconductor substrate 10 materials can be a kind of in monocrystalline silicon, polysilicon, the amorphous silicon; The material of described Semiconductor substrate 10 can be a GaAs; Described Semiconductor substrate 10 also can have silicon on the insulating barrier (Silicon On Insulator, SOI) epitaxial layer structure on structure or the silicon; In described Semiconductor substrate 10, can mix N type impurity or p type impurity.
Prerinse is carried out on Semiconductor substrate 10 surfaces, can be removed oxide or other impurity on Semiconductor substrate 10 surfaces.Because Semiconductor substrate 10 is exposed in the air and can forms natural oxidizing layer on the surface, the thickness evenness of this natural oxidizing layer and rete characteristic are all relatively poor, for avoiding this natural oxidizing layer that the rete characteristic of the gate dielectric layer of follow-up formation is exerted an influence, can remove this natural oxidizing layer by wet-cleaned.Common removal method is a wet etching, and for example BOE or HF or RCA clean etc.
Described gate dielectric layer 12 is oxygen containing dielectric layer, and wherein, described oxygen containing dielectric layer comprises silica and silicon oxynitride; The method that forms silica can be high temperature furnace pipe oxidation, rapid thermal oxidation (Rapid Thermal Oxidation, RTO) or the original position water vapour produce oxidation (In-Situ Stream Generation, ISSG) a kind of in, silica is carried out nitrogen treatment can form silicon oxynitride, wherein the method for nitrogenize comprises a kind of in high temperature furnace pipe nitrogenize, rapid thermal treatment nitrogenize or the pecvd nitride.
Step S110 forms polysilicon layer on described gate dielectric layer.
Fig. 7 is the cross-sectional view that is formed with the Semiconductor substrate of polysilicon layer.As shown in Figure 7, form polysilicon layer 14 on described gate dielectric layer 12, the method that forms polysilicon layer 14 can be a Low Pressure Chemical Vapor Deposition, and reacting gas comprises SiH
4Or Si
2H
6, the uniformity for the rete of the polysilicon layer 14 that improve to form can also add N in reacting gas
2
Among the embodiment therein, the reaction temperature when forming polysilicon layer 14 is 700 to 740 ℃, and the pressure of reaction chamber is 200 to 300T, and the reaction time is 10 to 50 seconds, can control the thickness of the polysilicon layer 14 of formation according to the time of reaction.
Step S120 forms silicon oxide layer on described polysilicon layer surface.
Fig. 8 is the generalized section of the structure after the polysilicon layer surface forms silicon oxide layer.As shown in Figure 8, form silicon oxide layer 16 on described polysilicon layer 14 surfaces.The thickness of the silicon oxide layer 16 that forms be 10 to
Wherein, the method for formation silicon oxide layer 16 can be an oxidizing process.Described oxidizing process can be that furnace oxidation, rapid thermal annealing oxidation, original position water vapour produce a kind of in the oxidation.
Among the embodiment therein, the method that forms described silicon oxide layer 16 is the rapid thermal annealing oxidation, and wherein, the temperature of annealing is 900 to 1200 ℃.
The method that forms described silicon oxide layer 16 also can be a chemical vapour deposition technique, by chemical vapour deposition (CVD) at described polysilicon layer 14 surface deposition silicon oxide layers 16.
Among the embodiment therein, the reacting gas that forms silicon oxide layer 16 is SiH
4And O
2, SiH4 and N
2O, Si (C
2H
5O)
4A kind of with in the ozone.Described chemical vapour deposition (CVD) can be a kind of in aumospheric pressure cvd, low-pressure chemical vapor deposition or the plasma enhanced chemical vapor deposition.
In a further embodiment, described silicon oxide layer 16 can be a multilayer.
In a further embodiment, the method that forms described silicon oxide layer 16 is as follows: at first nitriding processes are carried out on described polysilicon layer 14 surfaces, described nitrogenize can be a kind of in boiler tube nitrogenize, rapid thermal annealing nitrogenize or the pecvd nitride; Form the skim silicon nitride by carrying out nitriding process on described polysilicon layer surface; Follow surface execution oxidation technology, form silicon oxide layer 16 polysilicon layer 14 of carrying out nitriding process.By carrying out earlier nitriding process, the speed in the time of can suppressing oxidation helps controlling comparatively accurately the thickness of the silicon oxide layer 16 of formation.
The silicon oxide layer 16 that forms on described polysilicon layer 14 surfaces is as resilient coating or barrier layer, can suppress the follow-up ion that carries out injecting when ion injects in polysilicon layer 14 injects to gate dielectric layer 12, help improving formation semiconductor device electrically, improve the yield that semiconductor device is made.
In addition, if forming the method for silicon oxide layer 16 is oxidation technology, then when forming silicon oxide layer 16, the high temperature of oxidation technology can be heat-treated described polysilicon layer 14 simultaneously, thereby can reform, and the lattice defect in the reparation polysilicon layer 14 to the crystal grain in the polysilicon layer 14.
In addition, the technology of formation silicon oxide layer 16 is comparatively simple with respect to the technology that forms metal silicide shown in Figure 2; And, the silicon oxide layer 16 that forms can not spread in described polysilicon layer 14, can not impact polysilicon layer 14, and the often more or less freely diffusion in polysilicon layer 14 of metal when forming metal silicide, for example tungsten is easy to spread in polysilicon layer, thereby can influence the electrical of polysilicon layer 14.
Step S130 carries out ion implantation doping to described polysilicon layer.
The generalized section of Fig. 9 for polysilicon layer is carried out ion implantation doping.As shown in Figure 9, see through silicon oxide layer 16, described polysilicon layer 14 is carried out ion implantation doping, form doped polysilicon layer 14A.The impurity that mixes can be impurity such as phosphorus, arsenic, boron; The energy that ion injects can be to be 5KeV to 15KeV.
Because the buffering or the barrier effect of silicon oxide layer 16, make the ion that injects reduce through described silicon oxide layer 16 back speed, energy, the ion that makes injection enters gate dielectric layer 12 as much as possible less or does not enter gate dielectric layer 12 under the situation that can enter polysilicon layer 14.
In a further embodiment, can carry out selective doping to polysilicon layer 14, such as, the ion that carries out N type impurity in the zone of needs being made NMOS injects, the ion that carries out p type impurity in the zone of needs being made PMOS injects, described selective doping need define doped regions by photoetching process, repeats no more here.
After finishing ion implantation doping process, described doped polysilicon layer 14A is carried out annealing process, by annealing process, activate the dopant ion that is injected among the described doped polysilicon layer 14A on the one hand, repair the defective that when ion injects, polysilicon layer 14 is caused on the other hand.
Promptly be formed for making the grid layer of grating of semiconductor element after the annealing, described grid layer is doped polysilicon layer 14A.
Figure 10 to Figure 11 for the relevant cross-sectional view of manufacture method second embodiment of grid layer of the present invention.
Figure 10 is the cross-sectional view with Semiconductor substrate of two-layer polysilicon layer.
As shown in figure 10, form the first polysilicon layer 14a and the second polysilicon layer 14b successively on the Semiconductor substrate 10 with gate dielectric layer 12, wherein, the crystal grain of the described second polysilicon layer 14b is disorder distribution.
Wherein, the method that forms the first polysilicon layer 14a and the second polysilicon layer 14b can be chemical vapour deposition (CVD).
Because crystal grain disorder distribution among this second polysilicon layer 14b, the direction in crystal grain gap also has unordered distribution; Thereby, when the first polysilicon layer 14a is carried out ion implantation doping, the ion that injects is owing to be subjected to the stopping of crystal grain of the disorder distribution of this second polysilicon layer 14b, when entering into the first polysilicon layer 14a, energy can reduce to some extent, thereby can reduce or the ion avoiding injecting enters or pass gate dielectric layer 12; The also i.e. effect of this second polysilicon layer 14b with buffering.
Among the embodiment therein, the method that forms the described second polysilicon layer 14b is a low-pressure chemical vapor deposition, and reacting gas comprises SiH
4, Si
2H
6And H
2, the temperature of reaction is 700 to 740 degree, the pressure of reaction chamber is 200 to 300T, reaction time is 10 to 30 seconds, can control the thickness of the second polysilicon layer 14b of formation according to the time of reaction, after the reaction, the crystal grain disorder distribution among the second polysilicon layer 14b of formation.
For improving the uniformity of the rete that forms the second polysilicon layer 14b, in reacting gas, also can add N
2
In addition, the technology that forms the described second polysilicon layer 14b can original position be carried out or carry out respectively in different process cavity with the technology that forms the described first polysilicon layer 14a.
In other embodiments, described polysilicon layer can be multilayer, and along with the increase of the number of plies, crystallite dimension reduces.
Figure 11 is the generalized section of the structure after second polysilicon layer surface forms silicon oxide layer.As shown in figure 11, form silicon oxide layer 16 on described second polysilicon layer 14b surface.The thickness of the silicon oxide layer 16 that forms can for 10 to
Wherein, the method that forms silicon oxide layer 16 can be an oxidizing process, and oxidizing process can be that furnace oxidation, rapid thermal annealing oxidation, original position water vapour produce a kind of in the oxidation.
Among the embodiment therein, the method that forms described silicon oxide layer 16 is the rapid thermal annealing oxidation, and wherein, the temperature of rapid thermal annealing is 900 to 1200 ℃.
The method that forms described silicon oxide layer 16 also can be a chemical vapour deposition technique, by chemical vapour deposition (CVD) at the second polysilicon layer 14b surface deposition silicon oxide layer 16.
Among the embodiment therein, the reacting gas that forms silicon oxide layer 16 is SiH
4And O
2, SiH4 and N
2O, Si (C
2H
5O)
4A kind of with in the ozone.
Described chemical vapour deposition (CVD) can be a kind of in aumospheric pressure cvd, low-pressure chemical vapor deposition or the plasma enhanced chemical vapor deposition.
In a further embodiment, described silicon oxide layer 16 can be a multilayer.
By the silicon oxide layer 16 that forms on described second polysilicon layer 14b surface as resilient coating or barrier layer, can further suppress the follow-up ion that carries out injecting when ion injects in the first polysilicon layer 14a and the second polysilicon layer 14b injects to gate dielectric layer 12, help improving formation semiconductor device electrically, improve the yield that semiconductor device is made.
Then, with described silicon oxide layer 16 as barrier layer or resilient coating, the described first polysilicon layer 14a and the second polysilicon layer 14b are carried out ion implantation doping, then the first polysilicon layer 14a after mixing and the second polysilicon layer 14b are carried out annealing process, the crystal grain among the described second polysilicon layer 14b is reformed.The described first polysilicon layer 14a and the second polysilicon layer 14b are formed for making the grid layer of grid.
Figure 12 to Figure 13 for the relevant cross-sectional view of the 3rd embodiment of the manufacture method of grid layer of the present invention.
Figure 12 is the cross-sectional view with Semiconductor substrate of polysilicon layer and amorphous silicon layer.As shown in figure 12, on Semiconductor substrate 10, form polysilicon layer 14c and amorphous silicon layer 14d successively with gate dielectric layer 12.
Wherein the amorphous silicon 14d of Xing Chenging can suppress or slow down the ion that polysilicon layer 14c is carried out injecting when ion injects and enters or penetrate gate dielectric layer 12.
Figure 13 is the generalized section of the structure after the amorphous silicon layer surface of Figure 12 forms silicon oxide layer.As shown in figure 13, form silicon oxide layer 16 on amorphous silicon layer 14d surface.The thickness of the silicon oxide layer 16 that forms be 10 to
Wherein, the method for formation silicon oxide layer 16 can be an oxidizing process.Oxidizing process can be that furnace oxidation, rapid thermal annealing oxidation, original position water vapour produce a kind of in the oxidation.
Among the embodiment therein, the method that forms described silicon oxide layer 16 is the rapid thermal annealing oxidation, and wherein, the temperature of rapid thermal annealing is 900 to 1200 ℃.
The method that forms described silicon oxide layer 16 also can be a chemical vapour deposition technique, by chemical vapour deposition (CVD) at described amorphous silicon layer 14d surface deposition silicon oxide layer.
Among the embodiment therein, the reacting gas that forms silicon oxide layer 16 is SiH
4And O
2, SiH4 and N2O, Si (C
2H
5O)
4A kind of with in the ozone.
Described chemical vapour deposition (CVD) can be a kind of in aumospheric pressure cvd, low-pressure chemical vapor deposition or the plasma enhanced chemical vapor deposition.
In a further embodiment, described silicon oxide layer 16 can be a multilayer.
The silicon oxide layer 16 that forms is as stopping or resilient coating that the ion that suppresses injection passes or enter gate dielectric layer 12 follow-up when polysilicon layer 14c ion is injected.
Then, with described silicon oxide layer 16 as stopping or resilient coating, described polysilicon layer 14c and amorphous silicon layer 14d are carried out ion implantation doping, annealing to described doped polycrystalline silicon layer 14d and amorphous silicon layer 14d then, make amorphous silicon layer 14d be converted into polysilicon, the polysilicon layer after polysilicon layer 14c and amorphous silicon layer 14d transform forms the grid layer jointly.
Figure 14 and Figure 15 are the generalized section of the structure relevant with manufacture method the 4th embodiment of grid layer of the present invention.
Figure 14 is the structural representation with Semiconductor substrate of amorphous silicon layer.As shown in figure 14, on Semiconductor substrate 10, form amorphous silicon layer 15 with gate dielectric layer 12.
Figure 15 is the generalized section that forms the structure of silicon oxide layer on the amorphous silicon layer surface of Figure 14.As shown in figure 15, form silicon oxide layer 16 on described amorphous silicon layer 15 surfaces.The thickness of the silicon oxide layer 16 that forms be 10 to
Wherein, the method for formation silicon oxide layer 16 can be an oxidizing process.Oxidizing process can be that furnace oxidation, rapid thermal annealing oxidation, original position water vapour produce a kind of in the oxidation.
Among the embodiment therein, the method that forms described silicon oxide layer 16 is the rapid thermal annealing oxidation, and wherein, the temperature of rapid thermal annealing is 900 to 1200 ℃.
The method that forms described silicon oxide layer 16 also can be a chemical vapour deposition technique, by chemical vapour deposition (CVD) at described amorphous silicon layer 15 surface deposition silicon oxide layers.
Among the embodiment therein, the reacting gas that forms silicon oxide layer 16 is SiH
4And O
2, SiH4 and N2O, Si (C
2H
5O)
4A kind of with in the ozone.
Described chemical vapour deposition (CVD) can be a kind of in aumospheric pressure cvd, low-pressure chemical vapor deposition or the plasma enhanced chemical vapor deposition.
In a further embodiment, described silicon oxide layer 16 can be a multilayer.
The silicon oxide layer that forms is as stopping or resilient coating that the ion that suppresses injection passes or enter gate dielectric layer 12 follow-up when amorphous silicon layer 15 ions are injected.
Then, as the barrier layer, described amorphous silicon layer 15 is carried out ion implantation doping with described silicon oxide layer 16, to the annealing of described doped amorphous silicon layer 15, make amorphous silicon layer 15 be converted into polysilicon then, the polysilicon layer after the conversion is the grid layer.
The present invention also provides a kind of manufacture method of semiconductor device.Figure 16 is the flow chart of embodiment of the manufacture method of semiconductor device of the present invention.
As shown in figure 16, step S200 provides the Semiconductor substrate with gate dielectric layer;
Step S210 forms silicon layer on described gate dielectric layer; The method that forms described silicon layer can be chemical vapour deposition (CVD).
Wherein, described silicon layer is a polysilicon layer, and described silicon layer also can be the stacked structure of polysilicon layer and amorphous silicon layer, and amorphous silicon layer is positioned at the top of described polysilicon layer.Described silicon layer can also be amorphous silicon layer.
Step S220 forms silicon oxide layer in described silicon surface; The thickness of the silicon oxide layer that forms is 10 to 50A.
Wherein, the method that forms described silicon oxide layer can be an oxidizing process.Oxidizing process can be that furnace oxidation, rapid thermal annealing oxidation, original position water vapour produce a kind of in the oxidation.
The method that forms described silicon oxide layer also can be a chemical vapour deposition technique, by chemical vapour deposition (CVD) at described amorphous silicon layer surface deposition silicon oxide layer.In chemical vapor deposition method, the reacting gas that forms silicon oxide layer is SiH
4And O
2, SiH4 and N2O, Si (C
2H
5O)
4A kind of with in the ozone.
Described chemical vapour deposition (CVD) can be a kind of in aumospheric pressure cvd, low-pressure chemical vapor deposition or the plasma enhanced chemical vapor deposition.
In a further embodiment, described silicon oxide layer also can be a multilayer.
Step S230 carries out ion implantation doping to described silicon layer; See through described silicon oxide layer described silicon layer is mixed, form doped polycrystalline silicon layer.Wherein, described silicon oxide layer is as stopping or resilient coating when the silicon layer ion is injected, and the ion that suppresses to inject passes or enter the gate dielectric layer below the silicon layer.
After finishing ion implantation doping, described silicon layer is annealed, activate the dopant ion that is incorporated in the described silicon layer.
Step S240, graphical described silicon layer forms grid;
With described silicon layer is that polysilicon layer is an example, and Figure 17 is the cross-sectional view of the device behind the grid that forms behind the graphical polysilicon layer.As shown in figure 17, by the graphical polysilicon layer of chemical wet etching technology, form grid 14B.
Remove the silicon oxide layer on the described grid 14B then.
Step S250 mixes to the Semiconductor substrate of described grid both sides, forms source electrode and drain electrode.
Figure 18 is the cross-sectional view with semiconductor device of source electrode and drain electrode.As shown in figure 18, form side wall layer 18, in the Semiconductor substrate 10 of described grid 14B both sides, form source electrode 20 and drain electrode 22 in described grid 14B both sides.
In the manufacture method of semiconductor device of the present invention, before forming the doped polycrystalline silicon grid, at first form silicon oxide layer on the polysilicon layer surface, this silicon oxide layer can carry out playing cushioning effect when ion injects to polysilicon layer, thereby can make the ion of injection can not enter or pass gate dielectric layer.Can improve the stability of semiconductor device of formation, improve the yield that semiconductor device is made.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (19)
1. the manufacture method of a grid layer is characterized in that, comprising:
Semiconductor substrate with gate dielectric layer is provided;
Form polysilicon layer on described gate dielectric layer, described polysilicon layer comprises first polysilicon layer and second polysilicon layer of the crystal grain disorder distribution that forms on described first polysilicon layer;
Form silicon oxide layer on described polysilicon layer surface;
Described polysilicon layer is carried out ion implantation doping, form the grid layer.
2. the manufacture method of grid layer as claimed in claim 1 is characterized in that: the method that forms described silicon oxide layer is an oxidizing process.
3. the manufacture method of grid layer as claimed in claim 2 is characterized in that: described oxidizing process is that furnace oxidation, rapid thermal annealing oxidation, original position water vapour produce a kind of in the oxidation.
4. the manufacture method of grid layer as claimed in claim 2 is characterized in that: described oxidizing process is the rapid thermal annealing oxidation, and the temperature of annealing is 900 to 1200 ℃.
5. the manufacture method of grid layer as claimed in claim 1 is characterized in that: the method that forms described silicon oxide layer is chemical vapour deposition (CVD).
6. as the manufacture method of each described grid layer of claim 1 to 5, it is characterized in that: the thickness of described silicon oxide layer be 10 to
7. as the manufacture method of each described grid layer of claim 1 to 5, it is characterized in that: described silicon oxide layer is at least one deck.
8. the manufacture method of grid layer as claimed in claim 1 is characterized in that: before described polysilicon layer surface forms the silicon oxide layer step nitriding process is carried out on described polysilicon layer surface.
9. the manufacture method of grid layer as claimed in claim 1 is characterized in that: described gate dielectric layer is silica or silicon oxynitride.
10. the manufacture method of grid layer as claimed in claim 1 is characterized in that, further comprises: after finishing ion implantation doping described first polysilicon layer and second polysilicon layer are carried out annealing process.
11. the manufacture method of grid layer as claimed in claim 1 is characterized in that: described polysilicon layer is a multilayer, and along with the increase of the number of plies, crystallite dimension reduces.
12. the manufacture method of a grid layer is characterized in that, comprising:
Semiconductor substrate with gate dielectric layer is provided;
On described gate dielectric layer, form silicon layer, described silicon layer is the stacked structure of polysilicon layer and amorphous silicon layer, wherein, amorphous silicon layer is positioned at the top of described polysilicon layer, and described polysilicon layer comprises first polysilicon layer and second polysilicon layer of the crystal grain disorder distribution that forms on described first polysilicon layer;
Form silicon oxide layer in described silicon surface;
Described silicon layer is carried out ion implantation doping;
Described silicon layer is carried out annealing process.
13. the manufacture method of grid layer as claimed in claim 12 is characterized in that: the method that forms described silicon oxide layer is an oxidizing process.
14. the manufacture method of grid layer as claimed in claim 13 is characterized in that: described oxidizing process is that furnace oxidation, rapid thermal annealing oxidation, original position water vapour produce a kind of in the oxidation.
15. the manufacture method of grid layer as claimed in claim 12 is characterized in that: the method that forms described silicon oxide layer is a chemical vapour deposition technique.
16. the manufacture method of a semiconductor device is characterized in that, comprising:
Semiconductor substrate with gate dielectric layer is provided;
On described gate dielectric layer, form silicon layer, described silicon layer is the stacked structure of polysilicon layer and amorphous silicon layer, wherein, amorphous silicon layer is positioned at the top of described polysilicon layer, and described polysilicon layer comprises first polysilicon layer and second polysilicon layer of the crystal grain disorder distribution that forms on described first polysilicon layer;
Form silicon oxide layer in described silicon surface;
Described silicon layer is carried out ion implantation doping;
Graphical described silicon layer forms grid;
Semiconductor substrate to described grid both sides is mixed, and forms source electrode and drain electrode.
17. the manufacture method of semiconductor device as claimed in claim 16 is characterized in that: the method that forms described silicon oxide layer is an oxidizing process.
18. the manufacture method of semiconductor device as claimed in claim 17 is characterized in that: described oxidizing process is that furnace oxidation, rapid thermal annealing oxidation, original position water vapour produce a kind of in the oxidation.
19. the manufacture method of semiconductor device as claimed in claim 16 is characterized in that: the method that forms described silicon oxide layer is a chemical vapour deposition technique.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102412130A (en) * | 2011-03-30 | 2012-04-11 | 上海华力微电子有限公司 | Method for improving carrier mobility of transistor by utilizing gate polycrystalline silicon |
| CN103177947A (en) * | 2011-12-22 | 2013-06-26 | 无锡华润上华科技有限公司 | Method for preparing polysilicon gate electrode of Metal Oxide Semiconductor (MOS) transistor |
| CN103346076B (en) * | 2013-06-27 | 2016-05-11 | 上海华力微电子有限公司 | Improve the method for grid oxygen active area defect |
| CN109935518B (en) * | 2017-12-19 | 2021-04-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method for forming metal gate thereof |
| CN108550525A (en) * | 2018-05-28 | 2018-09-18 | 武汉新芯集成电路制造有限公司 | Floating boom preparation method |
| CN112993159A (en) * | 2021-02-05 | 2021-06-18 | 上海华虹宏力半导体制造有限公司 | Preparation method of passive integrated device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6524954B1 (en) * | 1998-11-09 | 2003-02-25 | Applied Materials, Inc. | Reduction of tungsten silicide resistivity by boron ion implantation |
| US6939770B1 (en) * | 2003-07-11 | 2005-09-06 | Advanced Micro Devices, Inc. | Method of fabricating semiconductor device having triple LDD structure and lower gate resistance formed with a single implant process |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6524954B1 (en) * | 1998-11-09 | 2003-02-25 | Applied Materials, Inc. | Reduction of tungsten silicide resistivity by boron ion implantation |
| US6939770B1 (en) * | 2003-07-11 | 2005-09-06 | Advanced Micro Devices, Inc. | Method of fabricating semiconductor device having triple LDD structure and lower gate resistance formed with a single implant process |
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