CN103346076B - Improve the method for grid oxygen active area defect - Google Patents
Improve the method for grid oxygen active area defect Download PDFInfo
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- CN103346076B CN103346076B CN201310264408.5A CN201310264408A CN103346076B CN 103346076 B CN103346076 B CN 103346076B CN 201310264408 A CN201310264408 A CN 201310264408A CN 103346076 B CN103346076 B CN 103346076B
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- 238000000034 method Methods 0.000 title claims abstract description 67
- 230000007547 defect Effects 0.000 title claims abstract description 38
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 title abstract 2
- 229910052760 oxygen Inorganic materials 0.000 title abstract 2
- 239000001301 oxygen Substances 0.000 title abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 106
- 229920005591 polysilicon Polymers 0.000 claims abstract description 106
- 239000012861 aquazol Substances 0.000 claims abstract description 40
- 229920006187 aquazol Polymers 0.000 claims abstract description 38
- 238000000151 deposition Methods 0.000 claims abstract description 26
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 18
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract 8
- 238000005530 etching Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 238000003475 lamination Methods 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 11
- 238000002474 experimental method Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000008021 deposition Effects 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000001556 precipitation Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- -1 4-5 Torr) Substances 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010835 comparative analysis Methods 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a kind of method of improving grid oxygen active area defect. At Grown gate oxide; Depositing polysilicon layer on gate oxide; Carrying out N-type polysilicon gate adulterates in advance; On polysilicon layer, form and comprise PEOX layer and O3The polysilicon gate mask layer of the lamination of TEOS layer; On polysilicon gate mask layer, form anti-reflecting layer; On anti-reflecting layer, form photoresist, and utilize photoresist etch polysilicon layer to form polysilicon gate. The invention provides a kind of method that can prevent active area generation defect in the manufacturing process of polysilicon grating structure.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for improving defects of a gate oxide active region.
Background
In the semiconductor manufacturing process, the gate process is the gate electrode required by the device formed by photolithography and etching, and is the most important process step in the flow. The fabrication of a polysilicon gate structure generally includes the following steps: 1) growing a gate oxide layer 20 on a substrate 10; 2) depositing a polysilicon layer 30 on the gate oxide layer 20; 3) depositing a polysilicon gate mask layer 40 on the polysilicon layer 30; 4) forming an anti-reflection layer 50 on the polysilicon gate mask layer 40; 5) a photoresist 60 is formed on the anti-reflection layer 50, and the polysilicon layer 30 is etched using the photoresist 60to form a polysilicon gate. Fig. 1 shows a stacked structure before polysilicon etching.
In order to suppress the polysilicon depletion effect and reduce the gate oxide electrical property, N-type polysilicon gate pre-doping (NPO) is performed immediately after polysilicon deposition, and phosphorus implantation (Varian equipment, energy 3E15, dose 8 Kev) is generally used for ion implantation of N-type polysilicon gate pre-doping. After the N-type polysilicon gate pre-doping process, an oxide film is deposited to be used as a polysilicon gate mask layer (PECVD deposition, the process pressure is 4-5 Torr). However, in the production process, after the anti-reflection layer is opened, once the wafer (wafer) passes through a vacuum environment (such as SEMreview), defects are generated in the active region, which affects the yield of the product.
Disclosure of Invention
The invention aims to solve the technical problem of the prior art and provides a method for preventing the defects of an active region in the manufacturing process of a polysilicon gate structure.
In order to achieve the above technical object, according to a first aspect of the present invention, there is provided a method of improving defects of a gate oxide active region, including:
growing a gate oxide layer on a substrate;
depositing a polysilicon layer on the gate oxide layer;
pre-doping an N-type polysilicon gate;
forming a layer comprising PEOX and O on the polysilicon layer3A polysilicon gate mask layer of a stack of TEOS layers;
forming an anti-reflection layer on the polysilicon gate mask layer;
and forming photoresist on the anti-reflection layer, and etching the polysilicon layer by using the photoresist to form a polysilicon gate.
Preferably, the fifth step comprises: depositing a PEOX layer of a first thickness on the polysilicon layer at a first process pressure, and depositing O of a second thickness on the PEOX layer at a second process pressure3A TEOS layer.
Preferably, the first process pressure is in the range of 4 to 5 Torr.
The second process pressure condition is preferably 30Torr to 60Torr, and more preferably 40Torr to 50 Torr. Most preferably, the second process pressure conditions are 45 Torr.
Preferably, in the fifth step, the first thickness of the PEOX layer and O3The second thickness of TEOS layer is betweenToWhile the first thickness of the PEOX layer and O are the same3The sum of the second thicknesses of the TEOS layers is betweenToIn the meantime.
Preferably, the first thickness of the PEOX layerDegree and O3The sum of the second thicknesses of the TEOS layers is
Preferably, the first thickness of the PEOX layer isAnd O is3The second thickness of the TEOS layer is
Preferably, an N-type polysilicon gate pre-doping anneal is performed after the N-type polysilicon gate pre-doping.
Therefore, the invention provides a method for improving the defects of the gate oxide active region, which can prevent the defects of the active region from being generated in the manufacturing process of the polysilicon gate structure.
Drawings
A more complete understanding of the present invention, and the attendant advantages and features thereof, will be more readily understood by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:
fig. 1 schematically shows a stacked structure of polysilicon etching according to the prior art.
Fig. 2 schematically shows a flow chart of a method for improving gate oxide active region defects according to an embodiment of the invention.
Fig. 3 schematically shows a schematic diagram of a method for improving gate oxide active region defects according to an embodiment of the invention.
It is to be noted, however, that the appended drawings illustrate rather than limit the invention. It is noted that the drawings representing structures may not be drawn to scale. Also, in the drawings, the same or similar elements are denoted by the same or similar reference numerals.
Detailed Description
In order that the present disclosure may be more clearly and readily understood, reference will now be made in detail to the present disclosure as illustrated in the accompanying drawings.
The inventor of the application finds that the reason for generating the defects of the active region in the manufacturing process of the polysilicon gate structure is that the N-type polysilicon gate is pre-doped, gas is separated out through a vacuum environment and is gathered on the surface of a polysilicon gate mask layer film, and the polysilicon is damaged in the opening process of the anti-reflection layer, so that the defects are formed and transferred to the active region. One solution is to anneal after the N-type polysilicon gate pre-doping process to prevent gas from being precipitated.
< analysis of Defect analysis experiment >
More specifically, to confirm the cause of defect generation, 3 sets of experiments were designed:
(1) experimental group 1:
a. growing a gate oxide layer 20 on a substrate 10 → b. depositing a polysilicon layer 30 on the gate oxide layer 20 → c.N type polysilicon gate pre-doping → d.N type polysilicon gate pre-doping annealing → e. depositing a polysilicon gate mask layer 40 on the polysilicon layer 30 → f. forming an anti-reflection layer 50 on the polysilicon gate mask layer 40 → g. forming a photoresist 60 on the anti-reflection layer 50, and etching the polysilicon layer 30 with the photoresist 60to form a polysilicon gate.
(2) Experimental group 2: the method has no N-type polysilicon gate pre-doping process or N-type polysilicon gate pre-doping annealing process, and specifically comprises the following steps:
a. the method includes growing a gate oxide layer 20 on a substrate 10 → b. depositing a polysilicon layer 30 on the gate oxide layer 20 → e. depositing a polysilicon gate mask layer 40 on the polysilicon layer 30 → f. forming an anti-reflection layer 50 on the polysilicon gate mask layer 40 → g. forming a photoresist 60 on the anti-reflection layer 50, and etching the polysilicon layer 30 with the photoresist 60to form a polysilicon gate.
(3) Experimental group 3: the pre-doping annealing process of the N-type polysilicon gate does not exist, and specifically comprises the following steps:
the experimental results are as follows: a. the method includes growing a gate oxide layer 20 on a substrate 10 → b. depositing a polysilicon layer 30 on the gate oxide layer 20 → c.N type polysilicon gate pre-doping → e. depositing a polysilicon gate mask layer 40 on the polysilicon layer 30 → f. forming an anti-reflection layer 50 on the polysilicon gate mask layer 40 → g. forming a photoresist 60 on the anti-reflection layer 50, and etching the polysilicon layer 30 with the photoresist 60to form a polysilicon gate.
| Experimental group 1 | Experimental group 2 | Experimental group 3 | |
| Total number of defects | 309 | 84 | 87 |
| Active region damage defect | 88 | 0 | 2 |
The above experimental results show that: the generation of gate oxide active region defects is related to an N-type polysilicon gate pre-doping process; the comparison between the experimental group 1 and the experimental group 3 shows that the defects are generated by gas separation after the N-type polysilicon gate pre-doping process.
< analysis of Defect Elimination experiment >
Based on the above analysis, the inventors solved the defect problem by changing the polysilicon gate mask layer film type. The following experimental comparative analysis was performed.
The method comprises the following steps: a. growing a gate oxide layer 20 on a substrate 10 → b. depositing a polysilicon layer 30 on the gate oxide layer 20 → c.N type polysilicon gate pre-doping → d.N type polysilicon gate pre-doping annealing → e. depositing a polysilicon gate mask layer 40 on the polysilicon layer 30 → f. forming an anti-reflection layer 50 on the polysilicon gate mask layer 40 → g. forming a photoresist 60 on the anti-reflection layer 50, and etching the polysilicon layer 30 with the photoresist 60to form a polysilicon gate.
Experiment 1: the polysilicon gate mask layer is PEOX
Experiment 2: the polysilicon gate mask layer is PEOX
Wherein PEOX is a silicon dioxide (SiO 2) film grown by a chemical vapor deposition (PECVD) method, and the film forming method is characterized by taking plasma as auxiliary energy, high reaction vacuum degree (low reaction gas pressure: 4-5 Torr) and high compactness of film quality.
O3TEOS is prepared by using TEOS (tetraethoxysiloxane) and O3The silicon dioxide (SiO 2) film formed by the (ozone) reaction is characterized by low reaction vacuum degree (high reaction gas pressure: about 45 Torr), loose film quality and low compactness.
Thus, PEOX and O3TEOS are silicon dioxide, and the properties of the formed silicon dioxide film are different only by different film forming processes.
That is, for step e. depositing polysilicon gate mask layer 40 on polysilicon layer 30, experiment 1 was formed at a process pressure of 4 to 5TorrPEOX of (1); in experiment 2, the reaction solution was first formed under a condition of 4 to 5TorrIs then formed at a process pressure of 45TorrO of (A) to (B)3TEOS。
The experimental results are as follows:
| experiment 1 | Experiment 2 | |
| Total number of defects | 309 | 104 |
| Active region damage defect | 88 | 0 |
The experimental result shows that the polysilicon gate mask layer is composed ofChange toThen, the defect problem of the gate oxide active region can be effectively solved.
< modified Experimental analysis >
Except thatThick PEOX andthick O3The inventors also performed experimental analysis of other thickness cases for combinations of TEOS, and found that preferably PEOX and O are maintained3TEOS has a thickness of betweenToWhile maintaining PEOX and O3Total thickness of TEOS betweenToIn addition, better technical effects can be obtained.
Also, PEOX and O were maintained3Total thickness of TEOSIt is preferred that, for example, at the same thickness ratio,can obtain relatively good experimental results.
Wherein,thick PEOX andthick O3The combination of TEOS gave the best experimental results.
And, for O3The process gas pressure condition of TEOS, preferably 30Torr to 60Torr, can show the object of the present invention, and the process gas pressure of 40Torr to 50Torr can obtain a good technical effect.
< principle analysis >
In the prior art, because the deposition pressure of PEOX is 4-5Torr, gas in the pre-doping of the N-type polysilicon gate is easy to precipitate, and the gas is gathered on the HM surface to form defects. Thus, the prior art usesIf the N-type polysilicon gate pre-doping process does not have an annealing procedure, the wafer can easily separate out gas once passing through a vacuum environment after the anti-reflection layer is opened, and the wafer can be gathered on the surface of the mask layer to form defects.
In the present example, however, O is used3The deposition pressure of TEOS is about 45Torr, which is much higher than the deposition pressure of PEOX, and gas precipitation in N-type polysilicon gate predoping is suppressed at high pressure, so that the precipitates cannot be accumulated on the surface of the polysilicon gate mask layer 40to form defects.
Therefore, PEOXThe process pressure is 4-5Torr and is changed to PEOX + O3TEOS (for example, the process pressure is about 45 Torr), thereby effectively inhibiting the formation of defects. This is because, first, O3The vacuum degree of TEOS is 45Torr which is higher than PEOX (such as 4-5 Torr), and gas precipitation can be effectively inhibited; second, the film densification ratio of PEOX is O3TEOS is good, so PEOX + O is used3TEOS not only inhibits gas separation, but also ensures the compactness of the film.
Therefore, the problem that after the anti-reflection layer is opened in the gate process, the active area of the wafer passes through a vacuum environment to generate defects is solved, and the product yield is improved.
< specific examples >
Fig. 2 schematically shows a flow chart of a method for improving gate oxide active region defects according to an embodiment of the invention, and fig. 3 schematically shows a schematic diagram of the method for improving gate oxide active region defects according to an embodiment of the invention.
As shown in fig. 2 and 3, the method for improving defects of a gate oxide active region according to an embodiment of the present invention includes:
first step S1: growing a gate oxide layer 20 on a substrate 10;
second step S2: depositing a polysilicon layer 30 on the gate oxide layer 20;
third step S3: pre-doping an N-type polysilicon gate;
fourth step S4: carrying out N-type polysilicon gate pre-doping annealing; however, it should be noted that this step is preferable, and the object of the present invention can be achieved without adding this step.
Fifth step S5: forming a layer comprising a PEOX layer 41 and O on the polysilicon layer 303A stacked polysilicon gate mask layer 40 of TEOS layers 42;
sixth step S6: forming an anti-reflection layer 50 on the polysilicon gate mask layer 40;
seventh step S7: a photoresist 60 is formed on the anti-reflection layer 50, and the polysilicon layer 30 is etched using the photoresist 60to form a polysilicon gate.
Preferably, the fifth step S5 includes: depositing a PEOX layer 41 of a first thickness on the polysilicon layer 30 at a first process pressure, and depositing a second thickness on the PEOX layer 41 at a second process pressureThickness of O3A TEOS layer 42.
Preferably, the first process pressure is in the range of 4 to 5 Torr.
The second process pressure condition is preferably 30Torr to 60Torr, and more preferably 40Torr to 50 Torr. Most preferably, the second process pressure conditions are 45 Torr.
Preferably, in a fifth step S5, the first thickness and O of the PEOX layer 413The second thickness of TEOS layer 42 is betweenToWhile the first thickness of the PEOX layer 41 and O are simultaneously3The sum of the second thicknesses of TEOS layer 42 is betweenToIn the meantime.
Preferably, the first thickness of the PEOX layer 41 and O3The sum of the second thicknesses of TEOS layer 42 is
Preferably, the first thickness of the PEOX layer 41 isAnd O is3The second thickness of TEOS layer 42 is
Therefore, the invention provides a method for improving the defects of the gate oxide active region, which can prevent the defects of the active region from being generated in the manufacturing process of the polysilicon gate structure.
In addition, it should be noted that the terms "first", "second", "third", and the like in the specification are used for distinguishing various components, elements, steps, and the like in the specification, and are not used for indicating a logical relationship or a sequential relationship between the various components, elements, steps, and the like, unless otherwise specified or indicated.
It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (10)
1. A method for improving gate oxide active region defects, comprising:
growing a gate oxide layer on a substrate;
depositing a polysilicon layer on the gate oxide layer;
pre-doping an N-type polysilicon gate;
forming a layer comprising PEOX and O on the polysilicon layer3A polysilicon gate mask layer of a stack of TEOS layers;
forming an anti-reflection layer on the polysilicon gate mask layer;
and forming photoresist on the anti-reflection layer, and etching the polysilicon layer by using the photoresist to form a polysilicon gate.
2. The method of claim 1, wherein the polysilicon layer is formed with a PEOX layer and O3The step of stacking a polysilicon gate mask layer of TEOS layers includes: depositing a PEOX layer of a first thickness on the polysilicon layer at a first process pressure, and depositing O of a second thickness on the PEOX layer at a second process pressure3A TEOS layer.
3. The method of claim 1 or 2, wherein the first process pressure is 4 to 5 Torr.
4. The method of claim 1 or 2, wherein the second process pressure is 30Torr to 60 Torr.
5. The method of claim 1 or 2, wherein the second process pressure is 40Torr to 50 Torr.
6. The method of claim 1 or 2, wherein the second process pressure is 45 Torr.
7. The method for improving gate oxide active region defects as claimed in claim 1 or 2, wherein in the fifth step, the first thickness of the PEOX layer and O3The second thickness of TEOS layer is betweenToWhile the first thickness of the PEOX layer and O are the same3The sum of the second thicknesses of the TEOS layers is betweenToIn the meantime.
8. The method of claim 1 or 2, wherein the first thickness of the PEOX layer and the O are3The sum of the second thicknesses of the TEOS layers is
9. The method of claim 1 or 2, wherein the first thickness of the PEOX layer isAnd O is3The second thickness of the TEOS layer is
10. The method for improving gate oxide active region defects as claimed in claim 1 or 2, further comprising: and carrying out N-type polysilicon gate pre-doping annealing after the N-type polysilicon gate is pre-doped.
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| CN103943527B (en) * | 2014-02-21 | 2016-08-17 | 上海华力微电子有限公司 | The method using Test Constructure of detection etching polysilicon gate defect |
| CN103871922A (en) * | 2014-02-21 | 2014-06-18 | 上海华力微电子有限公司 | Method for detecting polycrystalline silicon grid etching defect by adopting voltage contrast test structure |
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|---|---|---|---|---|
| US6849531B1 (en) * | 2003-11-21 | 2005-02-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Phosphoric acid free process for polysilicon gate definition |
| CN101399191A (en) * | 2007-09-27 | 2009-04-01 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing grillage layer and fabricating method for semiconductor device |
| CN101625960A (en) * | 2008-07-07 | 2010-01-13 | 旺宏电子股份有限公司 | Patterning method |
| CN102148149A (en) * | 2010-02-05 | 2011-08-10 | 中芯国际集成电路制造(上海)有限公司 | Method for forming grid of semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6849531B1 (en) * | 2003-11-21 | 2005-02-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Phosphoric acid free process for polysilicon gate definition |
| CN101399191A (en) * | 2007-09-27 | 2009-04-01 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing grillage layer and fabricating method for semiconductor device |
| CN101625960A (en) * | 2008-07-07 | 2010-01-13 | 旺宏电子股份有限公司 | Patterning method |
| CN102148149A (en) * | 2010-02-05 | 2011-08-10 | 中芯国际集成电路制造(上海)有限公司 | Method for forming grid of semiconductor device |
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