KR100717824B1 - Capacitor and method for manufacturing the same - Google Patents

Abstract

The present invention is to provide a capacitor having a good electrical characteristics and a method of manufacturing the same while maintaining the durability of the capacitor, the method of manufacturing the capacitor of the present invention comprises the steps of forming a lower electrode, a first dielectric film formed on the lower electrode Forming a second dielectric layer on the first dielectric layer, the second dielectric layer having a dielectric constant greater than that of the first dielectric layer, by atomic layer deposition; forming a third dielectric layer on the second dielectric layer, the formed Forming an upper electrode on the third dielectric film, the present invention is mixed with a high dielectric constant material to increase the dielectric constant of the laminated dielectric film and to reduce the effective oxide thickness effect of improving the electrical characteristics of the capacitor There is.

Capacitor, Dielectric, Aluminum Oxide, Hafnium Oxide, MIM

Description

Capacitor and manufacturing method thereof {CAPACITOR AND METHOD FOR MANUFACTURING THE SAME}

1 is a cross-sectional view illustrating a dielectric film of a capacitor according to a preferred embodiment of the present invention.

2A to 2D are cross-sectional views illustrating a method of manufacturing a capacitor according to a preferred embodiment of the present invention.

3A to 3B are diagrams for explaining a process of forming a second dielectric film according to a preferred embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

21 semiconductor substrate 22 landing plug contact

23: storage node contact 24: barrier metal

25: etching barrier layer 26: sacrificial oxide film

27: lower electrode 28: dielectric film

29: upper electrode

TECHNICAL FIELD The present invention relates to semiconductor manufacturing technology, and more particularly, to a capacitor and a method of manufacturing the same.

With the miniaturization and directization of semiconductor devices, there is a demand for reducing the effective oxide thickness (Tox) of dielectric films and manufacturing reliable devices in the manufacturing process of capacitors. To this end, it is necessary to decrease the ΔC according to the bias voltage and improve electrical characteristics such as leakage current. To improve these characteristics, instead of the conventional silicon insulator silicon (SIS), a capacitor of a metal insulator metal (MIM) structure is used.

In addition, in order to prevent a decrease in capacitance, researches on capacitors using aluminum oxide films (Al ₂ O ₃ ) and hafnium oxide films (HfO ₂ ) having a large dielectric constant instead of the conventional ONO (Oxide Nitride Oxide) dielectric films have been conducted.

The aluminum oxide film has a very low dielectric constant and thus has a limitation in securing capacitance. The hafnium oxide film has a low breakdown field strength, which is vulnerable to repeated electric shocks, thereby degrading the durability of the capacitor. There is a problem in that leakage current characteristics are deteriorated.

In order to solve this problem, a dielectric film composed of a hafnium oxide film / aluminum oxide film / hafnium oxide film triple layer has been proposed. The triple layer dielectric film has a hafnium oxide film deposited at a thickness that does not crystallize, deposits an aluminum oxide film having better leakage current characteristics than the hafnium oxide film, and then forms a hafnium oxide film, thereby providing better electrical characteristics and durability than a single film. Improves.

However, in the dielectric layer including the triple layer, since the aluminum oxide film has a smaller dielectric constant than the hafnium oxide film, the dielectric constant of the entire capacitor is reduced.

The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a method of manufacturing a capacitor having good electrical characteristics while maintaining the durability of the capacitor.

A method of manufacturing a capacitor of the present invention for achieving the above object is a step of forming a lower electrode, forming a first dielectric film on the lower electrode, a dielectric having a larger dielectric constant than the first dielectric film on the first dielectric film And forming a mixed second dielectric film by atomic layer deposition, forming a third dielectric film on the second dielectric film, and forming an upper electrode on the formed third dielectric film.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

1 is a cross-sectional view illustrating a capacitor according to a preferred embodiment of the present invention.

As shown in FIG. 1, the dielectric film 28 of the capacitor according to the preferred embodiment of the present invention includes a first dielectric film 28a made of one of the high dielectric films selected from the high dielectric films having a dielectric constant of at least 9, and the dielectric material. A second dielectric layer 28b including a mixture of at least two high dielectric layers selected from a high dielectric film having a constant of at least 9, and a third dielectric film 28c including a high dielectric film of the same type or different from that of the first dielectric film 28b; Include.

The first and third dielectric films 28a and 28c are formed of any one of the high dielectric films selected from the high dielectric films shown in Table 1 below. Here, Table 1 shows the G.D. Wilk et al., Journal of Applied Physics, vol. 89; no. 10, pp5243-5275 (2001) shows the dielectric film and its properties disclosed in the literature.

matter Dielectric constant (k) Bandgap Eg (eV) Crystal structure (s) SiO ₂ 3.9 8.9 Amorphous Si ₃ N ₄ 7 5.1 Amorphous Al ₂ O ₃ 9 8.7 Amorphous Y ₂ O ₃ 15 5.6 Cuboid La ₂ O ₃ 30 4.3 Hexagonal Cube Shape, Cube Shape Ta ₂ O ₅ 26 4.5 Tetragonal TiO ₂ 80 3.5 Square system type (Rutile, Anatase) HfO ₂ 25 5.7 Monoclinic, Rhombic, Cube ZrO ₂ 25 7.8 Monoclinic, Rhombic, Cube

Preferably, it is formed of a hafnium oxide film.

The second dielectric layer 28b improves the leakage current characteristics to compensate for the leakage current vulnerability when the first and third dielectric layers 28a and 28c are formed of the same high dielectric layer, for example, a hafnium oxide layer, and improves the dielectric constant than the hafnium oxide layer. At least two kinds of high dielectric films selected from among high dielectric films are formed into a mixed film. Preferably it is formed from a mixture of any one selected from the group of mixtures such as ZrOxAlyOz and LaOxAlyOz, where x, y, z are zero or natural water.

On the other hand, the capacitor according to the preferred embodiment of the present invention further includes a lower electrode 27 and the upper electrode 29 formed on the upper and lower portions of the dielectric film 28, respectively. The lower electrode 27 and the upper electrode 29 are each formed of a metal layer, preferably, any one conductive electrode selected from the group of TiN, Ru, Pt, Ir, Ru / RuO ₂ , Ir / IrO _2, and SrRuO ₃ Form into material.

Hereinafter, a method of manufacturing a capacitor according to a preferred embodiment of the present invention shown in Figure 1 with reference to Figures 2a to 2d will be described. Here, a method of manufacturing a DRAM (Dynamic Random Access Memory) device having a concave type capacitor is shown for convenience of description.

First, as shown in FIG. 2A, a device isolation film, a well region, a word line, and a junction region, which are not shown, are formed on a semiconductor substrate 21 through a series of semiconductor manufacturing processes.

Subsequently, a first interlayer dielectric (ILD1) is deposited on the substrate 21 to cover the word line, and then a landing plug contact hole exposing a junction region is formed by performing an etching process using a photo method. hole, LDC) (not shown).

Subsequently, an isolated landing plug 22 is formed inside the landing plug contact hole, and then a second interlayer insulating film ILD2 is deposited to cover the top of the landing plug 22. In this case, the landing plug 22 is formed of a polysilicon film, and the second interlayer insulating film ILD2 is formed of a single layer or a stack of an oxide-based material.

Subsequently, a bit line (not shown) is formed on a part of the second interlayer insulating film ILD2.

Subsequently, an etching process using a photo method is performed to form a storage node contact hole (SNC) (not shown) to which the landing plug 22 is exposed, and then the storage node contact plug isolated therein. Node Contact Plug) 23 is formed. At this time, the storage node contact plug 23 is preferably formed of a polysilicon film.

The storage node contact plug 23 is then recessed to a certain depth. In this case, the recess process is performed using an etching selectivity between the polysilicon film and the oxide film.

Subsequently, a barrier metal layer 24 is formed on the storage node contact plug 23 so that the storage node contact plug 23 is recessed to fill the exposed storage node contact hole. In this case, the barrier metal layer 24 is isolated inside the storage node contact hole through a chemical mechanical polishing (CMP) or etch back process. At this time, the barrier metal layer 24 is formed in a stacked structure of Ti and a TiN film.

Subsequently, an etch barrier layer 25 is formed on the substrate 21 including the barrier metal layer 24. In this case, the etching barrier layer 25 is preferably formed of a TiN film.

Subsequently, a sacrificial oxide layer 26 for a capacitor storage node pattern is deposited on the etch barrier layer 25.

Subsequently, an etching process using a photo method is performed to form a storage node pattern exposing the barrier metal layer 24.

Subsequently, as shown in FIG. 2B, the lower electrode 27, which is a storage node of the capacitor, is deposited along the surface of the storage node pattern and then etched to separate the lower electrode 27. In this case, the lower electrode 27 is formed of any one electrode material selected from the group of TiN, Ru, Pt, Ru / Ru0 ₂ , Ir / IrO _2, and SrRuO ₃ . The thickness is formed in the thickness of 200-400 mm.

For example, when the lower electrode 27 is formed of TiN, the manufacturing method thereof is as follows. TiCl _{4 is} used as the raw material of TiN and NH ₃ is used as the reaction gas at a flow rate of about 10 to 1000 sccm at a pressure of 0.1 to 10 torr and a substrate temperature of 500 to 650 ° C.

Subsequently, as shown in FIG. 2C, the first dielectric layer 28a having the lower dielectric layer 28 is formed by atomic layer deposition (ALD) on the lower electrode 27. In this case, the dielectric constant of the first dielectric layer 28a is at least 9 or more formed of any one of the high dielectric layers selected from the high dielectric layers. Preferably, it is formed of a hafnium oxide film.

The first dielectric film 28a is formed to a thickness of 30 ~ 50Å, using Hf (NEtMe) ₄ as the raw material of HfO ₂ , Ar as a carrier gas, O ₃ as an oxidant, N ₂ as a purge gas The temperature of the board | substrate can be 250-500 degreeC, and the pressure of a reaction chamber can be performed at 0.1-1 torr. example For example, argon (Ar), which is a carrier gas, is maintained at a flow rate of 500 to 1000 sccm for 0.1 to 10 seconds to flow Hf (NEtMe) ₄ for 0.1 to 10 seconds. Then, nitrogen (N ₂ ) gas is injected into the chamber at a flow rate of 1500 to 2000 sccm for 3 to 10 seconds to purge the source gas remaining in the chamber without being adsorbed. Then, O ₃ gas, which is an oxidant, is injected at a flow rate of 1500 to 2000 sccm for 3 to 10 seconds to oxidize Hf adsorbed on the wafer to form an HfO ₂ film. Then, nitrogen (N ₂ ) gas is injected into the chamber at a flow rate of 1500 to 2000 sccm for 3 to 10 seconds to purge the unreacted O ₃ . This step is made into one cycle and the cycle is repeated to form the required thickness.

Next, when the first and third dielectric layers 28a and 28c are formed of the same high dielectric layer, for example, a hafnium oxide layer, the second dielectric layer 28b may improve the leakage current characteristic to compensate for the leakage current. At least two kinds of high dielectric films selected from higher dielectric constants are formed into a mixed film having a thickness of 5 to 10 Å. Preferably it is formed from a mixture of any one selected from the group of mixtures such as ZrOxAlyOz and LaOxAlyOz, where x, y, z are zero or natural water.

3A to 3B, an Al ₂ O ₃ film is first formed using an ALD method, and then a process of forming a ZrO ₂ film is performed.

As shown in FIG. 3A, an Al ₂ O ₃ film is first formed. The Al ₂ O ₃ film forming process is as follows. Using TMA [Al (CH ₃ ) ₃ ] as the source gas, argon (Ar) as the carrier gas, O ₃ as the oxidant, and N ₂ as the purge gas, the substrate temperature is 250-500 ° C and the pressure of the reaction chamber is 0.1. It can carry out at -1 torr. For example, argon (Ar), which is a carrier gas, is maintained at a flow rate of 20 to 100 sccm for 0.1 to 5 seconds to flow TMA [Al (CH ₃ ) ₃ ]. Then, nitrogen (N ₂ ) gas is injected into the chamber at a flow rate of 50 to 300 sccm for 0.1 to 5 seconds to purge the Al source gas remaining in the chamber without adsorption to the outside. Then, O ₃ gas, which is an oxidant, is injected into the chamber at a flow rate of 200 to 500 sccm for 3 to 10 seconds to oxidize Al adsorbed on the wafer to form an Al ₂ O ₃ film. Then, nitrogen (N ₂ ) gas is injected into the chamber at a flow rate of 300 to 1000 sccm for 0.1 to 5 seconds to purge the unreacted O ₃ . This step is repeated in one cycle.

Subsequently, a ZrO ₂ film forming process is performed as shown in FIG. 3B. The ZrO ₂ film forming process is as follows. Zr (O-tBu) ₄ , Zr [N (CH ₃ ) ₂ ] ₄ , Zr [N (C ₂ H ₅ ) (CH ₃ )] ₄ , Zr [N (C ₂ H ₅ ) ₂ ] ₄ , Zr ( tmhd) ₄ , Zr (OiC ₃ H ₇ ) (tmhd) and Zr (OtBu) ₄ selected from a group of gases such as a source of argon (Ar) from 0.1 to 50 sccm at a flow rate of 10 to 50 sccm Hold for 5 seconds to flow. Then, nitrogen gas is injected at a flow rate of 50 to 300 sccm for 0.1 to 5 seconds to purge the Zr source gas remaining in the chamber without adsorption to the outside. Then, O ₃ is injected into the chamber to form a ZrO ₂ film on the wafer on which the Al ₂ O ₃ film is not formed. Then, nitrogen (N ₂ ) gas is injected into the chamber to purge the unreacted O ₃ in one cycle. The Al ₂ O ₃ formation cycle and the ZrO ₂ formation cycle are repeatedly performed once each to form a second dielectric film 28b having a required thickness.

At this time, TiO ₂ , La ₂ O ₃ besides ZrO ₂ as a raw material mixed with Al ₂ O ₃ in the second dielectric film 28b. Or Ta ₂ O ₅ can be used. As a raw material of the TiO ₂ , Ti (i-OC ₂ H ₇ ) ₄ , Ti (n-OC ₄ H ₉ ) ₄ , Ti (t-OC ₄ H ₉ ) ₄ , Ti (OC ₂ H ₅ ) ₄ , Ti source selected from a group of gases such as Ti (OCH ₃ ) ₄ , Ti (n-OC ₂ H ₇ ) ₄ , Ti (thd) ₃ , Ti (OiPr) _2, and Ti (mpd) (thd) ₂ For the raw material of La ₂ O ₃ , La (tmhd) ₃ and tantalum pentoxide may be used as the raw material of Ta ₂ O ₅ .

Finally, the third dielectric film 28c formed of the same or different types of high dielectric films as the first dielectric film 28a is formed using the same method as the first dielectric film, and is formed to have a thickness of 30 to 50 kHz. Preferably, it is formed of a hafnium oxide film.

The formed dielectric layer may include a first dielectric layer 28a including any one of the high dielectric layers selected from among the high dielectric layers having a dielectric constant of at least 9, and a second dielectric layer including at least two high dielectric layers selected from the high dielectric layers having at least 9 dielectric constants. And a third dielectric film 28c made of a high dielectric film of the same type or different from that of the first dielectric film 28b.

Plasma anneal or UV / O ₃ annealing is performed to remove defects such as impurities such as carbon, hydrogen, and oxygen vacancy in the formed dielectric film. First, the dielectric film is subjected to plasma treatment at a temperature of 300 to 400 ° C. at a power of 50 to 120 W for 30 to 120 seconds in an O ₂ or N ₂ O and N ₂ + O ₂ mixed gas atmosphere. At this time, the chamber pressure is maintained at 0.1 to 1 torr.

In addition, the UV / O ₃ annealing is performed at an intensity of 15 to 30 mW / cm 2 for 2 to 10 minutes at a temperature of 300 to 400 ° C.

As shown in FIG. 2D, an upper electrode is formed on the dielectric layer 28. In this case, TiN may be used as the upper electrode, and chemical vapor deposition (CVD) or physical vapor deposition (PVD) may be used. For example, in the chemical vapor deposition method, TiCl ₄ is used as a raw material, the reaction gas is used as NH ₃ , the flow rate is 10 to 1000 sccm, the pressure of the reaction chamber is 0.1 to 10 torr, and the temperature of the substrate is 500 to 600. It is possible to form the upper electrode at a thickness of 200 to 400 kV by maintaining it at ℃. In addition, the physical vapor deposition method can form a thickness of TiN to 600 to 1000 kPa.

As described above, the present invention can increase the dielectric constant of the laminated dielectric film and maintain the durability by mixing an aluminum oxide film, which is the second dielectric film, with a dielectric film having a larger dielectric constant than the hafnium first dielectric film. In addition, the present invention can also be applied to a cylinder process in which a capacitor oxide film is formed by diping out.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above has the effect of increasing the dielectric constant of the laminated dielectric film and reducing the effective oxide thickness by mixing a material having a higher dielectric constant than the aluminum oxide film in the aluminum oxide film to improve the electrical characteristics of the capacitor.

Claims (12)

Forming a lower electrode; Forming a first dielectric layer on the lower electrode; Forming a second dielectric layer on the first dielectric layer, the second dielectric layer having a dielectric constant having a larger dielectric constant than the first dielectric layer by atomic layer deposition; Forming a third dielectric layer on the second dielectric layer; And Forming an upper electrode on the formed third dielectric layer Manufacturing method of a capacitor comprising a. The method of claim 1, Method for manufacturing a capacitor according to claim wherein the second dielectric layer is _{TiO 2, ZrO 2, La 2} O 3 or Ta ₂ at least any one of materials selected from the group consisting of O ₅ and Al ₂ O ₃ that is mixed. The method according to claim 1 or 2, And the first and third dielectric layers are HfO ₂ . The method of claim 2, The second dielectric film is formed to a thickness of 5 ~ 10Å, the method of manufacturing a capacitor, characterized in that the substrate temperature is maintained at 250 to 500 ℃, the pressure in the reactor to 0.1 to 1torr. The method of claim 1, And annealing the defects on the first, second, and third dielectric layers before forming the upper electrode. The method of claim 3, wherein Wherein the first and third dielectric film is a substrate manufacturing method of 250 ~ 500 ℃, the pressure in the reactor 0.1 ~ 1torr, the thickness of the first dielectric film is 30 ~ 50 kPa The manufacturing method of the capacitor. The method of claim 5, The annealing is a capacitor manufacturing method characterized in that any one of the steps of plasma annealing or UV / O ₃ annealing. The method of claim 7, wherein The plasma annealing is performed at a substrate temperature of 300 to 400 ° C, a flow rate of O ₂ , N ₂ O and N ₂ + O ₂ gas to 100 to 200 sccm, a plasma power of 50 to 200 W, and a plasma treatment time of 30 to 120 seconds. A method of manufacturing a capacitor. The method of claim 7, wherein The UV / O ₃ annealing method of manufacturing a capacitor, characterized in that the substrate temperature 300 ~ 400 ℃, the treatment time 2 ~ 10 minutes, the intensity of the lamp to 15 ~ 30 ㎽ / ㎠. A first dielectric film of HfO ₂ ; A second dielectric film in which Al ₂ O ₃ is mixed with at least one material selected from the group consisting of TiO ₂ , ZrO ₂ , La ₂ O ₃ or Ta ₂ O ₅ formed on the first dielectric film; A third dielectric film of HfO ₂ formed on the second dielectric film Dielectric film of the capacitor comprising a. The method of claim 10, The dielectric layer of the capacitor, characterized in that the first dielectric layer has a thickness of 30 ~ 50Å. The method of claim 10, The dielectric layer of the capacitor, characterized in that the second dielectric film has a thickness of 5 ~ 10Å.

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