KR100713922B1 - Method for forming capacitor of semiconductor device - Google Patents

Abstract

The present invention discloses a method for forming a capacitor of a semiconductor device capable of improving leakage current and breakdown voltage characteristics while ensuring sufficient charge capacity. A method of forming a capacitor of a semiconductor device according to the present invention includes providing a semiconductor substrate on which a storage node contact is formed, forming a metal storage electrode to be connected to the storage node contact, and forming Ta _x on the metal storage electrode. And forming a ternary dielectric film of Zr _y O _z and forming a metal plate electrode on the ternary dielectric film.

Description

Method for forming capacitor of semiconductor device

1A to 1C are cross-sectional views illustrating processes for forming a capacitor of a semiconductor device according to the present invention.

2 is a view for explaining a capacitor dielectric film according to the present invention.

Explanation of symbols on the main parts of the drawings

1 semiconductor substrate 2 interlayer insulating film

3: contact hole 4: storage node contact

10: storage electrode 20: Samsung dielectric dielectric film

30 plate electrode 40 capacitor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a capacitor of a semiconductor device, and more particularly, to a method for forming a capacitor of a semiconductor device capable of securing leakage current characteristics while securing a desired charging capacity.

Recently, as the integration of memory products is accelerated due to the development of semiconductor manufacturing technology, the unit cell area is greatly reduced, and the operating voltage is reduced. As a result, problems such as a short refresh time of the device and a soft error occur, and in order to prevent such a problem, a high charging capacity of 25 fF / cell or more and a low leakage current are generated. The development of capacitors is constantly required.

As is well known, the charge capacity of a capacitor is proportional to the electrode surface area and the dielectric constant of the dielectric, and inversely proportional to the dielectric film thickness corresponding to the distance between electrodes, more precisely, the equivalent SiO2 thickness (Tox) of the dielectric film. Therefore, in order to implement a capacitor having a large charge capacity required in a high density device, it is necessary to use a dielectric film having a high dielectric constant and lowering the equivalent oxide film thickness.

NO (Nitride-Oxide) capacitors using Si3N4 (ε = 7) thin film as a dielectric film have revealed a limitation in securing charge capacity due to high integration, and dielectric constant higher than Si3N4 (ε = 7) to secure sufficient charge capacity. Capacitor of SIS (Polisilicon-Insulator-Polisilicon) structure with Ta2O5 (ε = 25), Al2O3 (ε = 9), La2O3 (ε = 30) and HfO2 (ε = 20) with single dielectric have.

However, the Ta2O5 (ε = 25) film is not only susceptible to leakage current, but also has a problem in that the equivalent oxide film cannot be lowered to 30 kΩ or less due to the oxide film generated during heat treatment.Al2O3 (ε = 9) film has a dielectric constant of ε = 7) As there is no difference with the film, there is a limit to securing a high charging capacity. In addition, the La2O3 and HfO2 films are advantageous in terms of securing charge capacity because the dielectric constants are about 30 and 20, respectively.However, if the thickness of the equivalent oxide film is lowered to 15 mA or less, the leakage current increases and the breakdown voltage strength is greatly reduced, resulting in repeated electrical shock. Since it is fragile, there is a problem of lowering the durability of the capacitor. In particular, the HfO 2 film has a lower crystallization temperature than Al 2 O 3, so that a leakage current increases rapidly during the subsequent high temperature heat treatment of 600 ° C. or higher.

Meanwhile, polysilicon, which has been used as an electrode material in a SIS (Polisilicon-Insulator-Polisilicon) type capacitor, also has a limitation in securing high electrical conductivity required for highly integrated devices. It was intended to be used as an electrode material.

Accordingly, capacitors employing a metal electrode and a double or triple dielectric film have been developed as a capacitor applicable to a highly integrated DRAM process having a fine metal wiring of 100 nm or less. For example, a metal-insulator-polioliicon (MIS) capacitor employing a double dielectric such as metal based electrode (TiN) and HfO2 / Al2O3, or a triple dielectric such as metal based electrode (TiN) and HfO2 / Al2O3 / HfO2. One MIM (Metal-Insulator-Metal) capacitor has been developed.

However, in the case of the conventional MIS or MIM structure capacitor, it is difficult to apply to the device having a metal wiring of 70nm or less. This is because the multiple dielectric films of HfO2 / Al2O3 and HfO2 / Al2O3 / HfO2 of the MIS or MIM capacitor have an equivalent oxide thickness limit of about 12 때문에, which makes it difficult to obtain a charge capacity of 25 fF / cell or more in a DRAM to which a metal wiring of 70 nm or less is applied. .

Recently, development of a MIM capacitor using a metal material such as Ru or TiN as an electrode and using a single dielectric film such as Ta2O5 or HfO2 has been made, but in these cases, when the thickness of the equivalent oxide film is lowered to 12 kW or less, 1fA / cell Because of high leakage current, it is difficult to apply to next generation DRAM of 512M class or more with metal wiring below 70nm class.

Accordingly, the present invention has been made to solve the above-mentioned problems, the MIM type of semiconductor device that can also secure the leakage current characteristics while ensuring the charge capacity required in the next generation DRAM products having a metal wiring of 70nm or less It is an object to provide a method of forming a capacitor.

According to another aspect of the present invention, there is provided a capacitor forming method including: providing a semiconductor substrate on which a storage node contact is formed; Forming a metal storage electrode connected to the storage node contact; Forming a ternary dielectric film of Ta _x Zr _y O _z on the metal storage electrode; And forming a metal plate electrode on the ternary dielectric layer.

Here, the storage electrode and the plate electrode is formed of any one metal-based material selected from the group consisting of TiN, TaN, W, WN, Ru, RuO 2, Ir, IrO 2 and Pt.

After forming the storage electrode and before forming the ternary dielectric layer, the substrate product on which the storage electrode is formed is selected from the group consisting of N2, H2, N2 / H2, O2, O3, and NH3. And annealing at low temperature in one gas atmosphere. In this case, the low temperature annealing is performed by any one method selected from the group consisting of a plasma, an electric furnace and a rapid thermal process (RTP).

The ternary dielectric film is formed to a thickness of 50 to 100 GPa.

The ternary dielectric film is formed in a temperature range of 200 to 500 ° C. according to ALD (Atomic Layer Deposition).

The ternary dielectric film is formed so that x / y, which is the ratio of the mole fraction x of Ta and the mole fraction y of Zr, is in the range of 0.1 to 10.

The formation of a ternary dielectric film of Ta _x Zr _y O _z using the ALD method includes ZrO2 thin film deposition cycle (recovery: n) and [Ta of [Zr source gas flow step, purge step, reaction gas flow step and purge step]. Source gas flow step, purge step, reaction gas flow step and purge step], and repeat the Ta2O5 thin film deposition cycle (recovery: m) while controlling n: m to be in a range of 9: 1 to 1: 9, or Alternatively, another deposition cycle of [Zr source gas flow step, purge step] (recovery: n '), [Ta source gas flow step, purge step] (recovery: m'), reaction gas flow step, and purge step may be used. Proceed by repeating the control with n ': m' to be in the range of 9: 1 to 1: 9.

The ternary dielectric film is formed using ZrCl4 or Zr [N (CH3) C2H5] 4 as the source gas of Zr or any one selected from the group consisting of Zr-containing other compounds, and O3 and O2 as reaction gases. And any one selected from the group consisting of plasma O 2, N 2 O, plasma N 2 O and H 2 O vapor. At this time, the reaction gas flows 0.1 to 1 slm, and when the reaction gas is O 3, the concentration is 100 to 500 g / m 3.

Formation of the ternary dielectric film is any one selected from the group consisting of Ta (OC2H5) 5 or Ta [N (CH3) 2] 5 as the source gas of Ta or other organometallic compounds containing Ta, As the reaction gas, any one selected from the group consisting of O 3, O 2, plasma O 2, N 2 O, plasma N 2 O and H 2 O vapor is used. At this time, the reaction gas flows from 0.1 to 1 slm, when the reaction gas is O 3, the concentration is 100 to 500 g / m 3, and the source gas of Ta flows 50 to 500 sccm.

And annealing the ternary dielectric layer after the forming of the ternary dielectric layer and before forming the metal plate electrode. In this case, the low temperature annealing is performed in any one gas selected from the group consisting of N2, H2, N2 / H2, O2, O3 and NH3 in any one method selected from the group consisting of plasma, electric furnace and RTP method. do. The low temperature annealing is performed by any one method selected from the group consisting of a plasma, an electric furnace, and an RTP method in the same manner as the low temperature annealing of the storage electrode.

The low temperature annealing using the plasma of the storage electrode or the ternary dielectric film is performed using a plasma having an RF power of 100 to 500 W, at a temperature range of 200 to 500 ° C. and a pressure range of 0.1 to 10 torr, by 5 sccm to 5 slm. Run for 1 to 5 minutes while flowing.

Low temperature annealing using the electric furnace of the storage electrode or the ternary dielectric film is performed while flowing the selected gas by 5 sccm to 5 slm at a temperature of 600 to 800 ° C.

Low temperature annealing using the RTP of the storage electrode or the ternary dielectric layer is performed by flowing the selected gas by 5 sccm to 5 slm in an atmospheric pressure (700 to 760 torr) or a reduced pressure (1 to 100 torr) chamber having a temperature range of 500 to 800 ° C. do.

After forming the plate electrode and before proceeding to the subsequent process, any one oxide film or TiN selected from the group consisting of Al 2 O 3, HfO 2, Ta 2 O 5, ZrO 2, TiO 2 and La 2 O 3 on the substrate product on which the plate electrode is formed. The method may further include forming a protective film made of a metal film such as 50-200 mm thick by an ALD method.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In order to obtain a charge capacity of 25 fF / cell or more and a leakage current of 0.5 fF / cell or less required for a 70 nm or less DRAM capacitor, the present invention employs a Ta _x Zr _y O _z ternary dielectric film as a metal electrode. A MIM capacitor is constructed.

In this case, the Ta _x Zr _y O _z (Eg = 4.5-7.8 eV, ε = 25-50) thin film is composed of a Ta2O5 (Eg = 4.5eV, ε = 25) dielectric film and an HfO2 (Eg = 5.7eV, ε = 20) dielectric film. In connection with materials having higher permittivity and relatively large band gap energy (Eg) values, the ternary dielectric film of Ta _x Zr _y O _z is a problem of leakage current of MIM type capacitors employing conventional single dielectric films. And thermal stability problems can be suppressed.

As a result, the MIM capacitor of the present invention employing the ternary dielectric film of Ta _x Zr _y O _z is required for the next generation DRAM product having a 70 nm or less metal wiring even if the equivalent oxide film thickness is lowered to 12 Å or less. It is possible to secure the leakage current characteristics and breakdown voltage characteristics that can be applied to the face while securing a large capacity of the cell.

1A to 1C are cross-sectional views illustrating processes of forming a capacitor of a semiconductor device according to the present invention.

Referring to FIG. 1A, an interlayer insulating layer 2 is formed on an entire surface of a semiconductor substrate 1 on which lower patterns (not shown) including transistors and bit lines are formed. Then, the interlayer insulating layer 2 is etched to form a contact hole 3 exposing the substrate bonding region or the landing plug poly (LPP), and then a conductive layer is embedded in the contact hole to form the storage node contact 4. Form. Subsequently, the storage electrode 10 is formed on the interlayer insulating layer 2 including the storage node contact 4 to be connected to the storage node contact 4.

Here, the storage electrode 10 is formed of any one metal-based material selected from the group consisting of TiN, TaN, W, WN, Ru, RuO2, Ir, IrO2 and Pt, and is formed to a thickness of 200 ~ 500Å. In addition, the storage electrode 10 may be formed of a concave structure or a simple plate structure in addition to the cylindrical structure as shown.

After the storage electrode 10 is formed, the storage electrode 10 is densified and N2 is removed to reduce the roughness on the surface of the electrode while removing residual impurities in the electrode, which causes an increase in leakage current. The low temperature annealing is carried out in any gas atmosphere selected from the group consisting of H2, N2 / H2, O2, O3 and NH3.

In this case, the low temperature annealing is performed by any one method selected from the group consisting of plasma, electric furnace and RTP method. When annealing using a plasma, a plasma having an RF power of 100 to 500 W is used for 1 to 5 minutes while flowing a selected gas by 5 sccm to 5 slm at a temperature range of 200 to 500 ° C. and a pressure range of 0.1 to 10 torr using a plasma having a power of 100 to 500 W. do. On the other hand, when annealing using an electric furnace, a gas selected at 600 to 800 ° C is flowed by 5 sccm to 5 slm, and when annealing using RTP, an atmospheric pressure having a temperature range of 500 to 800 ° C (700 to 760torr) is used. Or in a reduced pressure (1 to 100 torr) chamber while flowing the selected gas by 5 sccm to 5 slm.

Referring to FIG. 1B, a ternary dielectric film 20 of Ta _x Zr _y O _z is formed on the metal storage electrode 10. Here, the ternary dielectric film 20 of Ta _x Zr _y O _z is formed to a thickness of 50 to 100 kPa at an ALD method at a temperature of 200 to 500 ° C. In this case, x, y, and z are mole fractions of Ta, Zr and O, respectively, and the sum thereof is 1, and the ternary dielectric film 20 of Ta _x Zr _y O _z has an x / y value ranging from 0.1 to 10. It is formed to have.

FIG. 2 is a view for explaining the process of forming the ternary dielectric film 20 of Ta _x Zr _y O _z according to the ALD process, and as shown, the ternary dielectric film 20 of Ta _x Zr _y O _z is formed. The process proceeds by repeating the deposition cycle in which "source gas flow, purge, reaction gas flow, purge" is performed repeatedly until a thin film of a desired thickness is obtained.

In detail, the formation of the ternary dielectric film 20 of Ta _x Zr _y O _z using the ALD method is performed by ZrO2 thin film deposition cycle of [Zr source gas flow step, purge step, reaction gas flow step and purge step]. n) and [Ta source gas flow step, purge step, reaction gas flow step and purge step] repeat the Ta2O5 thin film deposition cycle (times: m) while controlling n: m to be in the range of 9: 1 to 1: 9. Or [Zr source gas flow step, purge step] (recovery: n '), [Ta source gas flow step, purge step] (recovery: m'), reaction gas flow step and purge step. Another deposition cycle proceeds in a repeating manner, controlling n ': m' to be in the range of 9: 1 to 1: 9.

Here, any one selected from the group consisting of ZrCl4 or Zr [N (CH3) C2H5] 4 or other compounds containing Zr as the source gas of Zr of the ternary dielectric film 20 of Ta _x Zr _y O _z And any one selected from the group consisting of O 3, O 2, plasma O 2, N 2 O, plasma N 2 O and H 2 O vapor as the reaction gas. At this time, the reaction gas flows from 0.1 to 1 slm, and when the reaction gas is O 3, the concentration is 100 to 500 g / m 3.

Meanwhile, Ta (OC2H5) 5 or Ta [N (CH3) 2] 5 or Ta-containing other organometallic compounds may be used as the source gas of Ta of the triangular dielectric film 20 of Ta _x Zr _y O _z . Any one selected from the group is used, and any one selected from the group consisting of O 3, O 2, plasma O 2, N 2 O, plasma N 2 O and H 2 O vapor is used as the reaction gas. At this time, the source gas of Ta flows 50-500 sccm, and the reaction gas flows 0.1-1 slm. In particular, when the reaction gas is O 3, the concentration is 100 to 500 g / m 3.

In addition, after the formation of the ternary dielectric film 20 of Ta _x Zr _y O _z , and before forming a plate electrode on the ternary dielectric film 20, carbon impurities and crystal grains in the ternary dielectric film 20 are formed. Low temperature annealing is performed to reduce roughness of the thin film surface while ultimately improving leakage current and breakdown voltage characteristics of the dielectric film.

At this time, the low temperature annealing is performed in any one gas atmosphere selected from the group consisting of N2, H2, N2 / H2, O2, O3 and NH3 in the temperature range of 200 ~ 800 ℃, plasma, electric furnace and RTP method This may be done in any way selected from the configured group.

Here, when the low temperature annealing is performed using a plasma, the selected gas is flowed by 5 sccm to 5 slm in a temperature range of 200 to 500 ° C. and a pressure range of 0.1 to 10 tor using a plasma having an RF power of 100 to 500 W. Run for 5 minutes.

On the other hand, when annealing using an electric furnace, a gas selected at 600 to 800 ° C is flowed by 5 sccm to 5 slm, and when annealing using RTP, an atmospheric pressure having a temperature range of 500 to 800 ° C (700 to 760torr) is used. Or in a reduced pressure (1 to 100 torr) chamber while flowing the selected gas by 5 sccm to 5 slm.

Referring to FIG. 1C, a plate electrode 30 made of a metallic material such as TiN, TaN, W, WN, Ru, RuO 2, Ir, IrO 2, and Pt is formed on the ternary dielectric film 20 of Ta _x Zr _y O _z . Then, through this, the formation of the MIM type capacitor 40 according to the present invention in which the ternary dielectric film 20 of Ta _x Zr _y O _z is employed.

Here, after the plate electrode 30 is formed, a protective film for securing structural stability of the capacitor 40 from hydrogen component, moisture, temperature, or electric shock in an environmental test in a subsequent integration process or a package process. For example, an oxide film such as Al 2 O 3, HfO 2, Ta 2 O 5, ZrO 2 and TiO 2 or a protective film made of a metal material such as TiN is preferably deposited to have a thickness of 50 to 200 μm by ALD.

Here, the ternary dielectric film 20 of Ta _x Zr _y O _z has a relatively large band having a higher dielectric constant than the Ta 2 O 5 (Eg = 4.5 eV, ε = 25) dielectric film and the HfO 2 (Eg = 5.7 eV, ε = 20) dielectric film. Since the material has a gap energy, the MIM type capacitor 40 of the present invention employing the ternary dielectric film 20 of Ta _x Zr _y O _z is larger than that of a conventional MIM type capacitor using Ta2O5 or HfO2 single dielectric film. Charge capacity can be obtained and leakage current density can be reduced. In addition, the ternary dielectric film 20 of Ta _x Zr _y O _z has better thermal stability than Ta2O5 or HfO2 single dielectric film, thereby improving performance and reliability of the product.

Accordingly, the capacitor 40 employing the ternary dielectric film 20 of Ta _x Zr _y O _z according to the present invention can be applied while ensuring the charging capacity required for a next generation DRAM product having a metal wiring of 70 nm or less. Leakage current and breakdown voltage characteristics can also be ensured.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, the present invention is a dielectric film of a MIM type capacitor, and has a Ta _x Zr _y O _z film (Eg = 4.5∼) having a higher dielectric constant and a relatively larger band gap energy (Eg) than a conventional Ta2O5 film or HfO2 film. By employing 7.8 eV, epsilon = 25 to 50), it is possible to improve the suppression force of the leakage current generation of the MIM capacitor as compared to the MIM capacitor employing the conventional Ta2O5 film or the HfO2 film as a single dielectric film. More specifically, the MIM capacitor of the present invention can reduce the leakage current generation level to 0.5 fA / cell or less, and can also lower the equivalent oxide film thickness to 12 kPa or less. Accordingly, the MIM capacitor of the present invention can easily secure a charging capacity of 25 fF / cell or more required in a next generation high density memory product of 70 nm or less.

In addition, the present invention has the advantage of overcoming the problem of lack of thermal stability of a single dielectric film such as a conventional HfO 2 film or Ta 2 O 5 film by employing a ternary dielectric film of Ta _x Zr _y O _z . As a result, the deterioration of electrical characteristics is suppressed even at the time of high temperature heat treatment which is inevitably involved in the integration process after the formation of the capacitor, and the durability and reliability of the capacitor are improved.

Claims (18)

Providing a semiconductor substrate on which storage node contacts are formed; Forming a metal storage electrode connected to the storage node contact; Forming a ternary dielectric film of Ta _x Zr _y O _z on the metal storage electrode; And Forming a metal plate electrode on the ternary dielectric layer; and forming a capacitor of a semiconductor device. The method of claim 1, And the storage electrode and the plate electrode are formed of any one metal-based material selected from the group consisting of TiN, TaN, W, WN, Ru, RuO 2, Ir, IrO 2, and Pt. The method of claim 1, Any one selected from the group consisting of N2, H2, N2 / H2, O2, O3 and NH3 is formed after the forming of the storage electrode and before the forming the ternary dielectric layer. Capacitor formation method of a semiconductor device characterized in that it further comprises the step of low temperature annealing in a gas atmosphere of. The method of claim 1, And the ternary dielectric film is formed to a thickness of 50 to 100 GPa. The method of claim 1, The ternary dielectric film is a capacitor forming method of a semiconductor device, characterized in that formed in the temperature range of 200 ~ 500 ℃ according to the ALD method. The method of claim 1, And the ternary dielectric film is formed so that x / y, which is the ratio of mole fraction x of Ta and mole fraction y of Zr, is in the range of 0.1 to 10. The ZrO2 thin film deposition cycle (recovery of Zr source gas flow step, purge step, reaction gas flow step and purge step) according to claim 5, wherein the formation of a ternary dielectric film of Ta _x Zr _y O _z using the ALD method is performed. : n) and Ta2O5 thin film deposition cycle (recovery: m) of [Ta source gas flow step, purge step, reaction gas flow step and purge step] are controlled while controlling n: m to be in the range of 9: 1 to 1: 9. Proceed in the manner of performing, or, [Zr source gas flow step, purge step] (recovery: n '), [Ta source gas flow step, purge step] (recovery: m'), reaction gas flow step and purge step The method of forming a capacitor of a semiconductor device according to claim 1, wherein the deposition cycle is performed in a repeating manner while controlling n ': m' to be in a range of 9: 1 to 1: 9. The method of claim 5, The ternary dielectric film is formed using ZrCl4 or Zr [N (CH3) C2H5] 4 as the source gas of Zr or any one selected from the group consisting of Zr-containing other compounds, and O3 and O2 as reaction gases. And using any one selected from the group consisting of plasma O 2, N 2 O, plasma N 2 O, and H 2 O vapor. The method of claim 5, Formation of the ternary dielectric film is any one selected from the group consisting of Ta (OC2H5) 5 or Ta [N (CH3) 2] 5 as the source gas of Ta or other organometallic compounds containing Ta, A method for forming a capacitor of a semiconductor device, characterized in that any one selected from the group consisting of O 3, O 2, plasma O 2, N 2 O, plasma N 2 O, and H 2 O vapor is used as the reaction gas. The method according to claim 8 or 9, And the reaction gas flows from 0.1 to 1 slm. The method according to claim 8 or 9, The method for forming a capacitor of a semiconductor device, characterized in that the concentration of O3 is 100 to 500g / m3. The method of claim 9, The source gas of Ta flows 50-500 sccm, The capacitor formation method of the semiconductor element characterized by the above-mentioned. The method of claim 1, And annealing the ternary dielectric layer after the forming of the ternary dielectric layer and before the forming the metal plate electrode, at a low temperature. The method according to claim 3 or 13, The low temperature annealing is performed in any one gas selected from the group consisting of N2, H2, N2 / H2, O2, O3 and NH3 in any one method selected from the group consisting of plasma, electric furnace and RTP method. A method for forming a capacitor of a semiconductor element, characterized in that. The method of claim 14, Low temperature annealing using the plasma, using a plasma having an RF power of 100 ~ 500W, in the 200 ~ 500 ℃ temperature range and 0.1 ~ 10torr pressure range, while flowing the selected gas by 5sccm ~ 5slm for 1-5 minutes A method of forming a capacitor of a semiconductor device, characterized in that the progress. The method of claim 14, The low temperature annealing using the electric furnace is performed while flowing the selected gas at a temperature of 600 to 800 ° C. by 5 sccm to 5 slm. The method of claim 14, The low temperature annealing using the RTP is performed while flowing the selected gas by 5 sccm to 5 slm in an atmospheric pressure (700 to 760 torr) or a reduced pressure (1 to 100 torr) chamber having a temperature range of 500 to 800 ° C. Capacitor formation method. The method of claim 1, After forming the plate electrode and before proceeding to the subsequent process, any one oxide film or TiN selected from the group consisting of Al 2 O 3, HfO 2, Ta 2 O 5, ZrO 2, TiO 2 and La 2 O 3 on the substrate product on which the plate electrode is formed. A method of forming a capacitor of a semiconductor device, characterized in that it further comprises the step of forming a protective film made of a metal film, such as 50 to 200 Å thickness by the ALD method.

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