KR20060076375A - Method for forming capacitor of semiconductor device - Google Patents
Method for forming capacitor of semiconductor device Download PDFInfo
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- KR20060076375A KR20060076375A KR1020040114769A KR20040114769A KR20060076375A KR 20060076375 A KR20060076375 A KR 20060076375A KR 1020040114769 A KR1020040114769 A KR 1020040114769A KR 20040114769 A KR20040114769 A KR 20040114769A KR 20060076375 A KR20060076375 A KR 20060076375A
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- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000003990 capacitor Substances 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 239000002184 metal Substances 0.000 claims abstract description 30
- 238000003860 storage Methods 0.000 claims abstract description 26
- 229910004143 HfON Inorganic materials 0.000 claims abstract description 23
- 238000000151 deposition Methods 0.000 claims abstract description 21
- 150000004767 nitrides Chemical class 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000009792 diffusion process Methods 0.000 claims abstract description 6
- 230000004888 barrier function Effects 0.000 claims abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 4
- 239000010703 silicon Substances 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims abstract description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 18
- 238000000231 atomic layer deposition Methods 0.000 claims description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 11
- 239000012159 carrier gas Substances 0.000 claims description 6
- 239000002994 raw material Substances 0.000 claims description 6
- 229910052707 ruthenium Inorganic materials 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 5
- 229910019899 RuO Inorganic materials 0.000 claims description 3
- 229910004121 SrRuO Inorganic materials 0.000 claims description 3
- 229910052741 iridium Inorganic materials 0.000 claims description 3
- 239000007800 oxidant agent Substances 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 238000010926 purge Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000009832 plasma treatment Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 7
- 239000001301 oxygen Substances 0.000 description 7
- 229910052760 oxygen Inorganic materials 0.000 description 7
- 230000007547 defect Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 2
- 238000010406 interfacial reaction Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- NFHFRUOZVGFOOS-UHFFFAOYSA-N palladium;triphenylphosphane Chemical compound [Pd].C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1.C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1.C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1.C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1 NFHFRUOZVGFOOS-UHFFFAOYSA-N 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
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- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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- H01L21/02107—Forming insulating materials on a substrate
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- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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- H10B—ELECTRONIC MEMORY DEVICES
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- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
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Abstract
본 발명은 반도체 소자의 캐패시터 형성방법을 개시한다. 개시된 본 발명에 따른 반도체 소자의 캐패시터 형성방법은, 스토리지 노드 콘택이 구비된 실리콘 기판 상에 질화막과 캡산화막을 차례로 증착하는 단계; 상기 질화막과 캡산화막을 식각하여 스토리지 노드 콘택을 노출시키는 콘택홀을 형성하는 단계; 상기 콘택홀 표면에 금속 스토리지 전극을 형성하는 단계; 상기 금속 스토리지 전극 상에 HfO2/AL2O3/HfO2의 삼중막 구조로 이루어진 유전막을 증착하는 단계; 상기 HfO2/AL2O3/HfO2의 삼중막 구조로 이루어진 유전막 상에 확산방지막으로 HfON막을 증착하는 단계; 상기 HfON막 상에 금속 플레이트 전극을 형성하는 단계;를 포함하는 것을 특징으로 한다. The present invention discloses a method for forming a capacitor of a semiconductor device. A method of forming a capacitor of a semiconductor device according to the present invention includes sequentially depositing a nitride film and a cap oxide film on a silicon substrate having a storage node contact; Etching the nitride layer and the cap oxide layer to form a contact hole exposing a storage node contact; Forming a metal storage electrode on a surface of the contact hole; Depositing a dielectric film having a triple layer structure of HfO 2 / AL 2 O 3 / HfO 2 on the metal storage electrode; Depositing a HfON film as a diffusion barrier on the dielectric film having a triple layer structure of HfO 2 / AL 2 O 3 / HfO 2 ; Forming a metal plate electrode on the HfON film; characterized in that it comprises a.
Description
도 1 내지 도 6은 본 발명에 따른 캐패시터의 형성방법을 설명하기 위한 공정별 단면도.1 to 6 are cross-sectional views for each process for explaining a method of forming a capacitor according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1: 반도체 기판 2: 층간절연막1: semiconductor substrate 2: interlayer insulating film
3: 스토리지 노드 콘택 4: 질화막3: storage node contact 4: nitride
5: 캡산화막 6: 금속 스토리지 전극5: cap oxide film 6: metal storage electrode
7: 유전막 8: 확산방지막용 HfON막7: dielectric film 8: HfON film for diffusion barrier
9: 금속 플레이트 전극 10: 캐패시터9: metal plate electrode 10: capacitor
본 발명은 반도체 소자의 캐패시터 형성방법에 관한 것으로, 보다 상세하게는, 유전막의 산소 결함을 방지하여 누설 전류 특성을 개선시키는 반도체 소자의 캐패시터 형성방법에 관한 것이다. The present invention relates to a method of forming a capacitor of a semiconductor device, and more particularly, to a method of forming a capacitor of a semiconductor device for preventing oxygen defects in a dielectric film to improve leakage current characteristics.
최근 디램(DRAM) 소자의 디자인 룰(Design rule)이 작아짐에 따라 셀 면적은 감소하고 있는 반면 스토리지 전극의 종횡비(aspect ratio)는 매우 커지게 되어, 단위 셀당 요구되는 충전용량의 확보와 아울러 큰 종횡비의 구조에 균일한 두께의 유전막을 형성하기 위한 새로운 기술의 개발이 시급히 요구되고 있다. As the design rules of DRAM devices become smaller, the cell area decreases, but the aspect ratio of the storage electrode becomes very large, thereby ensuring the required charge capacity per unit cell and a large aspect ratio. There is an urgent need to develop a new technology for forming a dielectric film having a uniform thickness in the structure of.
이에, 충전용량의 확보를 위해서 기존 ONO(Oxide-Nitride-Oxide)의 유전막 대신에 유전율이 큰 Al2O3(ε=9), HfO2(ε=20) 또는 이들을 적층한 HfO 2/Al2O3의 유전막을 채용하고자 하는 연구가 활발하게 진행되고 있다. 아울러, 이들 유전막을 큰 종횡비에 대응하기 위해 기존의 화학기상증착(Chemical Vapor Depositio: CVD) 기술 대신에 원자층증착(Atomic Layer Deposition: ALD) 기술이 적용되고 있다. 게다가, 스토리지 및 플레이트 전극 물질로서 기존의 폴리실리콘을 대신하여 금속이 채용되는 추세인데, 그 한 예로서 실리콘(Si) 반도체 공정에의 적합성이 이미 검증된 TiN을 사용하고 있으며, 이러한 MIM (Metal Insulator Metal) 캐패시터에서 플레이트 전극 물질로는 CVD 방식에 따라 증착된 TiN막과 PVD 방식에 따라 증착된 TiN막의 적층막을 주로 사용하게 된다.Therefore, in order to secure the charging capacity, Al 2 O 3 (ε = 9), HfO 2 (ε = 20) having a high dielectric constant or HfO 2 / Al 2 stacked thereon instead of the existing ONO (Oxide-Nitride-Oxide) dielectric film. Research into employing a dielectric film of O 3 has been actively conducted. In addition, in order to cope with the large aspect ratio of these dielectric films, atomic layer deposition (ALD) technology is applied instead of the conventional chemical vapor deposition (CVD) technology. In addition, metals are used instead of conventional polysilicon as storage and plate electrode materials. For example, TiN, which has been proven to be suitable for a silicon (Si) semiconductor process, is used. Metal) In the capacitor, a laminated film of a TiN film deposited by a CVD method and a TiN film deposited by a PVD method is mainly used as a plate electrode material.
그러나, 플레이트 전극으로 TiN막을 증착하는 CVD 공정시, 원료가스로 TiCl4와 NH3를 이용하여 증착하게 되는데, 상기 NH3 가스에 의해서 유전막과 CVD 방식에 따라 증착된 TiN막의 계면 반응이 발생하게 된다. 이때, 유전막내의 산소가 TiN막으로 확산함에 따라 유전막의 산소 결함이 증가하게 되어 누설 전류의 발생이 증가하는 문제점이 발생하게 된다.However, during the CVD process of depositing a TiN film with a plate electrode, the deposition is performed using TiCl 4 and NH 3 as a source gas, and the NH 3 gas causes an interfacial reaction between the dielectric film and the TiN film deposited by the CVD method. . At this time, as oxygen in the dielectric film diffuses into the TiN film, oxygen defects in the dielectric film increase, thereby causing a problem in that leakage current is increased.
따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출된 것으로서, 유전막의 산소결함을 감소시켜 누설 전류가 증가하는 것을 방지할 수 있는 반도체 소자의 캐패시터 형성방법을 제공함에 그 목적이 있다. Accordingly, an object of the present invention is to provide a method for forming a capacitor of a semiconductor device capable of preventing an increase in leakage current by reducing oxygen defects in a dielectric film.
상기와 같은 목적을 달성하기 위하여, 본 발명은, 스토리지 노드 콘택이 구비된 실리콘 기판 상에 질화막과 캡산화막을 차례로 증착하는 단계; 상기 질화막과 캡산화막을 식각하여 스토리지 노드 콘택을 노출시키는 콘택홀을 형성하는 단계; 상기 콘택홀 표면에 금속 스토리지 전극을 형성하는 단계; 상기 금속 스토리지 전극 상에 HfO2/AL2O3/HfO2의 삼중막 구조로 이루어진 유전막을 증착하는 단계; 상기 HfO2/AL2O3/HfO2의 삼중막 구조로 이루어진 유전막 상에 확산방지막으로 HfON막을 증착하는 단계; 상기 HfON막 상에 금속 플레이트 전극을 형성하는 단계;를 포함하는 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of depositing a nitride film and a cap oxide film sequentially on a silicon substrate with a storage node contact; Etching the nitride layer and the cap oxide layer to form a contact hole exposing a storage node contact; Forming a metal storage electrode on a surface of the contact hole; Depositing a dielectric film having a triple layer structure of HfO 2 / AL 2 O 3 / HfO 2 on the metal storage electrode; Depositing a HfON film as a diffusion barrier on the dielectric film having a triple layer structure of HfO 2 / AL 2 O 3 / HfO 2 ; Forming a metal plate electrode on the HfON film; provides a method of forming a capacitor of a semiconductor device comprising a.
상기 금속 스토리지 전극은 CVD 공정에 따라 0.1 내지 1 Torr의 압력 및 500 내지 650℃의 온도 조건에서 TiN막을 증착하여 형성하는 것을 특징으로 한다.The metal storage electrode is formed by depositing a TiN film at a pressure of 0.1 to 1 Torr and a temperature of 500 to 650 ° C. according to a CVD process.
상기 금속 스토리지 전극은 Ru, Pt, Ir, Ru, RuO2, Ir, IrO2, SrRuO3로 구성된 그룹으로부터 선택되는 어느 하나로 이루어진 것이 바람직하다.The metal storage electrode is preferably made of any one selected from the group consisting of Ru, Pt, Ir, Ru, RuO 2 , Ir, IrO 2 , SrRuO 3 .
상기 HfO2/AL2O3/HfO2의 삼중막 구조로 이루어진 유전막은 ALD(Atomic Layer Deposition) 공정에 따라 0.1 내지 1 Torr의 압력 및 250 내지 350℃의 온도 조건에서 증착되는 것을 특징으로 한다. The dielectric film having the triple layer structure of HfO 2 / AL 2 O 3 / HfO 2 is characterized in that the deposition is carried out at a pressure of 0.1 to 1 Torr and a temperature of 250 to 350 ℃ according to the ALD (Atomic Layer Deposition) process.
상기 HfON막은 플라즈마 원자층 증착(Plasma-Enhanced Atomic Layer Deposition : PEALD) 방식에 따라 2 내지 10Å의 두께로 증착하는 것이 바람직하다.The HfON film is preferably deposited to a thickness of 2 to 10 kPa according to the Plasma-Enhanced Atomic Layer Deposition (PEALD) method.
상기 HfON막은, 0.1 내지 1 Torr의 압력 및 250 내지 350℃의 온도 조건에서, 원료물질로 Hf(NEtMe)4를 사용하여 증착되는 것을 특징으로 한다.The HfON film is deposited using Hf (NEtMe) 4 as a raw material at a pressure of 0.1 to 1 Torr and a temperature of 250 to 350 ° C.
상기 HfON막은, 원료물질의 운반가스 및 퍼지가스로 N2 또는 Ar을 이용하고 상기 운반가스의 유량을 150 내지 250 sccm으로 하여 3 내지 10초 동안 플로우하여 증착하는 것이 바람직하다.The HfON film is preferably deposited by using N 2 or Ar as a carrier gas and a purge gas of the raw material, and flowing the carrier gas at a flow rate of 150 to 250 sccm for 3 to 10 seconds.
상기 HfON막은, 플라즈마 파워를 30 내지 500W로 하고, 산화제인 O3의 유량을 200 내지 500 sccm으로 하여 3 내지 10초동안 플로우하며, 플라즈마 처리시 N2O의 유량을 500 내지 2000sccm으로 하여 3 내지 10초동안 플로우하여 증착하는 것을 특징으로 한다.The HfON film has a plasma power of 30 to 500 W, flow rate of oxidant O 3 at 200 to 500 sccm, and flows for 3 to 10 seconds, and at a plasma treatment, the flow rate of N 2 O is 3 to 500 to 2000 sccm. Characterized in that the flow is deposited for 10 seconds.
상기 금속 플레이트 전극은 CVD 방식에 따라 증착된 제1TiN막과 PVD 방식에 따라 증착된 제2TiN의 적층막 구조로서, 상기 제1TiN막은 200 내지 400Å의 두께로 증착되며, 상기 제2TiN막은 600 내지 1000Å의 두께로 증착되는 것이 바람직하다.The metal plate electrode is a laminated film structure of a first TiN film deposited by a CVD method and a second TiN deposited by a PVD method. It is preferable to deposit to a thickness.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1을 참조하면, 반도체 기판(1) 상에 층간절연막(2)을 증착하고 이를 평탄 화한 후에, 스토리지 노드 콘택 형성을 위한 콘택홀을 형성한다. 그 다음, 상기 콘택홀 내에 도전 물질을 매립하여 스토리지 노드 콘택(3)을 형성한다.Referring to FIG. 1, after depositing and planarizing the
도 2를 참조하면, 상기 기판 결과물 상에 질화막(4)을 증착한 다음, 상기 질화막(4) 상에 캡산화막(5)을 증착한다.Referring to FIG. 2, a
도 3을 참조하면, 상기 기판 결과물 상에 콘택홀이 형성될 부분을 노출시키는 마스크(도시안됨)를 형성한 다음, 이를 이용해서 캡산화막(5)과 질화막(4)을 차례로 식각하여 콘택홀을 형성한다. 그런 다음, 상기 콘택홀 내에, 금속막을 증착한 후 이를 CMP하여 금속 스토리지 전극(6)을 형성한다. Referring to FIG. 3, a mask (not shown) for exposing a portion where a contact hole is to be formed is formed on the substrate resultant, and then the
여기서, 상기 금속 스토리지 전극(6)은 CVD 공정에 따라 0.1 내지 1 Torr의 압력 및 500 내지 650℃의 온도 조건에서 TiN막을 증착하여 형성하는 것이 바람직하다.Here, the
또한, 상기 금속 스토리지 전극(6)은 Ru, Pt, Ir, Ru와 RuO2, Ir과 IrO2, SrRuO3등의 금속 및 산화물 중에서 선택하여 형성한다.In addition, the
도 4를 참조하면, 상기 금속 스토리지 전극(6) 상에 유전막(7)을 증착한다. 여기서, 상기 유전막(7)은 ALD(Atomic Layer Deposition) 공정을 통해 0.1 내지 1 Torr의 압력 및 250 내지 350℃의 온도 조건에서 증착한다.Referring to FIG. 4, a
그리고, 상기 유전막(7)은 HfO2/AL2O3/HfO2의 삼중막 구조로 이루어진 것이 바람직한데, 이때 HfO2막은 30 내지 40Å의 두께로 증착하여, AL2O3막은 5 내지 20Å의 두께로 증착한다.
In addition, the
도 5를 참조하면, 상기 유전막(7) 상에 확산방지막용으로 HfON막(8)을 인-시튜(in-situ)로 증착한다. 상기 HfON막(8)은 플라즈마 원자층 증착(Plasma-Enhanced Atomic Layer Deposition : PEALD) 방식에 따라 2 내지 10Å의 두께로 증착한다.Referring to FIG. 5, an
상기 HfON막은, 0.1 내지 1 Torr의 압력 및 250 내지 350℃의 온도 조건에서, 원료물질로 Hf(NEtMe)4(tetrakis(ethylmethylamido)hafnium)를 사용하여 증착한다. 여기서, 상기 HfON막의 증착시 원료물질의 운반가스 및 퍼지가스로 N2 또는 Ar을 이용하고 상기 운반가스의 유량을 150 내지 250 sccm으로 하여 3 내지 10초 동안 플로우시킨다. 또한, 상기 HfON막은, 플라즈마 파워를 30 내지 500W로 하고, 산화제인 O3의 유량을 200 내지 500 sccm으로 하여 3 내지 10초동안 플로우하며, 플라즈마 처리시 N2O의 유량을 500 내지 2000sccm으로 하여 3 내지 10초동안 플로우하여 증착하는 것이 바람직하다.The HfON film is deposited using Hf (NEtMe) 4 (tetrakis (ethylmethylamido) hafnium) as a raw material at a pressure of 0.1 to 1 Torr and a temperature of 250 to 350 ° C. Here, when the HfON film is deposited, N 2 or Ar is used as a carrier gas and a purge gas of a raw material, and the flow rate of the carrier gas is 150 to 250 sccm for 3 to 10 seconds. In addition, the HfON film, the plasma power is 30 to 500W, the flow rate of the oxidizing agent O 3 200 to 500 sccm flows for 3 to 10 seconds, and the plasma flow rate of N 2 O at 500 to 2000 sccm It is desirable to flow and deposit for 3 to 10 seconds.
도 6을 참조하면, 상기 HfON막(8) 상에 금속 플레이트 전극(9)을 증착한다. 상기 플레이트 전극(9)은 CVD 방식에 따라 증착된 제1TiN막과 PVD 방식에 따라 증착된 제2TiN의 적층막 구조인 것이 바람직한데, 상기 제1TiN막은 200 내지 400Å의 두께로 증착하며, 상기 제2TiN막은 600 내지 1000Å의 두께로 증착한다. Referring to FIG. 6, a
상기와 같이, 본 발명은 HfO2/AL2O3/HfO2의 삼중막 구조로 이루어진 유전막(7) 상에 HfON막(8)을 증착함으로써, CVD 방식에 따른 TiN막 증착시, 유전막(7)과 금속 플레이트 전극간의 계면 반응에 의해 유전막의 산소가 금속 플레이트 전극으 로 확산되는 것을 방지함으로써, 유전막의 산소 결함을 감소시킬 수 있게 되어 캐패시터의 누설 전류가 발생하는 것을 방지할 수 있게 된다.As described above, the present invention, by depositing the
여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자는 용이하게 알 수 있을 것이다.Although the present invention has been illustrated and described in connection with specific embodiments herein, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. And one of ordinary skill in the art that the present invention can be modified.
이상에서와 같이, 본 발명은 금속 플레이트 전극의 증착 전 유전막 상에 HfON막을 증착함으로써, 유전막의 산소 결함을 감소시켜 누설 전류 특성을 개선시킬 수 있다. As described above, according to the present invention, by depositing the HfON film on the dielectric film before the deposition of the metal plate electrode, it is possible to reduce the oxygen defect of the dielectric film to improve the leakage current characteristics.
따라서, 본 발명은 반도체 소자의 캐패시터 자체의 신뢰성을 확보할 수 있음은 물론 반도체 소자의 신뢰성 및 제조수율을 향상시킬 수 있다.Therefore, the present invention can ensure the reliability of the capacitor itself of the semiconductor device, as well as improve the reliability and manufacturing yield of the semiconductor device.
Claims (9)
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