KR20070002579A - Method for forming capacitor of semiconductor device - Google Patents

Abstract

A method for forming an MIM capacitor in a semiconductor device is provided to reduce roughness and to restrain grain boundary in a dielectric film by using a TixZryOz thin film as the dielectric film. A semiconductor substrate(1) having a storage node contact(4) is prepared. A metal storage electrode(10) is formed to connect the storage node contact. A dielectric film(20) made of a TixZryOz thin film is formed on the metal storage electrode by ALD(Atomic Layer Deposition) or PE(Plsma Enhanced)-ALD. A metal plate electrode(30) is then formed on the dielectric film, thereby forming an MIM(Metal Insulator Metal) capacitor(40).

Description

Method for forming capacitor of semiconductor device

1A to 1C are cross-sectional views illustrating processes for forming a capacitor of a semiconductor device according to the present invention.

2 is a view for explaining a Ti _x Zr _y O _z dielectric film deposition process according to the present invention.

Explanation of symbols on the main parts of the drawings

1 semiconductor substrate 2 interlayer insulating film

3: contact hole 4: storage node contact

10: storage electrode 20: Ti _x Zr _y O _z dielectric film

30 plate electrode 40 capacitor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a capacitor of a semiconductor device, and more particularly, to a method for forming a capacitor of a semiconductor device capable of securing leakage current characteristics while securing a desired charging capacity.

Recently, as the integration of memory products is accelerated due to the development of semiconductor manufacturing technology, the unit cell area is greatly reduced, and the operating voltage is reduced. As a result, problems such as a short refresh time of the device and a soft error occur, and in order to prevent such a problem, a high charging capacity of 25 fF / cell or more and a low leakage current are generated. The development of capacitors is constantly required.

As is well known, the charge capacity of a capacitor is proportional to the electrode surface area and the dielectric constant of the dielectric, and inversely proportional to the dielectric film thickness corresponding to the distance between electrodes, more precisely, the equivalent SiO2 thickness (Tox) of the dielectric film. Therefore, in order to implement a capacitor having a large charge capacity required in a high density device, it is necessary to use a dielectric film having a high dielectric constant and lowering the equivalent oxide film thickness.

As the NO (Nitride-Oxide) capacitor using a conventional Si3N4 (ε = 7) thin film as a dielectric film has a limit in securing charge capacity due to high integration, a dielectric constant higher than that of Si3N4 (ε = 7) in order to secure sufficient charge capacity. Capacitors of SIS (Polisilicon-Insulator-Polisilicon) structure in which Al2O3 (ε = 9), HfO2 (ε = 20) and Ta2O5 (ε = 25) having a single dielectric are applied.

However, the Al2O3 (ε = 9) film has a limit in securing a high charge capacity because the dielectric constant does not differ from the Si3N4 (ε = 7) film. On the other hand, the HfO2 film has a dielectric constant of about 20, which is advantageous in terms of securing the charge capacity. However, if the thickness of the equivalent oxide film is lowered to 15 mA or less, the leakage current increases and the breakdown voltage strength is significantly reduced, which is vulnerable to repetitive electric shock, thereby lowering the durability of the capacitor. In addition, the Ta2O5 (ε = 25) film has a relatively large dielectric constant, but is not only susceptible to leakage current, but also has a problem in that the equivalent oxide film cannot be lowered to 30 kΩ or less due to the oxide film generated during heat treatment. In particular, the HfO 2 film has a low crystallization temperature, so that a leakage current increases rapidly during a subsequent high temperature heat treatment of 600 ° C. or higher.

In addition, the conventional SIS (Polisilicon-Insulator-Polisilicon) capacitor, in addition to the dielectric film problem, there is a problem that the polysilicon film itself, which is a material used as an electrode material, also has a limitation in securing the high electrical conductivity required in high-density devices. Therefore, there is a need for developing a new type of capacitor incorporating a new electrode material that can realize high electrical conductivity.

Accordingly, as a new capacitor that can be applied to a highly integrated DRAM process having a fine metal wiring of 100 nm or less, conventionally, capacitors employing a metal electrode instead of a polysilicon electrode and employing a double or triple dielectric film have been developed. For example, a metal-insulator-polioliicon (MIS) capacitor employing a double dielectric such as metal based electrode (TiN) and HfO2 / Al2O3, or a triple dielectric such as metal based electrode (TiN) and HfO2 / Al2O3 / HfO2. One MIM (Metal-Insulator-Metal) capacitor has been developed.

However, in the case of the capacitor of the conventional MIS or MIM structure described above, it is difficult to apply to the device having a metal wiring of 70 nm or less because the equivalent oxide film thickness limit is about 12 kHz. In other words, the multiple dielectric films of HfO2 / Al2O3 and HfO2 / Al2O3 / HfO2 of the MIS or MIM capacitor have an equivalent oxide thickness limit of about 12 금속 so that the structure of the electrode is not changed to increase the area of the storage electrode by increasing the structure of the electrode. It is difficult to obtain a charge capacity of more than 25 fF / cell from DRAMs to which wiring is applied.

Recently, the development of a MIM capacitor using a metal such as TiN as an electrode material and employing a single dielectric film such as Ta2O5 (ε = 25), HfO2 (ε = 20) and ZrO2 (ε = 25) has been made. In these cases, crystallites, which cause leakage currents, are formed in the dielectric film deposition process. As a result, a roughness of the surface is intensified, so that an electric field is concentrated at the interface between the electrode and the dielectric film. There is an increasing problem.

Therefore, in the case of the MIM type capacitor using the Ta2O5, HfO2 and ZrO2 films as a single dielectric film, when the thickness of the equivalent oxide film is lowered to 10 mA or less while adopting TiN as an electrode, a high leakage current of about 1 fA / cell is generated. It is difficult to apply to next generation DRAM of 512M class or more with metal wiring.

Accordingly, the present invention has been made to solve the above-mentioned problems, the MIM type of semiconductor device that can also secure the leakage current characteristics while ensuring the charge capacity required in the next generation DRAM products having a metal wiring of 70nm or less It is an object to provide a method of forming a capacitor.

A method of forming a capacitor of a semiconductor device of the present invention for achieving the above object comprises the steps of: providing a semiconductor substrate having a storage node contact; Forming a metal storage electrode connected to the storage node contact; Forming a Ti _x Zr _y O _z dielectric layer on the metal storage electrode; And forming a metal plate electrode on the Ti _x Zr _y O _z dielectric layer.

Here, the storage electrode and the plate electrode is formed of any one metal-based material selected from the group consisting of TiN, Ru, TaN, W, WN, RuO2, Ir, IrO2 and Pt.

After forming the storage electrode and before depositing the Ti _x Zr _y O _z dielectric layer, the surface of the electrode surface is roughened while densifying the storage electrode and removing residual impurities in the electrode, which causes an increase in leakage current. a low temperature annealing of the substrate product on which the storage electrode is formed in a gas atmosphere selected from the group consisting of N2, H2, N2 / H2, O2, O3, and NH3 to alleviate roughness do.

Here, the low temperature annealing is performed in any one method selected from the group consisting of plasma, electric furnace and RTP method.

Low temperature annealing using the plasma, using a plasma having an RF power of 100 ~ 500W, in the 200 ~ 500 ℃ temperature range and 0.1 ~ 10torr pressure range, while flowing the selected gas by 5sccm ~ 5slm for 1-5 minutes Proceed.

On the other hand, the low temperature annealing using the electric furnace proceeds while flowing the selected gas at a temperature of 400 ~ 800 ℃ by 5sccm ~ 5slm, the low temperature annealing using RTP, the atmospheric pressure having a temperature range of 500 ~ 800 ℃ (700 ~ 760torr) Or in the reduced pressure (1 to 100 torr) chamber while flowing the selected gas by 5 sccm to 5 slm.

The Ti _x Zr _y O _z dielectric film is deposited to a thickness of 50 to 150 Pa at a temperature of 200 to 500 ° C. according to ALD or PE-ALD method, wherein x / y values (x and y are mole fractions) are 0.1 to 10. To form a range.

Reaction gas using any one selected from the group consisting of Ti [OCH (CH3) 2] 4 or other organometallic compounds containing Ti as the source gas of the Ti component of the Ti _x Zr _y O _z dielectric film Furnace selected from the group consisting of O 3 (concentration: 200 ± 20 g / m 3), O 2, plasma O 2, N 2 O, plasma N 2 O and H 2 O vapor. At this time, the reaction gas flows 0.1 to 1 slm.

ZrCl4 or Zr [N (CH3) C2H5] 4 is used as the source gas of Zr of the Ti _x Zr _y O _z dielectric layer, or any one selected from the group consisting of other compounds containing Zr is used as the reaction gas. Any one selected from the group consisting of O 3 (concentration: 100 to 500 g / m 3), O 2, plasma O 2, N 2 O, plasma N 2 O and H 2 O vapor is used. At this time, the reaction gas flows 0.1 to 1 slm.

The deposition of the Ti _x Zr _y O _z thin film using the ALD method includes the ZrO thin film deposition cycle of the Zr source gas flow step, the purge step, the reaction gas flow step, and the purge step (number: n), the Ti source gas flow step, and the purge step. The TiO thin film deposition cycle (number: m) of the steps, the reaction gas flow step, and the purge step is repeatedly performed while controlling the ratio of n to m to be 7: 3 or less, or [Zr source gas flow and Proceeding with a deposition method including a purge step], a Ti source gas flow and purge step, and a reactive gas flow and purge step, wherein the Zr source gas flow and purge step versus the Ti source gas flow and purge step ] Is controlled while controlling the deposition method so that the ratio of 7:] or less.

The deposition of the Ti _x Zr _y O _z thin film using the PE-ALD method is performed at least once in a cycle to improve the film quality during the Ti _x Zr _y O _z thin film deposition cycle by the ALD method. Discharge and proceed.

After depositing the Ti _x Zr _y O _z dielectric film according to the ALD or PE-ALD method, and before forming the metal plate electrode, carbon impurities and grains in the dielectric film are removed and the roughness of the dielectric film surface is removed. In order to reduce the degree and ultimately improve the leakage current and breakdown voltage characteristics of the dielectric film, the substrate resultant on which the dielectric film is deposited is selected in a gas atmosphere selected from the group consisting of N2, H2, N2 / H2, O2, O3 and NH3. Further comprising a low temperature annealing.

In this case, the low temperature annealing is performed in any one method selected from the group consisting of plasma, electric furnace, and RTP method, under the same conditions as the low temperature annealing condition of the storage electrode.

After forming the plate electrode and before proceeding to the subsequent process, Al2O3 is formed on the substrate product on which the plate electrode is formed to ensure structural stability of the device from hydrogen component, moisture, temperature, and electric shock in the subsequent process. And forming an oxide film selected from the group consisting of HfO 2, Ta 2 O 5, ZrO 2 and TiO 2, or a protective film made of a metal film such as TiN, having a thickness of 50 to 200 μm by ALD.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention provides a MIM type employing a Ti _x Zr _y O _z dielectric film on a metal storage electrode for the purpose of obtaining a charge capacity of 25 fF / cell or more and a leakage current of 0.5 fF / cell or less required for a 70 nm or less DRAM capacitor. Configure the capacitor.

In the case of the MIM capacitor employing Ta2O5 (ε = 25), HfO2 (ε = 20), and ZrO2 (ε = 25) as a single dielectric film, crystallites causing leakage current during the deposition of the dielectric film Formed, and the surface roughness (deepness) is deepened, the leakage current increases, but the Ti _x Zr _y O _z thin film employed as the dielectric film in the present invention alternately deposited TiO and ZrO during the ALD deposition process Due to the lattice mismatch effect, grain formation can be suppressed, and the degree of roughness of the thin film can be reduced, so that leakage current can be effectively suppressed.

Accordingly, the capacitor of the present invention employing the Ti _x Zr _y O _z dielectric film can reduce the equivalent oxide film thickness to 10 Å or less, and as a result, the charge capacity required for the next generation DRAM products having a metal wiring of 70 nm or less. In addition, the applicable leakage current and breakdown voltage characteristics can be secured.

1A to 1C are cross-sectional views of processes for explaining a method of forming a capacitor of a semiconductor device according to the present invention.

Referring to FIG. 1A, an interlayer insulating layer 2 is formed on an entire surface of a semiconductor substrate 1 on which lower patterns (not shown) including transistors and bit lines are formed. Then, the interlayer insulating layer 2 is etched to form a contact hole 3 exposing the substrate bonding region or the landing plug poly (LPP), and then a conductive layer is embedded in the contact hole to form the storage node contact 4. Form. Subsequently, the storage electrode 10 is formed on the interlayer insulating layer 2 including the storage node contact 4 to be connected to the storage node contact 4.

Here, the storage electrode 10 is formed of any one metal-based material selected from the group consisting of TiN, Ru, TaN, W, WN, RuO2, Ir, IrO2, and Pt, and is formed to a thickness of 100 ~ 500Å. In addition, the storage electrode 10 may be formed of a concave structure or a simple plate structure in addition to the cylindrical structure as shown.

After the storage electrode 10 is formed, the storage electrode 10 is densified and N2 is removed to reduce the roughness on the surface of the electrode while removing residual impurities in the electrode, which causes an increase in leakage current. Low temperature annealing at 200 to 800 ° C. is carried out in a H 2, N 2 / H 2, O 2, O 3 or NH 3 atmosphere.

In this case, the low temperature annealing is performed by any one method selected from the group consisting of plasma, electric furnace and RTP method. Here, when the low temperature annealing using the plasma, using a plasma having an RF power of 100 ~ 500W, in the 200 ~ 500 ℃ temperature range and 0.1 ~ 10torr pressure range, the selected gas flows by 5sccm ~ 5slm 1-5 Proceed for minutes. On the other hand, when annealing using an electric furnace, a gas selected at 400 to 800 ° C. is flowed by 5 sccm to 5 slm, and when annealing using RTP, an atmospheric pressure having a temperature range of 500 to 800 ° C. (700 to 760 torr) is performed. Or in a reduced pressure (1 to 100 torr) chamber while flowing the selected gas by 5 sccm to 5 slm.

Referring to FIG. 1B, a Ti _x Zr _y O _z dielectric layer 20 is deposited on the storage electrode 10 to a thickness of 50 to 150 kPa at a temperature of 200 to 500 ° C. according to an ALD or PE-ALD method. Here, x, y, z are mole fractions, the sum of which is 1, and the Ti _x Zr _y O _z dielectric film is formed so that the x / y value is in the range of 0.1 to 10.

2 is a view for explaining the deposition process of the Ti _x Zr _y O _z dielectric film 20 according to the ALD or PE-ALD process, as shown, Ti _x Zr _y O _z dielectric film 20 using the ALD method ) ZrO thin film deposition cycle (number: n) of Zr source gas flow step, purge step, reaction gas flow step and purge step and Ti source gas flow step, purge step, reaction gas flow step and purge step TiO The thin film deposition cycle (number: m) is repeatedly performed while controlling the ratio of n to m to be 7: 3 or less, or [Zr source gas flow and purge step], [Ti source gas flow and The purge step] and [reaction gas flow and purge step], wherein the ratio of [Zr source gas flow and purge step] to [Ti source gas flow and purge step] is 7: 3 or less. Deposition method Proceeds while air.

Meanwhile, the deposition of the Ti _x Zr _y O _z dielectric film 20 using the PE-ALD method is performed at least in a cycle such that the film quality is improved during the progress of the Ti _x Zr _y O _z thin film deposition cycle by the ALD method. The plasma is discharged at least once.

At this time, any one selected from the group consisting of Ti [OCH (CH3) 2] 4 or other organometallic compounds containing Ti is used as the source gas of the Ti component during the deposition of the Ti _x Zr _y O _z dielectric film 20. One is used and any one selected from the group consisting of O 3 (concentration: 200 ± 20 g / m 3), O 2, plasma O 2, N 2 O, plasma N 2 O and H 2 O vapor is used as the reaction gas. At this time, the reaction gas flows 0.1 to 1 slm.

In addition, as a source gas of Zr of the Ti _x Zr _y O _z dielectric layer, any one selected from the group consisting of ZrCl 4 or Zr [N (CH 3) C 2 H 5] 4, or other compounds containing Zr, may be used. As the gas, any one selected from the group consisting of O 3 (concentration: 100 to 500 g / m 3), O 2, plasma O 2, N 2 O, plasma N 2 O, and H 2 O vapor is used. At this time, the reaction gas flows 0.1 to 1 slm.

As described above, after depositing the Ti _x Zr _y O _z dielectric film 20 according to the ALD or PE-ALD method, the carbon impurities and grains in the dielectric film are removed and the degree of roughness of the dielectric film surface is ultimately reduced. Low temperature annealing is performed at 200 to 800 ° C. in an N 2, H 2, N 2 / H 2, O 2, O 3, or NH 3 atmosphere to improve leakage current and breakdown voltage characteristics of the dielectric film.

In this case, the low temperature annealing is performed by any one method selected from the group consisting of a plasma, an electric furnace, and an RTP method, and the annealing of the plasma, an electric furnace, and an RTP method is performed under the same conditions as the low temperature annealing condition of the storage electrode. Proceed.

Referring to FIG. 1C, a plate electrode 30 made of metal materials such as TiN, TaN, W, WN, Ru, RuO 2, Ir, IrO 2, and Pt is formed on the Ti _x Zr _y O _z dielectric layer 20. Through this, the formation of the capacitor 40 according to the present invention employing the Ti _x Zr _y O _z dielectric film 20 is completed.

Here, after the plate electrode 30 is formed, a protective film for securing structural stability of the capacitor 40 from hydrogen, moisture, temperature, or electric shock in an environmental test in a subsequent integration process or a package process. For example, it is preferable to deposit an oxide film selected from the group consisting of Al 2 O 3, HfO 2, Ta 2 O 5, ZrO 2 and TiO 2 or a protective film made of a metal material such as TiN to a thickness of 50 to 200 μm by ALD.

Hereinbefore, the present invention has been illustrated and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications and variations can be made.

As described above, the present invention, by applying the Ti _x Zr _y O _z thin film according to the ALD or PE-ALD method as the dielectric film of the MIM type capacitor, suppresses the formation of grains that cause an increase in leakage current in the dielectric film, The degree of roughness can also be lowered. Accordingly, the MIM capacitor of the present invention employing the Ti _x Zr _y O _z dielectric film has conventional Ta2O5 (ε = 25), HfO2 (ε = 20), ZrO2 (ε = 25) and TiO2 having high dielectric constant (ε = The leakage current characteristic (0.5 fA / cell or less) can be obtained lower than that of the MIM capacitor which employs 40 to 80 as a single dielectric film.

In addition, the MIM capacitor of the present invention employing a Ti _x Zr _y O _z dielectric film has an equivalent oxide film thickness of 10 kW, which is smaller than that of conventional Ta2O5 (ε = 25), HfO2 (ε = 20) and ZrO2 (ε = 25) films. It can be lowered to below, and thus it is possible to secure a charging capacity of 25 fF / cell or more required in a next generation DRAM product of 512 M class or more having a metal wiring of 70 nm or less.

Claims (17)

Providing a semiconductor substrate on which storage node contacts are formed; Forming a metal storage electrode connected to the storage node contact; Forming a Ti _x Zr _y O _z dielectric layer on the metal storage electrode; And And forming a metal plate electrode on the Ti _x Zr _y O _z dielectric layer. The method of claim 1, And the storage electrode and the plate electrode are formed of any one metal material selected from the group consisting of TiN, Ru, TaN, W, WN, RuO 2, Ir, IrO 2, and Pt. The method of claim 1, After forming the storage electrode and before forming the Ti _x Zr _y O _z dielectric layer, the substrate product on which the storage electrode is formed is formed from a group consisting of N2, H2, N2 / H2, O2, O3, and NH3. Capacitor forming method of a semiconductor device characterized in that it further comprises the step of low temperature annealing in any one selected gas atmosphere. The method of claim 1, And the Ti _x Zr _y O _z dielectric layer is formed so that x / y values (x and y are mole fractions) are in a range of 0.1 to 10. The method of claim 1, The Ti _x Zr _y O _z dielectric film is deposited to a thickness of 50 ~ 150 Pa at a temperature of 200 ~ 500 ℃ according to the ALD or PE-ALD method. The method of claim 5, Reaction gas using any one selected from the group consisting of Ti [OCH (CH3) 2] 4 or other organometallic compounds containing Ti as the source gas of the Ti component of the Ti _x Zr _y O _z dielectric film The method for forming a capacitor of a semiconductor device, characterized in that carried out using any one selected from the group consisting of O3 (concentration: 200 ± 20g / m3), O2, plasma O2, N2O, plasma N2O and H2O vapor. The method of claim 5, ZrCl4 or Zr [N (CH3) C2H5] 4 is used as the source gas of Zr of the Ti _x Zr _y O _z dielectric layer, or any one selected from the group consisting of Zr-containing other compounds, and the reaction gas A method for forming a capacitor of a semiconductor device, characterized by using any one selected from the group consisting of O 3 (concentration: 100 to 500 g / m 3), O 2, plasma O 2, N 2 O, plasma N 2 O, and H 2 O vapor. The method according to claim 6 or 7, And the reaction gas flows from 0.1 to 1 slm. The method of claim 5, The deposition of the Ti _x Zr _y O _z thin film using the ALD method may include a ZrO thin film deposition cycle (number: n) and a Ti source gas flow step and purge of a Zr source gas flow step, a purge step, a reaction gas flow step, and a purge step. Forming a capacitor of a semiconductor device, characterized in that the step of repeating the step of controlling the TiO thin film deposition cycle (number: m) of the step, the reaction gas flow step and the purge step so that the ratio of n to m is less than 7: 3 Way. The method of claim 5, The deposition of the Ti _x Zr _y O _z thin film using the ALD method is performed by a deposition method including [Zr source gas flow and purge step], [Ti source gas flow and purge step], and [reaction gas flow and purge step]. Proceed while controlling the deposition method so that the ratio of the [Zr source gas flow and purge step] to the [Ti source gas flow and purge step] is 7: 3 or less. . The method of claim 5, Deposition of the Ti _x Zr _y O _z thin film using the PE-ALD method is performed by discharging the plasma at least once in one cycle during the Ti _x Zr _y O _z thin film deposition cycle by the ALD method. A method of forming a capacitor of a semiconductor device. The method of claim 5, After depositing the Ti _x Zr _y O _z dielectric film according to the ALD or PE-ALD method, and before forming the metal plate electrode, the substrate product on which the dielectric film is deposited is N2, H2, N2 / H2, And annealing at a low temperature in any one of a gas atmosphere selected from the group consisting of O 2, O 3 and NH 3. The method according to claim 3 or 12, wherein The low temperature annealing is performed by any one method selected from the group consisting of a plasma, an electric furnace and an RTP method. The method of claim 13, Low temperature annealing using the plasma, using a plasma having an RF power of 100 ~ 500W, in the 200 ~ 500 ℃ temperature range and 0.1 ~ 10torr pressure range, while flowing the selected gas by 5sccm ~ 5slm for 1-5 minutes A method of forming a capacitor of a semiconductor device, characterized in that the progress. The method of claim 13, The low temperature annealing using the electric furnace is performed while flowing the selected gas by 5 sccm to 5 slm at a temperature of 400 to 800 ° C. The method of claim 13, The low temperature annealing using the RTP is performed while flowing the selected gas by 5 sccm to 5 slm in an atmospheric pressure (700 to 760 torr) or a reduced pressure (1 to 100 torr) chamber having a temperature range of 500 to 800 ° C. Capacitor formation method. The method of claim 1, After forming the plate electrode and before proceeding to the subsequent process, any one of an oxide film or TiN selected from the group consisting of Al 2 O 3, HfO 2, Ta 2 O 5, ZrO 2 and TiO 2 is formed on the substrate product on which the plate electrode is formed. A method of forming a capacitor of a semiconductor device, characterized by further comprising the step of forming a protective film made of a metal film to a thickness of 50 ~ 200∼ by ALD method.

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