CN102148149A - Method for forming grid of semiconductor device - Google Patents
Method for forming grid of semiconductor device Download PDFInfo
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- CN102148149A CN102148149A CN2010190630240A CN201019063024A CN102148149A CN 102148149 A CN102148149 A CN 102148149A CN 2010190630240 A CN2010190630240 A CN 2010190630240A CN 201019063024 A CN201019063024 A CN 201019063024A CN 102148149 A CN102148149 A CN 102148149A
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Abstract
The invention relates to a method for forming a grid of a semiconductor device, comprising the following steps of: (a) providing a substrate, sequentially forming a grid oxidation layer, a polysilicon layer, a dielectric layer and a bottom anti-reflection layer on the substrate, and forming patterned photoresist on the bottom anti-reflection layer; (b) with the patterned photoresist as a mask, etching the bottom anti-reflection layer and the dielectric layer to form a patterned bottom anti-reflection layer and a patterned bottom anti-reflection layer, and removing the photoresist; and (c) with the patterned bottom anti-reflection layer and the patterned dielectric layer as masks, patterning the polysilicon layer and the grid oxidation layer by etching, thus the grid is obtained by the patterned polysilicon layer. By adopting the technical scheme, the grid profile is improved, and the stability of performances of the device and the yield are all improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, especially a kind of formation method of grid of semiconductor device.
Background technology
Along with the deep development of very lagre scale integrated circuit (VLSIC) (VLSI), the device integrated level on the semiconductor chip improves day by day, the physical dimension of device then reduces day by day.When the physical dimension of device reduced, the manufacturing process of device was subjected to increasing challenge.
Grid with semiconductor device (for example metal-oxide-semiconductor), existing formation method can be referring to accompanying drawing 1a, on substrate 10, be formed with gate oxide 11, polysilicon layer 12, bottom anti-reflection layer 13 successively, form patterned photoresist 14 on bottom anti-reflection layer 13, wherein bottom anti-reflection layer 13 can be organic antireflection layer; With described photoresist 14 is mask, and etching bottom anti-reflection layer 13 is graphical with bottom anti-reflection layer 13; Bottom anti-reflection layer 13 with patterning is a mask again, and etch polysilicon layer 12 forms grid.
Grid through above-mentioned technology forms mainly has following two defectives: the first, and the edge is comparatively coarse, referring to Fig. 1 b.For example, for certain a product, the roughness of grid width CD (deviation of grid width maximum and minimum value) reaches 10nm, and the average of roughness reaches 7.3nm.The second, the end of grid produces and retracts phenomenon (pull back), forms beak shape, referring to Fig. 1 c.Retract phenomenon and cause the distance between the neighboring gates end to increase, for example in the said goods, between the neighboring gates end apart from d average out to 73.6nm.Above-mentioned defective can influence the consistency of gate features size, influences the overlapping area of grid and active area, causes the reduction of yield of devices and stability.
Summary of the invention
Technical problem to be solved by this invention is in the prior art, the deficiency that gate profile is undesirable, the characteristic size consistency is relatively poor.
For solving the problems of the technologies described above, the technical solution adopted in the present invention is: a kind of formation method of grating of semiconductor element, comprise the steps: that (a) provides substrate, on substrate, form gate oxide, polysilicon layer, dielectric substance layer, bottom anti-reflection layer successively, on bottom anti-reflection layer, form patterned photoresist; (b) be mask with described patterned photoresist, etching bottom anti-reflection layer, dielectric substance layer form patterned bottom anti-reflection layer, dielectric substance layer, remove photoresist; (c) be mask with described patterned bottom anti-reflection layer, dielectric substance layer, with graphical polysilicon layer, gate oxide, graphical polysilicon layer forms grid by etching.
Because the employing of technique scheme, make the improvement of gate profile, device performance stability and yield all are improved.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by actual size equal proportion convergent-divergent.
Fig. 1 a is the schematic diagram of grid etch step in the prior art;
Fig. 1 b is the cutaway view of the grid of prior art formation;
Fig. 1 c is the side-looking thumbnail of Fig. 1 b;
Fig. 2 a to 2d is the schematic diagram of the first embodiment grid formation method
Fig. 3 is the schematic diagram of grid etch step among second embodiment.
Embodiment
[embodiment one]
Present embodiment passes through the improvement to mask layer, and then improves the formation method of formed grid, the grid that the acquisition profile is optimized.
The formation method of the grid that present embodiment proposed may further comprise the steps: substrate (a) is provided, forms gate oxide, polysilicon layer, dielectric substance layer, bottom anti-reflection layer successively on substrate, form patterned photoresist on bottom anti-reflection layer; (b) be mask with described patterned photoresist, etching bottom anti-reflection layer, dielectric substance layer form patterned bottom anti-reflection layer, dielectric substance layer, remove photoresist; (c) be mask with described patterned bottom anti-reflection layer, dielectric substance layer, with graphical polysilicon layer, gate oxide, graphical polysilicon layer forms grid by etching.
Below in conjunction with accompanying drawing 2a to 2d above-mentioned formation method is described in detail.
(a) provide substrate, on substrate, form gate oxide, polysilicon layer, dielectric substance layer, bottom anti-reflection layer successively, on bottom anti-reflection layer, form patterned photoresist;
Referring to Fig. 2 a, substrate 20 is provided, this substrate 20 can be to have carried out pre-doping, doping, has formed the Semiconductor substrate of well region.
Utilize on substrate, the grow gate oxide 21 of one deck densification of high temperature furnace pipe oxidation technology, described high temperature furnace pipe oxidation technology can for dry oxidation (with O
2Be raw material) or wet oxidation (with H
2O is a raw material), also can adopt other alternative techniques.
Adopt the technology of chemical vapour deposition (CVD) to form polysilicon layer 22 on gate oxide 21, described polysilicon layer 22 is used for forming follow-up polysilicon gate.
Form dielectric substance layer 23 on polysilicon layer 22, the material of described dielectric substance layer 23 can be silicon oxynitride, silica, silicon nitride etc.; Preferably have the material of big dielectric constant K value, for example the K value can be so that dielectric substance layer 23 has bigger density and hardness greater than 3; The formation technology of dielectric substance layer 23 can be chemical vapour deposition (CVD) or high temperature furnace pipe growth; The thickness of dielectric substance layer 23 is
Form anti-reflecting layer 24 on dielectric substance layer 23, using more anti-reflecting layer 24 in the advanced semiconductor fabrication process is silicon-based polymer, and this silicon-based polymer is liquid, and spin coating is after the hot setting moulding.The thickness of anti-reflecting layer 24 can be 20nm～200nm scope.
Spin coating photoresist material, soft baking on anti-reflecting layer 24, expose, cure, develop, form patterned photoresist 25, the figure in the photoresist 25 exposes anti-reflecting layer 24.Need to prove that dielectric substance layer 23 also plays certain antireflection effect in this step, can further reduce reflection ray, help exposure technology carrying out, guarantee that the size of figure in the photoresist 25 is consistent with mask.
(b) be mask with described patterned photoresist, etching bottom anti-reflection layer, dielectric substance layer form patterned bottom anti-reflection layer, dielectric substance layer, remove photoresist;
Referring to Fig. 2 b, be mask with described patterned photoresist 25, with dry etching bottom anti-reflection layer 24, dielectric substance layer 23, form patterned bottom anti-reflection layer, dielectric substance layer.The etching that is noted that bottom anti-reflection layer 24, dielectric substance layer 23 is to finish in a step, helps shortening process cycle.
Referring to Fig. 2 c, ashing method is removed photoresist 25.
(c) be mask with described patterned bottom anti-reflection layer, dielectric substance layer, with graphical polysilicon layer, gate oxide, graphical polysilicon layer forms grid by etching.
Referring to Fig. 2 d, with described patterned bottom anti-reflection layer 24, dielectric substance layer 23 is mask, by dry etching with graphical polysilicon layer 22, gate oxide 21, exposure substrate 20, graphical polysilicon layer 22 has formed the polysilicon gate of semiconductor device.In this step, comparatively fine and close dielectric layer 23 is as hard mask, and the process of dry etching can keep shape, can play good figure transmission effect, makes the profile of polysilicon gate keep better.
Also comprise the step of removing bottom anti-reflection layer 24, dielectric substance layer 23 afterwards, and injection, backend interconnect technology etc. are leaked in the formation of grid curb wall, source.
The grid that the formation method of employing present embodiment obtains, compared to existing technology, the roughness of grid width reduces, and the phenomenon that retracts of grid end alleviates, and the perpendicularity of gate lateral wall is also better.With with background technology in cited certain a product be example, adopt after the method for present embodiment, the roughness average of the width of grid is reduced to 4.8nm from 7.3nm; Average distance between the neighboring gates end is reduced to 64.6nm from 73.6nm; And the perpendicularity of gate lateral wall is obviously improved.More than the improvement of various gate profiles can play the effect that improves device performance stability, improves yield of devices.
[embodiment two]
Embodiment two and embodiment one are roughly the same, just after forming polysilicon layer 22, also on polysilicon layer 22, form surface barrier 26, inject the electric conductivity that improves polysilicon layer 22 by ion afterwards, described surface barrier 26 can be silica, and surface barrier 26 can improve the uniformity that ion injects.Afterwards, dielectric substance layer 23 is formed on the surface barrier 26, referring to Fig. 3.
Accordingly, the formation method of grid is: substrate (a) is provided, on substrate, form gate oxide, polysilicon layer, surface barrier successively, by surface barrier polysilicon layer being carried out ion injects, on surface barrier, form dielectric substance layer, bottom anti-reflection layer, on bottom anti-reflection layer, form patterned photoresist; (b) be mask with described patterned photoresist, etching bottom anti-reflection layer, dielectric substance layer form patterned bottom anti-reflection layer, dielectric substance layer, remove photoresist; (c) be mask with described patterned bottom anti-reflection layer, dielectric substance layer, with patterned surface barrier layer, polysilicon layer, gate oxide, graphical polysilicon layer forms grid by etching.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (4)
1. the formation method of a grating of semiconductor element comprises the steps: that (a) provides substrate, forms gate oxide, polysilicon layer, dielectric substance layer, bottom anti-reflection layer on substrate successively, forms patterned photoresist on bottom anti-reflection layer; (b) be mask with described patterned photoresist, etching bottom anti-reflection layer, dielectric substance layer form patterned bottom anti-reflection layer, dielectric substance layer, remove photoresist; (c) be mask with described patterned bottom anti-reflection layer, dielectric substance layer, with graphical polysilicon layer, gate oxide, graphical polysilicon layer forms grid by etching.
2. method according to claim 1, it is characterized in that, comprise the steps: that (a) provides substrate, on substrate, form gate oxide, polysilicon layer, surface barrier successively, by surface barrier polysilicon layer being carried out ion injects, on surface barrier, form dielectric substance layer, bottom anti-reflection layer, on bottom anti-reflection layer, form patterned photoresist; (b) be mask with described patterned photoresist, etching bottom anti-reflection layer, dielectric substance layer form patterned bottom anti-reflection layer, dielectric substance layer, remove photoresist; (c) be mask with described patterned bottom anti-reflection layer, dielectric substance layer, with patterned surface barrier layer, polysilicon layer, gate oxide, graphical polysilicon layer forms grid by etching.
3. according to claim 1 or 2 described methods, it is characterized in that: the material of described dielectric substance layer is a kind of in silicon oxynitride, silica, the silicon nitride.
4. according to claim 1 or 2 described methods, it is characterized in that: anti-reflecting layer is a silicon-based polymer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010190630240A CN102148149A (en) | 2010-02-05 | 2010-02-05 | Method for forming grid of semiconductor device |
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| CN2010190630240A CN102148149A (en) | 2010-02-05 | 2010-02-05 | Method for forming grid of semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103346076A (en) * | 2013-06-27 | 2013-10-09 | 上海华力微电子有限公司 | Method for modifying defects of gate-oxide active region |
| CN105470120A (en) * | 2014-06-18 | 2016-04-06 | 上海华力微电子有限公司 | Polysilicon etching method |
| CN112366179A (en) * | 2020-10-15 | 2021-02-12 | 长江存储科技有限责任公司 | Semiconductor device structure and preparation method |
-
2010
- 2010-02-05 CN CN2010190630240A patent/CN102148149A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103346076A (en) * | 2013-06-27 | 2013-10-09 | 上海华力微电子有限公司 | Method for modifying defects of gate-oxide active region |
| CN103346076B (en) * | 2013-06-27 | 2016-05-11 | 上海华力微电子有限公司 | Improve the method for grid oxygen active area defect |
| CN105470120A (en) * | 2014-06-18 | 2016-04-06 | 上海华力微电子有限公司 | Polysilicon etching method |
| CN112366179A (en) * | 2020-10-15 | 2021-02-12 | 长江存储科技有限责任公司 | Semiconductor device structure and preparation method |
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Application publication date: 20110810 |