TWI515825B - Semiconductor structure and manufacturing method for the same - Google Patents

Description

Semiconductor structure and method of manufacturing same

This invention relates to a semiconductor structure and method of fabricating the same, and more particularly to a method of fabricating a semiconductor structure incorporating a damascene process and a self-aligned shallow trench isolation process.

With the advancement of semiconductor technology, the shrinking capability of electronic components has been increasing, enabling electronic products to have more functions while maintaining a fixed size or even a smaller volume. As the processing volume of information becomes higher and higher, the demand for large-capacity and small-volume memory is also growing.

Devices in different areas usually need to be integrated into different processes to manufacture. However, the process applied to an intended area easily affects other unintended areas, causing the structure of the device on the unintended area to be affected.

The present invention relates to a semiconductor structure and a method of fabricating the same, which can properly integrate different kinds of processes to obtain a product having a desired quality.

According to an aspect of the invention, a method of fabricating a semiconductor structure is provided, comprising the following steps. Forming a first gate structure on a substrate in a first region. The substrate includes an adjacent first semiconductor layer and a second semiconductor layer. A protective layer is formed to cover the first gate structure. An isolation structure is formed between a sidewall of the first semiconductor layer and a sidewall of the second semiconductor layer. Forming a second gate structure on the first semiconductor layer in a second region adjacent to the first region exposed by the protective layer. A third gate structure is formed on the second semiconductor layer exposed by the protective layer. After forming the second gate structure or the third gate structure, the protective layer is removed.

According to an aspect of the invention, a semiconductor structure is provided, including a first region, a second region, a substrate, a first gate structure and a second gate structure. The second area is adjacent to the first area. The first gate structure is disposed on the substrate in the first region. The first gate structure includes at least one gate electrode film. The second gate structure is disposed on the substrate in the second region. The second gate structure includes a plurality of gate electrode films. The at least one gate electrode film of the first gate structure and the gate electrode film of the second gate structure have different number of layers.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

102‧‧‧First area

104‧‧‧Second area

106, 116, 118, 120‧‧‧ dielectric layer

108‧‧‧Dielectric stripes

110‧‧‧ Conductive stripes

112‧‧‧Stack structure

114, 114A, 114B‧‧‧ semiconductor layer

122, 124‧‧‧ sacrificial layer

126‧‧‧mask layer

128‧‧‧film layer

130, 132‧‧‧ anti-reflection layer

134‧‧‧ photoresist layer

136‧‧‧resist pattern

138‧‧‧film pattern

140‧‧‧Material film

142‧‧‧Material spacers

144‧‧‧pattern structure

146‧‧‧ mask pattern

148‧‧‧sacrificial pattern

150‧‧‧Material layer

152‧‧‧pattern layer

154‧‧‧ Conductive layer

156‧‧‧Gate electrode film

158‧‧‧Protective layer

160‧‧‧resist pattern

162, 166, 170, 172‧‧ dielectric layers

164, 168‧‧‧ mask pattern

174, 190‧‧‧ electrode layer

176, 178‧‧‧ mask layer

180, 182, 192‧‧ ‧ mask pattern

184‧‧‧ gap

186‧‧‧Insulation materials

188‧‧‧Isolation structure

194‧‧‧Protective layer

196A, 196B‧‧‧ gate dielectric film

198A, 198B‧‧‧ gate electrode film

200A, 200B, 202‧‧ ‧ spacer

204A, 204B‧‧‧ gate electrode film

206A, 206B‧‧‧ gate electrode film

FIGS. 1 through 34 illustrate a method of fabricating a semiconductor structure in accordance with an embodiment.

FIGS. 1 through 34 illustrate a method of fabricating a semiconductor structure in accordance with an embodiment.

Referring to FIG. 1, in an embodiment, for example, the first region 102 is a three-dimensional memory array region. The second region 104 adjacent to the first region 102 is a peripheral region for a complementary MOS field effect transistor.

Referring to FIG. 1 , in the first region 102 , the substrate may include a dielectric layer 106 . In one embodiment, the dielectric layer 106 includes an oxide. In other embodiments, other suitable material layers, such as semiconductor layers, may be used in place of dielectric layer 106. The semiconductor layer may include germanium or the like. The dielectric strips 108 and the conductive strips 110 are alternately stacked on the dielectric layer 106 to form a stacked structure 112. In one embodiment, the dielectric strips 108 comprise an oxide. In an embodiment, the conductive strips 110 comprise polysilicon.

Referring to FIG. 1 , in the second region 104 , the substrate may include a semiconductor layer 114 . In one embodiment, the semiconductor layer 114 includes germanium. A dielectric layer 116 is formed over the semiconductor layer 114. In one embodiment, the dielectric layer 116 includes an oxide.

Referring to FIG. 1, a dielectric layer 118 is formed on the dielectric layer 116 on the stacked structure 112, the dielectric layer 106, and the semiconductor layer 114. In an embodiment, Dielectric layer 118 includes a dielectric anti-reflective coating (DARC). For example, the dielectric layer 118 can include hafnium oxide, tantalum nitride, hafnium oxynitride, or the like. The dielectric layer 120 is disposed between the sidewall of the stacked structure 112 and the sidewall of the semiconductor layer 114. In one embodiment, the dielectric layer 120 includes an oxide. The sacrificial layer 122 is disposed on the dielectric layer 118 and the dielectric layer 120. In an embodiment, the sacrificial layer 122 includes a carbon film such as carbon-containing cerium oxide (SiOC). The sacrificial layer 124 is disposed on the sacrificial layer 122. In one embodiment, the sacrificial layer 124 includes a cap oxide and may have a thickness of 300 nm. A mask layer 126 is formed on the sacrificial layer 124. In one embodiment, the mask layer 126 comprises polysilicon and may have a thickness of 400 nm. A film layer 128 is formed on the mask layer 126. In one embodiment, the film layer 128 comprises an advanced pattern film (APF) (trade name) obtained from U.S. application materials and has a thickness of 800 nm. The anti-reflection layer 130 is provided on the film layer 128. In one embodiment, the anti-reflective layer 130 comprises a dielectric anti-reflective coating (DARC). For example, the anti-reflective layer 130 may include hafnium oxide, tantalum nitride, hafnium oxynitride or the like. In one embodiment, the anti-reflective layer 130 has a thickness of 180 nm. The anti-reflection layer 132 is provided on the anti-reflection layer 130. In one embodiment, the anti-reflective layer 132 includes a bottom anti-reflective coating (BARC). For example, the anti-reflective layer 132 can include an organic material. In one embodiment, the anti-reflective layer 132 has a thickness of 300 nm. The photoresist layer 134 is disposed on the anti-reflection layer 132. In one embodiment, the photoresist layer 134 has a thickness of 1000 nm.

Referring to FIG. 2, the photoresist layer 134 is patterned to form a photoresist pattern 136 on the anti-reflection layer 132.

Referring to FIG. 3, the photoresist pattern 136 is used as an etch mask, and an etching step is performed to remove a portion of the thin film layer 128 to form a thin film pattern 138 on the mask layer 126. The thin film pattern 138 may include an etched thin film layer 128 and an anti-reflective layer 130 remaining thereover. The thin film pattern 138 has an opening to expose the mask layer 126.

Referring to FIG. 4, a material film 140 is formed on the mask pattern 126 on the film pattern 138 and the opening of the film pattern 138. In one embodiment, the material film 140 includes an oxide.

Referring to FIG. 5, an anisotropic etch can be performed to remove portions of the material film 140, leaving a portion of the material film 140 on the sidewalls of the film pattern 138 to form a material spacer 142. This etching step also removes the anti-reflective layer 130 of the thin film pattern 138. In one embodiment, the etching step is substantially stopped at the mask layer 126.

Referring to FIG. 6, the film pattern 138 is removed.

Referring to FIG. 7, a pattern structure 144 is formed on the mask layer 126 in the first region 102. In an embodiment, the pattern structure 144 includes a photoresist pattern.

Referring to FIG. 8, the material spacer 142 and the pattern structure 144 are used as an etch mask, and an etching step is performed to remove a portion of the mask layer 126 to form a mask pattern 146 having an opening on the sacrificial layer 124. Material gap 142 and pattern structure 144 are then removed.

Referring to FIG. 9, the mask pattern 146 is used as an etch mask, and an etching step is performed to remove the sacrificial layer 124 and a portion of the sacrificial layer 122 to form a sacrificial pattern 148 having an opening. In one embodiment, after the etching step, the sacrificial pattern 148 will leave the sacrificial layer 124 on the etched sacrificial layer 122 (not shown).

Referring to FIG. 10, the opening of the sacrificial pattern 148 is filled with a material layer 150. In one embodiment, material layer 150 includes an oxide.

Referring to FIG. 11, the upper portion of the material layer 150 is removed to form the pattern layer 152. The pattern layer 152 is a exposed sacrificial pattern 148. The method of removing the material layer 150 may include a chemical mechanical polishing method, an etch back method, or other suitable method. In an embodiment, the etching step can be stopped on the sacrificial pattern 148.

Referring to FIG. 12, the sacrificial pattern 148 is removed, and thus, the remaining pattern layer 152 has an opening.

Referring to FIG. 13, the opening of the pattern layer 152 is filled with a conductive layer 154. In an embodiment, the conductive layer 154 includes polysilicon.

Referring to FIG. 14, the upper portion of the conductive layer 154 is removed, wherein the portion of the conductive layer 154 remaining in the opening of the pattern layer 152 is the gate electrode film 156 forming the gate structure. The gate electrode films 156 of the gate structure are separated from each other. In an embodiment, the guide The electrical layer 154 is a single material film, so that the gate electrode film 156 of a single material film can be obtained. The disclosure is not limited thereto. In other embodiments, the conductive layer 154 is a multilayer material film, so that the gate electrode film 156 of the multilayer material film can be obtained, wherein when the multilayer material film is formed by using different condition parameters, the material film is There may be a grain boundary between them. In an embodiment, the conductive layer 154 can be removed by etch back. In another embodiment, the conductive layer 154 can be removed by chemical mechanical polishing.

In an embodiment, the gate structure (gate electrode film 156) on the stacked structure 112 is formed by a damascene process, that is, a size feature fine pattern layer 152 is formed first, and the conductive layer 154 is filled in. The gate electrode film 156 (gate structure) is formed by the opening of the pattern layer 152.

Referring to FIG. 15, a protective layer 158 is formed on the gate electrode film 156 and the pattern layer 152, so that the elements on the first region 102 are not affected by the process of the second region 104, so that the gate electrode film 156 (gate structure) ) Maintain structural features. In an embodiment, the protective layer 158 includes an oxide.

Referring to FIG. 16, a photoresist pattern 160 is formed on the protective layer 158. The photoresist pattern 160 is used as an etch mask, and an etching step is performed to remove the portion of the protective layer 158 located in the second region 104 and the dielectric layer 116, the dielectric layer 118 and the pattern layer 152 on the semiconductor layer 114 to The semiconductor layer 114 is exposed. In one embodiment, the etching step is substantially stopped on the semiconductor layer 114.

Referring to FIG. 17, a dielectric layer 162 is formed over the semiconductor layer 114. In one embodiment, the dielectric layer 162 includes an oxide (SAC OX).

Referring to FIG. 18, a mask pattern 164 is formed over the semiconductor layer 114, the dielectric layer 120, the dielectric layer 162, and the protective layer 158. In an embodiment, the mask pattern 164 includes a photoresist material. The opening exposed semiconductor layer 114 of the mask pattern 164 is doped to form the semiconductor layer 114A. The mask pattern 164 is then removed. In other embodiments, another mask pattern (not shown) may be formed to expose other regions of the semiconductor layer 114, and the exposed semiconductor layer 114 is doped to form the semiconductor layer 114B. The semiconductor layer 114A and the semiconductor layer 114B may have different doping strips Pieces. In one embodiment, for example, the semiconductor layer 114A and the semiconductor layer 114B have an N conductivity type and a P conductivity type, respectively.

Referring to FIG. 19, a dielectric layer 166 is formed over the dielectric layer 162, the dielectric layer 120, and the protective layer 158. In an embodiment, the dielectric layer 166 may comprise tantalum nitride, hafnium oxynitride or a similar material (PAD SIN). Dielectric layer 166 can be formed in a deposition manner or other suitable manner.

Referring to FIG. 20, a mask pattern 168 is formed on the dielectric layer 166. In an embodiment, the mask pattern 168 includes a photoresist material. The mask pattern 168 is used as an etch mask, and an etching step is performed to remove portions of the dielectric layer 162 and the dielectric layer 166. The mask pattern 168 is then removed.

Referring to FIG. 21, a dielectric layer 170 is formed on the semiconductor layer 114A. In one embodiment, dielectric layer 170 includes an oxide.

Referring to FIG. 22, after the dielectric layer 162 and the dielectric layer 166 are removed, the dielectric layer 172 is formed on the semiconductor layer 114B. In one embodiment, dielectric layer 172 includes an oxide.

Referring to FIG. 23, an electrode layer 174 is formed over the dielectric layer 120, the dielectric layer 170, the dielectric layer 172, and the protective layer 158. In one embodiment, electrode layer 174 includes polysilicon.

Referring to FIG. 24, a mask layer 176 is formed on the electrode layer 174. In an embodiment, the mask layer 176 includes an oxide. A mask layer 178 is formed over the mask layer 176. In one embodiment, the mask layer 178 comprises tantalum nitride, hafnium oxynitride or a similar material.

Referring to FIG. 25, a mask pattern 180 is formed on the mask layer 178. In an embodiment, the mask pattern 180 includes a photoresist material.

Referring to FIG. 26, the mask pattern 180 is used as an etch mask, and an etching step is performed to remove the mask layer 178 exposed by the opening of the mask pattern 180 to form the mask pattern 182. Then, the mask pattern 180 is removed. The mask pattern 182 is used as an etch mask, and an etching step is performed to remove the electrode layer 174, the dielectric layer 170, the dielectric layer 172, the semiconductor layer 114A, and the semiconductor layer under the opening of the mask pattern 182. 114B, wherein the etched electrode layer 174, the dielectric layer 170, the dielectric layer 172, and the semiconductor layer 114A and the semiconductor layer 114B are separated from each other by a gap 184.

Referring to Figure 27, the void 184 is filled with an insulating material 186. In one embodiment, the insulating material 186 includes an oxide.

Referring to Figure 28, a portion of the insulating material 186 is removed, leaving a portion of the void 184 to form the isolation structure 188. The isolation structure 188 is a shallow trench isolation (STI). In an embodiment, the isolation structure 188 (STI) is formed in a self-aligned manner. During the self-aligned STI process of the second region 104, the gate structure (gate electrode film 156) formed by the Damascus process on the first region 102 is protected by the protective layer 158, so the STI process does not affect the gate. The nature of the structure (gate electrode film 156). Therefore, the method according to the embodiment is capable of integrating the Damascene process with the STI process, and enables components having different characteristics to have good characteristics, and a device capable of obtaining good electrical and performance, and improving the product. Yield and performance. Then, the mask pattern 182 is removed.

Referring to FIG. 29, an electrode layer 190 is formed on the electrode layer 174 and the isolation structure 188. In one embodiment, electrode layer 190 includes polysilicon.

Referring to FIG. 30, a mask pattern 192 is formed to cover the electrode layer 190 in the second region 104. In an embodiment, the mask pattern 192 includes a photoresist material. The portion of the electrode layer 190 that is not covered by the mask pattern 192 is subjected to an etching step, leaving the electrode layer 174 and the electrode layer 190 on the sidewalls of the pattern layer 152 and the protective layer 158. This etching step can substantially stop the exposed dielectric layer 120 and the protective layer 158.

Referring to Figure 31, the mask pattern 192 is removed. The protective layer 158 over the gate electrode film 156, the upper portion of the electrode layer 174, and the upper portion of the electrode layer 190 are removed. This removal step can be carried out by chemical mechanical grinding so that the elements after the removal step have a substantially flush upper surface.

Referring to FIG. 32, the protective layer 194 is formed on the dielectric layer 120, the pattern layer 152, the gate electrode film 156, the electrode layer 174 and the electrode layer 190 on the first region 102, so that the components of the first region 102 can be made. Without the influence of the second region 104 process, the gate electrode film 156 (gate structure), the electrode layer 174 and the electrode layer 190 are Hold structural features. In an embodiment, the protective layer 194 comprises a photoresist material.

Referring to FIG. 33, the electrode layer 190, the electrode layer 174, the dielectric layer 170, and the portion of the dielectric layer 172 that is not shielded by the protective layer 194 are removed to form the gate dielectric film 196A of the gate structure on the first region 102. And the gate electrode film 198A, and the gate dielectric film 196B and the gate electrode film 198B of the gate structure on the second region 104. The gate electrode film 198A includes a gate electrode film 204A and a gate electrode film 206A. The gate electrode film 198B includes a gate electrode film 204B and a gate electrode film 206B. In one embodiment, the process conditions for forming the gate electrode film 204A and the gate electrode film 204B (FIG. 23 to FIG. 32) are different from those for forming the gate electrode film 206A and the gate electrode film 206B. The electrode layer 190 (Figs. 29 to 32) has a grain boundary between the gate electrode film 204A and the gate electrode film 206A, and has a grain boundary between the gate electrode film 204B and the gate electrode film 206B. In the embodiment, since the process of the gate electrode film 156 on the first region 102 is performed separately from the process of the gate electrode film 198A and the gate electrode film 198B on the second region 104, the gate electrode film 156 and the gate electrode film 198A are formed. The gate electrode film 198B may have different structural features, such as having different film layers, or other conditions. Therefore, according to the manufacturing method of the embodiment, it is possible to elastically form a rich circuit design in accordance with actual needs. The protective layer 194 is then removed.

Referring to Fig. 34, a spacer 200A is formed on the sidewalls of the gate dielectric film 196A and the gate electrode film 198B. A spacer 200B is formed on the sidewalls of the gate dielectric film 196B and the gate electrode film 198B. A spacer 202 is formed on the sidewall of the electrode layer 190.

In one embodiment, the gate structure (gate electrode film 156) disposed on the stacked structure 112 is a word line used as a three-dimensional stacked memory. The upper surface of the isolation structure 188 is higher than the upper surfaces of the semiconductor layer 114A and the semiconductor layer 114B. The gate dielectric film 196A has a thickness greater than the gate dielectric film 196B. For example, gate dielectric film 196A is a high voltage oxide layer (HV GOX). The gate dielectric film 196B is a low pressure oxide layer (LV GOX).

In an embodiment, the three-dimensional stacked memory cell comprises a floating gate memory, a charge trapping memory, or other non-volatile memory. The concept of an embodiment is not limited to high density memory The unit's device can also be applied to other semiconductor circuit devices that require integration of damascene processes and self-aligned STI processes, or other different types of processes.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

102‧‧‧First area

104‧‧‧Second area

112‧‧‧Stack structure

114A, 114B‧‧‧ semiconductor layer

156‧‧‧Gate electrode film

174, 190‧‧‧ electrode layer

188‧‧‧Isolation structure

196A, 196B‧‧‧ gate dielectric film

198A, 198B‧‧‧ gate electrode film

200A, 200B, 202‧‧ ‧ spacer

Claims (10)

A method of fabricating a semiconductor structure, comprising: forming a first gate structure on a substrate in a first region, wherein the substrate comprises an adjacent first semiconductor layer and a second semiconductor layer; forming a protective layer covering the a first gate structure; forming an isolation structure between a sidewall of the first semiconductor layer and a sidewall of the second semiconductor layer; forming a second gate structure exposed to the protective layer adjacent to the first region On the first semiconductor layer in the second region; forming a third gate structure on the second semiconductor layer exposed by the protective layer; after forming the second gate structure or the third gate structure, removing the protection Floor. The method for fabricating a semiconductor structure according to claim 1, wherein the first semiconductor layer, the second semiconductor layer, and the isolation structure are formed by: forming a first mask pattern on a third semiconductor layer Using the first mask pattern as an etch mask, performing an etching step to remove a portion of the third semiconductor layer to form the first semiconductor layer and the second semiconductor layer separated from each other by a gap; And filling the gap with an insulating material to form the isolation structure. The second gate structure and the third gate structure are formed by: forming a dielectric layer on the first semiconductor layer and the second semiconductor layer; forming a An electrode layer is on the dielectric layer; a second mask pattern is formed on the electrode layer; and the second mask pattern is used as an etch mask, and an etching step is performed to remove a portion of the dielectric layer and The electrode layer is formed to form a plurality of gate dielectric films and a plurality of gate electrode films separated from each other, wherein the gate dielectric films and the gate electrode films are disposed on the first semiconductor layer and the second semiconductor layer Is formed separately a second gate structure and the third gate structure. The method of fabricating a semiconductor structure according to claim 2, wherein the first gate structure is a plurality of the first gate structures separated from each other, and the first gate junctions The forming method comprises: forming a sacrificial layer on the substrate; forming a mask layer on the sacrificial layer; forming a thin film layer on the mask layer; forming a photoresist pattern on the thin film layer; The photoresist pattern is used as an etch mask, and an etching step is performed to remove a portion of the thin film layer to form a thin film pattern having a plurality of openings to expose the mask layer; forming a material film on the thin film pattern And a portion of the film pattern exposed to the opening; removing a portion of the film of material leaving a portion of the film on the sidewall of the film pattern to form a plurality of material spacers; a film pattern; using the material spacers as an etch mask, performing an etching step to remove a portion of the mask layer to form a third mask pattern having a plurality of openings; The third mask pattern is used as an etch mask, an etching step is performed to remove a portion of the sacrificial layer to form a sacrificial pattern having a plurality of openings; and the sacrificial pattern is filled with a material layer Openings to form a patterned layer, the patterned layer having a plurality of openings; and a conductive layer filled in the patterned layer, the openings to form the plurality of first gate structure. A semiconductor structure comprising: a first region; a second region adjacent to the first region; a substrate; a first gate structure disposed on the substrate in the first region, wherein the first gate structure Including at least one gate electrode film, and the first gate structure is a plurality of the first gate structures separated from each other; a second gate structure disposed on the substrate in the second region, wherein the second gate structure comprises a plurality of gate electrode films, the at least one gate electrode film of the first gate structure and the second gate structure The gate electrode films have different number of layers. The semiconductor structure of claim 4, wherein the gate electrode film of the second gate structure has a grain boundary therebetween. The semiconductor structure of claim 4, wherein the first region is a three-dimensional memory array region, and the second region is a peripheral region for a complementary metal oxide half field effect transistor. The semiconductor structure of claim 4, further comprising: a first semiconductor layer, wherein the second gate structure is disposed on the first semiconductor layer; a second semiconductor layer; and a third gate structure On the second semiconductor layer, the second gate structure and the third gate structure each include a gate dielectric film and a gate electrode film disposed on the gate dielectric film, the second gate structure and the second gate structure The gate dielectric films or the gate electrode films of the three-gate structure have different thicknesses; and an isolation structure is disposed between a sidewall of the first semiconductor layer and a sidewall of the second semiconductor layer. The semiconductor structure of claim 7, wherein the isolation structure is shallow trench isolation, an upper surface of the isolation structure being higher than an upper surface of the first semiconductor layer and the second semiconductor layer. The semiconductor structure of claim 4, further comprising: a stacked structure, wherein the stacked structure is formed by alternately stacking a plurality of dielectric stripes and a plurality of conductive stripes, wherein the first gate structure is disposed on the a semiconductor structure, wherein the second gate structure is disposed on the semiconductor layer; and a dielectric layer is disposed between a sidewall of the stacked structure and a sidewall of the semiconductor layer. The semiconductor structure of claim 4, wherein the first gate structure is a word line used as a three-dimensional stacked memory.