CN108831890B - Preparation method of three-dimensional memory - Google Patents
Preparation method of three-dimensional memory Download PDFInfo
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- CN108831890B CN108831890B CN201810645748.5A CN201810645748A CN108831890B CN 108831890 B CN108831890 B CN 108831890B CN 201810645748 A CN201810645748 A CN 201810645748A CN 108831890 B CN108831890 B CN 108831890B
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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Abstract
The invention provides a preparation method of a three-dimensional memory, which comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a grid stacking layer and a channel hole penetrating through the stacking layer, a core layer and a memory layer surrounding the core layer are filled in the channel hole, and at least the outer layer of the core layer is a channel layer; removing the top end of the core layer to form a first groove; forming a barrier layer at the bottom of the first groove; removing the part of the memory layer protruding from the barrier layer by using the barrier layer to widen the first groove and form a second groove; a drain is formed in the second recess. According to the preparation method of the three-dimensional memory, the drain electrode is manufactured by the second groove formed by widening the first groove, so that the size of the drain electrode in the horizontal direction is larger, the risk that a tungsten electrode formed in a tungsten filling process cannot be connected with the drain electrode can be reduced, and the production yield of the three-dimensional memory is improved.
Description
Technical Field
The invention mainly relates to the technical field of semiconductors, in particular to a preparation method of a three-dimensional memory.
Background
With the continued emphasis on highly integrated electronic devices, there is a continuing need for semiconductor memory devices that operate at higher speeds and lower powers and have increased device densities. To achieve this, devices with smaller dimensions and multi-layer devices with transistor cells arranged in horizontal and vertical arrays have been developed. Three-dimensional is an emerging flash memory type developed in the industry, the limitation caused by a 2D or planar NAND flash memory is solved by vertically stacking multiple layers of data charge capture, the flash memory has excellent precision, higher storage capacity is supported to be accommodated in a smaller space, storage equipment with the storage capacity being several times higher than that of the similar NAND technology can be manufactured, the cost and the energy consumption are further effectively reduced, and the requirements of numerous consumer mobile devices and the enterprise deployment with the severest requirements can be comprehensively met.
The drain is an electrode for connecting a circuit in the channel hole with an external circuit. Due to the restriction of factors such as the radius of a channel hole and the thickness of a storage layer, the size of a drain electrode in the horizontal direction is small in the current NAND memory. The drain electrode having a small horizontal dimension poses a risk that the tungsten electrode formed in the tungsten filling process cannot be connected to the drain electrode. Failure to connect the tungsten electrode to the drain connection would then render the device unusable. Therefore, a relatively expensive lithography machine (such as an Immersion lithography machine) with higher precision is often required to manufacture the tungsten electrode.
Therefore, it is necessary to provide a method for fabricating a three-dimensional memory device having a drain electrode with a large size in a horizontal direction and a method for fabricating a drain electrode on a recess structure.
Disclosure of Invention
The technical problem to be solved by the invention comprises a preparation method of a three-dimensional memory with a drain electrode with a larger size in the horizontal direction.
In order to solve at least a part of the technical problems, the invention provides a preparation method of a three-dimensional memory, which comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a stacking layer and a channel hole penetrating through the stacking layer, the stacking layer comprises a plurality of mutually-spaced grid layers, a core layer and a memory layer surrounding the core layer are filled in the channel hole, and at least the outer layer of the core layer is a channel layer;
removing the top end of the core layer to form a first groove;
forming a barrier layer at the bottom of the first groove;
removing the part of the memory layer protruding from the barrier layer by using the barrier layer to widen the first groove and form a second groove;
a drain is formed in the second recess.
According to at least one embodiment of the present invention, forming the barrier layer at the bottom of the first recess comprises:
covering a barrier material layer on the semiconductor structure, wherein the barrier material layer fills the first groove;
removing a part of the barrier material layer, and leaving a predetermined thickness of the barrier material at the bottom of the first groove to serve as the barrier layer.
According to at least one embodiment of the present invention, the method of covering the semiconductor structure with the barrier material layer includes spin coating.
According to at least one embodiment of the present invention, the method of removing a portion of the barrier material layer includes etching.
According to at least one embodiment of the invention, the material of the barrier layer is carbon.
According to at least one embodiment of the present invention, the predetermined thickness is in a range of 5nm to 50 nm;
according to at least one embodiment of the present invention, the method for removing the barrier layer includes performing an ashing process and a cleaning process.
According to at least one embodiment of the invention, the forming the second groove comprises the steps of:
and removing at least one part of the memory layer protruding from the barrier layer by selective dry etching.
According to at least one embodiment of the present invention, the bias voltage for the selective dry etching is in the range of 100 volts to 5000 volts.
According to at least one embodiment of the present invention, the memory layer includes a tunneling layer, a charge trapping layer, and a blocking layer.
According to at least one embodiment of the present invention, the stack layer further includes a hard mask layer on a surface thereof;
the step of removing the portion of the memory layer protruding from the barrier layer to widen the recess includes:
removing the tunneling layer and the blocking layer by using the blocking layer;
after removing the blocking layer, the hard mask layer and the portion of the charge trapping layer protruding from the core layer are removed simultaneously.
According to at least one embodiment of the present invention, the tunneling layer and the blocking layer are removed by selective dry etching;
and removing the hard mask layer and the part of the charge trapping layer protruding out of the core layer by selective wet etching.
According to at least one embodiment of the present invention, at least a portion of the hard mask layer and the charge trapping layer is made of silicon nitride, and the blocking oxide layer, the tunneling oxide layer and the insulating core film material layer are made of silicon oxide.
According to at least one embodiment of the present invention, the method for manufacturing a three-dimensional memory further includes the steps of:
forming a cover layer covering the semiconductor structure and the drain electrode, wherein a through hole aligned with the drain electrode is formed in the cover layer;
and filling metal into the through hole to form a conductive contact hole.
According to at least one embodiment of the present invention, the drain material comprises polysilicon.
According to the three-dimensional memory and the preparation method thereof, the drain electrode is manufactured by the second groove formed by widening the first groove, so that the size of the drain electrode in the horizontal direction is larger, the risk that a tungsten electrode formed in a tungsten filling process cannot be connected with the drain electrode can be reduced, and the production yield of the three-dimensional memory is improved.
Drawings
FIG. 1 is a flow chart of a method of fabricating a three-dimensional memory according to one embodiment of the invention;
FIG. 2 is a flow chart of a method of fabricating a three-dimensional memory according to another embodiment of the invention;
fig. 3A-3K are schematic diagrams of the steps of a process for fabricating a three-dimensional memory according to an embodiment of the invention.
Description of the symbols
1-substrate:
2-channel holes;
3-a first insulating layer;
a 4-gate layer;
5-stacking layers;
6-hard mask layer;
7-a first hard mask layer material layer;
8-a second hard mask layer material layer;
9-a silicon layer;
10-a reservoir material layer;
110-a reservoir layer;
12-a channel material layer;
120-a channel layer;
13-a layer of insulating core film material;
130-insulating core film;
14-a first groove;
140-a second groove;
16-a layer of drain material;
160-a drain electrode;
17-a cap layer;
171-a through hole;
18-conductive contact holes;
19-a barrier layer;
190-barrier material layer.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.
A method for manufacturing a three-dimensional memory according to an embodiment of the present invention will be described with reference to fig. 1 and fig. 3A, 3C, 3D, 3F, 3H, and 3J. In this embodiment, the method for manufacturing the three-dimensional memory mainly includes the following steps:
referring to fig. 3A, in step 100, a semiconductor structure is provided. The semiconductor structure comprises a substrate 1 and a stack of layers 5 on said substrate. The stacked layer 5 comprises several layers of gate layers 4 arranged in a mutually spaced manner in a direction perpendicular to the substrate 1, i.e. in a vertical direction in fig. 3A. In the present exemplary embodiment, substrate 1 is made of monocrystalline silicon. In other embodiments, substrate 1 is made of other suitable materials including, but not limited to, polysilicon, silicon germanium, silicon-on-insulator (SOI). In some embodiments, a doped region (not shown) is also formed on the substrate 1. It should be noted that the term "gate" should be understood in a broad sense, i.e., the gate may be a gate that is eventually retained in the product, or a "dummy gate" that is replaced by another material in a subsequent step. With continued reference to fig. 3A, the semiconductor structure also has a channel hole 2 through the stack of layers 5.
Referring to fig. 3C, a core layer located within the channel hole 2 and a memory layer surrounding the core layer are formed, and the memory layer is referred to as a memory material layer 10 herein for convenience of distinction since the memory layer is partially removed in a subsequent step. The core layer includes at least a channel layer in some embodiments, the core layer includes an insulating core film layer in addition to the channel layer. The channel layer is an outer layer of the core layer. Similarly, the channel layer is referred to as a channel material layer 12 at this time, since the top end of the core layer is also removed in the subsequent step. Accordingly, the insulating core film layer is referred to as an insulating core film material layer 13.
Referring to fig. 3D, in step 200, the top end of the core layer is removed to form the first groove 14. This step may be generally performed by etching the core layer to a predetermined depth D1. The etching may be single or multiple.
Referring to fig. 3F, in step 300, a barrier layer 19 is formed overlying the top surface of the channel layer 120. In some embodiments, the barrier layer 19 may also cover other regions besides the top surface of the channel layer 120.
Referring to fig. 3H, in step 400, the barrier layer 19 is used to remove the portion of the storage material layer 10 protruding from the barrier layer 19, so as to form a second groove 140. Through this step, the layer of reservoir material 10 becomes the reservoir layer. Accordingly, the first recess 14 is widened in this step, and the recess formed after widening, which includes the region of the portion of the original reservoir material layer 10 protruding beyond the barrier layer 19, is referred to as the second recess 140.
Referring to fig. 3J, in step 500, the drain electrode 160 located within the channel hole 2 is formed. After this step is completed, the drain electrode 160 is formed on the channel layer 120, and the drain electrode 160 protrudes outward from the channel layer 120 in a radial direction of the channel hole 2 (i.e., in a horizontal direction in fig. 3H). Such a drain 160 with a large horizontal dimension can reduce the risk that the tungsten electrode formed in the tungsten filling process cannot be connected to the drain, thereby improving the yield of the three-dimensional memory.
Although the method for fabricating the three-dimensional memory in one embodiment of the present invention is described above, the method for fabricating the three-dimensional memory in other embodiments of the present invention may be variously changed in many aspects with respect to the above-described embodiments. For example, although the steps in the method for manufacturing a three-dimensional memory in the above embodiment are arranged in the above order, this does not mean that the steps can be performed only in the above order. At least some of these variations are described below in terms of several embodiments.
A method for manufacturing a three-dimensional memory according to another embodiment of the present invention will be described with reference to fig. 2 and 3A to 3K. In this embodiment, the method for manufacturing the three-dimensional memory mainly includes the following steps:
referring to fig. 3A, in step 100, a semiconductor structure is provided. The semiconductor structure comprises a substrate 1 and a stack of layers 5 on said substrate. The stacked layer 5 comprises several layers of gate layers 4 arranged in a mutually spaced manner in a direction perpendicular to the substrate 1, i.e. in a vertical direction in fig. 3A. In the present embodiment, the first insulating layer 3 is disposed between the gate layers 4. In other words, in the stack layer 5, the plurality of first insulating layers 3 and the plurality of gate layers 4 are disposed in a two-by-two spaced manner such that several layers of gate layers 4 are spaced from each other.
With continued reference to fig. 3A, in step 200, a trench hole 2 is formed through the stack of layers 5. The trench hole 2 may be formed by an etching method or the like.
Referring to fig. 3B, in step 301, a layer of reservoir material 10 is formed within the channel hole 2. The layer of reservoir material 10 covers at least the side walls of the channel holes 2. In the present embodiment, the reservoir material layer 10 also covers the bottom of the channel hole 2. The layer of reservoir material 10 may be fabricated in a subsequent step as a reservoir layer 110.
The structure of the layer of reservoir material 10 may vary. In some embodiments, the memory material layer 10 includes, but is not limited to, a blocking oxide layer, a charge trapping layer, and a tunneling oxide layer sequentially formed from inside to outside (since the thicknesses of the memory material layer 10 and the memory layer 110 are very small, the blocking oxide layer, the charge trapping layer, and the tunneling oxide layer are not labeled one by one to avoid the complicated figures).
In some embodiments, the tunnel oxide layer may be made of an insulating material including, but not limited to, silicon oxide, silicon nitride, or silicon oxynitride, or a combination thereof. In some embodiments, the tunnel oxide layer has a thickness of 5-15 nm. In some embodiments, the charge trapping layer may be used to store charge, and the storage or removal of charge in the charge trapping layer determines the switching state of the semiconductor channel. The material of the charge trapping layer includes, but is not limited to, silicon nitride, silicon oxynitride, silicon, or combinations thereof. In some embodiments, the charge trapping layer has a thickness of 3-15 nm. In some embodiments, the barrier layer material is silicon oxide, silicon nitride, a high-k insulating material, or a combination of more of the above. For example a silicon oxide layer or a composite layer comprising three layers of silicon oxide/silicon nitride/silicon oxide (ONO) with a thickness of 4-15 nm. In some embodiments, the barrier layer may further comprise a high-K dielectric layer (e.g., alumina having a thickness of 1-5 nm).
Referring to fig. 3C, in step 302, a channel material layer 12 located within the channel hole 2 is formed. Wherein at least a portion of the memory material layer 10 is located at the periphery of the channel material layer 12. The material of the channel material layer 12 may be selected from amorphous, polycrystalline, and single crystal silicon materials. The process of forming the channel material layer 12 may use a thin film deposition process. The thin film deposition process includes, but is not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD), or combinations thereof, or other suitable methods.
With continued reference to fig. 3C, in step 303, an insulating core film material layer 13 is formed. As the material of the insulating core film material layer 13, various materials suitable for the insulating core film, such as silicon oxide, can be selected. On the other hand, a specific method of forming the insulating core film material layer 13 may be Atomic Layer Deposition (ALD), Spin-on dielectric (SOD), or a combination of the above processes, or other suitable methods.
Referring to fig. 3D, in step 304, the top of the insulating core film material layer 13 is removed, forming an insulating core film layer 130.
With continued reference to fig. 3D, the top of the channel material layer 12 is removed in step 305, forming the channel layer 120. Optionally, in this step, the top of the layer of channel material 12 exposed in step 304 is removed. In other embodiments, removing the top of the channel material layer 12 may also include exposing a portion of the channel material layer 12 below the top of the channel material layer 12. Optionally, in this step, the top of the channel material layer 12 is removed by wet etching. It is noted that although this step 305 and step 304 are described as two steps independent of each other, this merely means that both the top of the insulating core film material layer 13 and the top of the channel material layer 12 need to be removed. In some embodiments, the top of the insulating core film material layer 13 and the top of the channel material layer 12 may be removed in the same step. After this step is completed, the top surfaces of the insulating core film layer 130 and the channel layer 120 and the sidewalls of the top of the channel hole 2 form a first recess 14.
Referring to fig. 3E, a barrier material layer 190 is formed overlying the top surface of the channel layer 120 in step 306. In some embodiments, the barrier material layer 190 is formed to not only fill the first recess 14, but also cover the upper surface of the semiconductor structure. The barrier material layer 190 may be selected from any material that is capable of protecting structures covered thereby in subsequent steps, such as at least one of the channel material layer 12 and the insulating core film material layer 13 covered thereby in some embodiments, and such that these structures are not removed in subsequent steps. In some embodiments, the material of the barrier material layer 190 includes carbon, and the material of the barrier layer 19 made of the barrier material layer 190 also includes carbon.
On the other hand, the specific manner of forming the barrier material layer 190 covering the top surface of the channel layer 120 may be various. Since the barrier material layer 190 is finally removed entirely, the barrier material layer 190 does not need to meet a high standard in terms of degree of densification, etc., so the barrier material layer 190 may be formed in various ways. In some embodiments, the barrier material layer 190 is formed by spin coating.
Referring to fig. 3F, in step 307, at least a portion of the barrier material layer 190 is removed, forming a barrier layer 19 at the bottom of the first recess 14. In some embodiments, all of the barrier material layer 190 outside the channel hole 2 and a portion inside the channel hole 2 are removed. After the removal step is completed, the remaining barrier material layer 190 with a predetermined thickness is the barrier layer 19. In other words, the barrier layer 19 is a barrier material having a certain thickness inside the channel hole 2 covering the top surfaces of the channel layer 120 and the insulating core film layer 130. This removal step may be performed by etching or the like.
In general, the thickness (i.e., the predetermined thickness) of the barrier layer 19 can be freely selected as desired. However, an excessively thick barrier layer 19 may result in insufficient depth of the reservoir material layer 10 being removed when the barrier layer 19 is used to remove the portion of the reservoir material layer 10 protruding from the barrier layer. An excessively thin barrier layer 19 may not provide adequate protection to the top of the core layer during removal of a portion of the reservoir material layer 10. The thickness of the barrier layer 19 can therefore be set generally in the range from 5nm to 50 nm.
With continued reference to fig. 3G, in step 308, all or a portion of the top of the layer of reservoir material 10 is removed using the barrier layer 19. In some embodiments, the structure of the reservoir material layer 10 may be varied. In some embodiments, the memory material layer 10 includes, but is not limited to, a blocking oxide layer, a charge trapping layer, and a tunneling oxide layer sequentially formed from inside to outside (since the thicknesses of the memory material layer 10 and the memory layer 110 are very small, the blocking oxide layer, the charge trapping layer, and the tunneling oxide layer are not labeled one by one to avoid the complicated figures).
In some embodiments, the tunnel oxide layer may be made of an insulating material including, but not limited to, silicon oxide, silicon nitride, or silicon oxynitride, or a combination thereof. In some embodiments, the tunnel oxide layer has a thickness of 5-15 nm. In some embodiments, the charge trapping layer may be used to store charge, and the storage or removal of charge in the charge trapping layer determines the switching state of the semiconductor channel. The material of the charge trapping layer includes, but is not limited to, silicon nitride, silicon oxynitride, silicon, or combinations thereof. In some embodiments, the charge trapping layer has a thickness of 3-15 nm. In some embodiments, the barrier layer material is silicon oxide, silicon nitride, a high-k insulating material, or a combination of more of the above. For example a silicon oxide layer or a composite layer comprising three layers of silicon oxide/silicon nitride/silicon oxide (ONO) with a thickness of 4-15 nm. In some embodiments, the barrier layer may further comprise a high-K dielectric layer (e.g., alumina having a thickness of 1-5 nm).
In this step, the barrier oxide layer and the tunnel oxide layer on top of the layer of memory material 10 are removed. In some embodiments, the reason that the barrier oxide layer and the tunnel oxide layer may be removed in this step is that the materials of the barrier oxide layer and the tunnel oxide layer are the same. In some embodiments, the material of the barrier oxide layer and the tunnel oxide layer is silicon oxide. And thus can be removed in the same step. The step of removing the barrier oxide layer and the tunnel oxide layer may be a selective dry etching step. Alternatively, the material of the insulating core film material layer 13 may also be silicon oxide.
At this time, since the top surfaces of the insulating core film layer 130 and the channel layer 120 are covered with the barrier layer 19, the heights of the insulating core film layer 130 and the channel layer 120 are not substantially changed and the inner structure and the top surface thereof are not significantly changed when the barrier oxide layer and the tunnel oxide layer are removed by the selective dry etching. In this step, in order to make the etching direction of the dry etching good, the dry process may be appropriately biased and controlled within a range of 100 volts to 5000 volts.
Referring to fig. 3H, in step 309, barrier layer 19 is removed. Any suitable step may be selected to remove the barrier layer, depending on the material of the barrier layer. For example, when the material of the barrier layer 19 is carbon, the barrier layer 19 may be removed by an ashing process (Ash) and a cleaning process (Wet).
With continued reference to fig. 3H, in step 310, the top of the channel material layer 12 is again removed. A reservoir layer 110 is formed. In some embodiments, what is removed in this step is the charge trapping layer on top of the layer of reservoir material 10. This step is completed to form the second recess 140. At least a portion of the second recess 140 is located above the top surface of the reservoir layer 110. This arrangement enables at least a portion of the drain electrode 160 formed in a subsequent step to be located above the reservoir layer 110. In some embodiments, a specific method of removing the top of the channel material layer 12 may be to perform a selective wet etch. After this step is completed, the second groove obtained is widened with respect to the first groove 14, thus having a greater dimension in the horizontal direction.
Referring to fig. 3A, in some embodiments, the stack layer 5 includes a hard mask layer 6 on a top layer of the stack layer 5 in addition to the gate layer 4 and the first insulating layer 3. The hard mask layer 6 may have a single-layer structure or a multi-layer structure. With continued reference to fig. 3A, in one embodiment, the hard mask layer 6 further includes a first hard mask layer material layer 7 and a second hard mask layer material layer 8 over the first hard mask layer material layer 7. Wherein the materials of the first hard mask layer material layer 7 and the second hard mask layer material layer 8 are different, and the materials of the first hard mask layer material layer 7 and the second hard mask layer material layer 8 include, but are not limited to, silicon oxide, silicon nitride or silicon oxynitride, or a combination of a plurality of the above materials.
Referring to fig. 3G and 3H, optionally, in step 310, at least a portion of the hard mask layer 6 is also removed while the top portion of the channel material layer 12 is removed again. For example, the second hard mask layer material layer 8 is also removed at the same time as the top of the channel material layer 12 is removed again. In some embodiments, the reason the charge trapping layer and at least a portion of the hard mask layer 6 may be removed in this step is because the charge trapping layer and at least a portion of the hard mask layer 6 are the same material. In some embodiments, the material of at least a portion of the hard mask layer 6 (e.g., the second hard mask layer material layer 8) and the charge trapping layer is silicon nitride.
In step 400, a drain 160 is formed. The step of forming the drain electrode 160 may be performed at one time or may be performed in a plurality of sub-steps. An alternative method of forming the drain 160 is illustrated in fig. 3G and 3H.
Referring to fig. 3I, in an alternative method of forming the drain 160, a layer of drain material 16 is first formed over the entire semiconductor structure used to fabricate the three-dimensional memory. The specific form of this forming step may vary. For example, the material of the drain material layer 16 may be polysilicon, monocrystalline silicon, or the like. A specific method for forming the drain material Layer 16 may be a Chemical Vapor Deposition (CVD), a Physical Vapor Deposition (PVD), an Atomic Layer Deposition (ALD), or the like. The top of the formed drain material layer 16 may not be smooth, for example, in the current embodiment, the top of the formed drain material layer 16 has a protrusion corresponding to the channel material layer 12.
Referring to fig. 3H, after forming the drain material layer 16, the drain material layer 16 is planarized, which may be performed by Chemical-Mechanical planarization (CMP), or other planarization methods. The planarization step removes the drain material layer 16 outside the second recess, thereby forming the drain 160.
In the method for manufacturing the three-dimensional memory according to the embodiment, the drain 160 of the three-dimensional memory protrudes outward from the channel layer 120 in the radial direction of the channel hole 2. The method of fabricating the three-dimensional memory of the present embodiment makes the size of the drain electrode 160 in the radial direction of the channel hole 2 (i.e., in the horizontal direction of fig. 3A to 3H) larger. The drain 160 with a larger horizontal dimension can reduce the risk that the tungsten electrode formed in the subsequent tungsten filling process cannot be connected with the drain 160, thereby improving the production yield of the three-dimensional memory.
Although the above embodiments show some variations of the method of fabricating the three-dimensional memory. In other embodiments, however, there are more variations on aspects of the method of fabricating the three-dimensional memory. For example, although the steps in the method for manufacturing a three-dimensional memory in the above embodiment are arranged in the above order, this does not mean that the steps can be performed only in the above order. The following description continues with at least some of the possible variations of the method for producing a three-dimensional memory in a number of further embodiments.
The size of the drain 160 in the direction perpendicular to the substrate is defined as the height of the drain 160. The height of the drain 160 may be selected within a certain range. Referring to fig. 3H, in some embodiments, the height of the drain 160 ranges from 50 nanometers to 500 nanometers.
Although a step after forming the drain electrode 160 is not described in the foregoing embodiment. In fact, there may be more steps after forming the drain 160 in some embodiments of the present invention. Some embodiments of the invention are described below with reference to fig. 3K. In these embodiments, in addition to all or part of the steps before forming the drain 160 in any of the previous embodiments, the following steps are also included:
in step 500, a cap layer 17 is formed overlying the semiconductor structure and the drain 160. A via 171 is formed in the cap layer 17 in alignment with the drain 160. The through hole 171 may have a funnel shape as shown in fig. 3I, or may have other shapes such as a column shape.
In step 600, the via hole 171 is filled with metal, so that the filled metal and the drain 160 form a conductive contact hole 18. The metal in which the via 171 is filled may be tungsten or other conductive metal.
Although the foregoing embodiments are related to the method for fabricating the three-dimensional memory, these embodiments are merely illustrative of the spirit of the present invention. The present invention is not in fact limited to the field of methods for the preparation of three-dimensional memories. For convenience of description and reduction of the number of figures, the following describes some embodiments of the present invention with reference to fig. 3C, 3F, and 3J, in which the drain is formed on a recessed structure. It is noted that the figures are used only for the sake of description and for the reduction of the number of figures, and do not necessarily represent all the references in these figures.
In these embodiments, the method for fabricating the drain electrode mainly includes the following steps:
referring first to fig. 3C, a semiconductor structure having a recessed structure 2 is provided. The semiconductor structure may be used for manufacturing a three-dimensional memory, or may be used for manufacturing another chip or a memory. The recessed structure 2 may be a trench hole, or may be another recessed structure such as a groove.
With continued reference to fig. 3C, a core layer is disposed in the recess structure 2, the core layer at least includes a channel layer material layer 12 (the channel layer material layer 12 is to be fabricated as a channel layer in a subsequent step, and is herein temporarily referred to as the channel layer 12 first), and a memory material layer 10 surrounding the core layer is disposed outside the core layer (the memory material layer 10 is to be fabricated as a memory layer in a subsequent step, and is herein temporarily referred to as the memory material layer 10 first).
Referring to fig. 3D, the top end of the core layer is removed to form a first groove 14. In this step, the top of the channel layer material layer 12 is removed, and the remaining channel layer material layer 12 will be used as the channel layer 120 in a subsequent step.
Referring to fig. 3F, a barrier layer 19 is formed at the bottom of the first groove.
Referring to fig. 3H, the barrier layer 19 is used to remove the portion of the memory material layer 10 protruding from the barrier layer 19 to widen the first recess 14, and a second recess 140 is formed.
Referring to fig. 3J, a drain electrode 160 is formed using the second recess 140.
Although one embodiment of the method of forming the drain is described above, in some other embodiments, the method of forming the drain includes more variations. At least some of these further variations are explained below with reference to the figures.
First, the specific method of forming the barrier layer 19 at the bottom of the first groove 14 may be various. Referring to fig. 3E and 3F, in some embodiments, a particular method of forming barrier layer 19 includes the steps of:
referring to fig. 3E, a barrier material layer 190 is overlying the semiconductor structure. The barrier material layer 190 fills the first recess 14. And the barrier material layer 190 may also cover regions other than the first groove 14. The barrier material layer 190 may be selected from any material that is capable of protecting structures covered thereby in subsequent steps, such as at least one of the channel material layer 12 and the insulating core film material layer 13 covered thereby in some embodiments, and such that these structures are not removed in subsequent steps. In some embodiments, the material of the barrier material layer 190 includes carbon, and the material of the barrier layer 19 made of the barrier material layer 190 also includes carbon.
On the other hand, the specific manner of forming the barrier material layer 190 covering the top surface of the channel layer 120 may be various. Since the barrier material layer 190 is finally removed entirely, the barrier material layer 190 does not need to meet a high standard in terms of degree of densification, etc., so the barrier material layer 190 may be formed in various ways. In some embodiments, the barrier material layer 190 is formed by spin coating.
Referring to fig. 3F, a portion of the barrier material layer 190 is removed so that a predetermined thickness of the barrier material can remain at the bottom of the first groove, and the barrier material can be used as the barrier layer 19. This removal step may be performed by etching or the like.
Secondly, "removing the portion of the memory material layer 10 protruding from the barrier layer 19 by using the barrier layer 19" should be understood in a broad sense, and this expression should not be understood as meaning that the portion of the memory material layer 10 protruding from the barrier layer 19 must be entirely removed by using the barrier layer 19. Referring to fig. 3G and 3H, in some embodiments, the step of removing the portion of the memory material layer 10 protruding from the barrier layer 19 by using the barrier layer 19 specifically includes the following steps:
referring to fig. 3G, a portion of the memory material layer 10 protruding from the barrier layer 19 is removed using the barrier layer 19.
Referring to fig. 3H, the barrier layer 19 is removed.
With continued reference to fig. 3H, another portion of the memory material layer 10 protruding beyond the barrier layer 19 is removed to form a memory layer 110. Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, changes and modifications to the above embodiments within the spirit of the invention are intended to fall within the scope of the claims of the present application.
Claims (13)
1. A preparation method of a three-dimensional memory is characterized by comprising the following steps:
providing a semiconductor structure, wherein the semiconductor structure comprises a stacking layer and a channel hole penetrating through the stacking layer, the stacking layer comprises a plurality of mutually spaced grid layers, a core layer and a memory layer surrounding the core layer are filled in the channel hole, the memory layer comprises a tunneling layer, a charge capturing layer and an oxidation blocking layer, and at least the outer layer of the core layer is a channel layer;
removing the top end of the core layer to form a first groove;
forming a barrier layer at the bottom of the first groove, wherein the barrier layer covers the core layer;
removing the part of the memory layer protruding out of the barrier layer by using the barrier layer to widen the first groove to form a second groove;
forming a drain electrode in the second groove;
forming a barrier layer at the bottom of the first recess comprises the steps of:
covering a barrier material layer on the semiconductor structure, wherein the barrier material layer fills the first groove;
and removing a part of the barrier material layer, and leaving a barrier material with a preset thickness at the bottom of the first groove to serve as the barrier layer.
2. The method of claim 1, wherein the step of covering the semiconductor structure with a layer of barrier material comprises spin coating.
3. The method of claim 1, wherein removing the portion of the barrier material layer comprises etching.
4. The method for manufacturing a three-dimensional memory according to claim 1, wherein: the material of the barrier layer is carbon.
5. The method for manufacturing a three-dimensional memory according to claim 1, wherein: the predetermined thickness is in a range of 5nm to 50 nm.
6. The method for manufacturing a three-dimensional memory according to claim 1, wherein: the method for removing the barrier layer comprises an ashing process and a cleaning process.
7. The method of fabricating a three-dimensional memory according to claim 1, wherein the forming of the second recess comprises the steps of:
and removing at least one part of the memory layer protruding out of the barrier layer by selective dry etching.
8. The method for manufacturing a three-dimensional memory according to claim 7, wherein: the bias voltage for the selective dry etch ranges from 100 volts to 5000 volts.
9. The method for manufacturing a three-dimensional memory according to claim 1, wherein:
the stacked layer also comprises a hard mask layer positioned on the surface;
the step of removing the part of the memory layer protruding from the barrier layer to widen the groove comprises the following steps:
removing the tunneling layer and the oxidation blocking layer by using the blocking layer;
and after removing the barrier layer, simultaneously removing the hard mask layer and the part of the charge trapping layer protruding out of the core layer.
10. The method for manufacturing a three-dimensional memory according to claim 9, wherein: removing the tunneling layer and the oxidation barrier layer by selective dry etching;
and removing the hard mask layer and the part of the charge trapping layer protruding out of the core layer by selective wet etching.
11. The method for manufacturing a three-dimensional memory according to claim 9, wherein: the core layer includes an insulating core film material layer located inside the channel layer;
at least part of the hard mask layer and the charge trapping layer are made of silicon nitride, and the blocking oxide layer, the tunneling oxide layer and the insulating core film material layer are made of silicon oxide.
12. The method of any one of claims 1 to 11, further comprising the steps of:
forming a cover layer covering the semiconductor structure and the drain electrode, wherein a through hole aligned with the drain electrode is formed in the cover layer;
and filling metal in the through hole to form a conductive contact hole.
13. The manufacturing method according to any one of claims 1 to 11, wherein a material of the drain electrode includes polysilicon.
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| CN104779154A (en) * | 2015-04-10 | 2015-07-15 | 武汉新芯集成电路制造有限公司 | Manufacturing method of 3D flash memory channel |
| CN107464817A (en) * | 2017-08-23 | 2017-12-12 | 长江存储科技有限责任公司 | A kind of preparation method of 3D nand flash memories |
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| US20120256253A1 (en) * | 2011-04-05 | 2012-10-11 | Sung-Min Hwang | Vertical Memory Devices |
| CN104779154A (en) * | 2015-04-10 | 2015-07-15 | 武汉新芯集成电路制造有限公司 | Manufacturing method of 3D flash memory channel |
| CN107464817A (en) * | 2017-08-23 | 2017-12-12 | 长江存储科技有限责任公司 | A kind of preparation method of 3D nand flash memories |
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