TWI548036B - Method of fabricating embedded memory device - Google Patents

Description

Method for manufacturing embedded memory element

The present invention relates to a method of fabricating an embedded memory device.

Embedded Memory Components In order to reduce the cost and simplify the process steps, it has become a trend to integrate the cell and peripheral components on the same wafer, for example, integrating flash memory and logic components on the same wafer. Such a component is called an embedded flash memory.

However, the conventional embedded memory device has a maximum distance between two adjacent drain regions and source regions, and cannot form a deep void because it cannot fill the dielectric layer, and is subsequently formed as a metal layer of a metal plug. It may be filled in these deep pores, thus causing the problem that the bit line and the word line are electrically shorted.

Embodiments of the present invention provide a method for fabricating an embedded memory device that avoids being at a maximum distance between two adjacent drain regions and source regions because deep dielectric layers are formed to form deep voids.

Embodiments of the present invention provide a method for manufacturing an embedded memory component, including A substrate is provided, the substrate including a cell region and a peripheral region. A plurality of first gate structures are formed on the cell regions of the substrate. A second gate structure is formed on the peripheral region of the substrate. A dielectric layer is formed on the substrate of the peripheral region. A plurality of dummy self-aligning contact window plugs are formed in the cell region and a plurality of openings are formed around the dummy self-aligning contact windows. A first stop layer is formed on the substrate, and the first stop layer is filled in the opening, wherein the plurality of recesses are formed on the surface of the first stop layer of the corresponding opening. A hard mask layer is formed in each of the depressions. Remove the hard mask layer and some of the first stop layer. The virtual self-aligning contact window plugs described above are removed to form a plurality of self-aligning contact window openings. A plurality of self-aligning contact windows are formed in the self-aligning contact window openings.

Embodiments of the present invention also provide a method of fabricating an embedded memory device, comprising providing a substrate, the substrate including a cell region, and the cell region including the first region and the second region. Forming a plurality of first gate structures on the substrate, a first gap between the first gate structures on the first region, and a second gap between the first gate structures on the second region, the first gap being less than The second gap. A plurality of virtual self-aligning contact window plugs are formed on the second zone of the first zone. A first stop layer is formed on the substrate, wherein a height of the first stop layer in the second gap is lower than a height of the first stop layer in the first gap. The first stop layer is anisotropically etched, the first first spacers are formed in the first gap, and the second spacers are separated from each other in the second gap. A second stop layer is formed on the first zone and the second zone to fill the first gap and the second gap.

The method of fabricating the embedded memory device of the embodiment of the present invention can avoid forming deep voids at a maximum distance between two adjacent drain regions and source regions.

In order to make the above features and advantages of the present invention more apparent, the following is a special The embodiments are described in detail below in conjunction with the drawings.

10‧‧‧First District

20‧‧‧Second District

100‧‧‧Base

100a‧‧‧cell area

100b‧‧‧ surrounding area

102, 110‧‧‧ gate structure

103‧‧‧ Tunneling Oxidation Layer

104, 106, 112‧‧‧ conductor layer

105‧‧‧Interruptor dielectric layer

107, 113‧‧‧ metal telluride layer

108, 114‧‧‧ under the cover layer

109‧‧‧Upper cover

111‧‧‧Well oxide layer

115‧‧‧ Cover layer

116, 120, 132, 133‧‧‧ stop layer

117‧‧‧ lining

118, 119, 132a, 132b‧‧‧ spacers

122‧‧‧ dielectric layer

124‧‧‧Conductor layer

125‧‧‧ Cover layer

126‧‧‧Top cover

127‧‧‧Virtual self-aligning contact window plug

128‧‧‧ openings

130‧‧‧ spacer

133‧‧‧stop layer

134‧‧‧ dent

136‧‧‧ Hard mask material layer

136a‧‧‧hard mask layer

140‧‧‧ openings

142‧‧‧ Self-aligning contact window openings

144‧‧‧Metal layer of barrier layer

146‧‧‧Conductor metal layer

148‧‧‧ Self-aligning contact window

150‧‧‧Bungee Area

160‧‧‧ source area

162, 164‧ ‧ gap

166‧‧‧ pores

a, c‧‧‧ distance

1A to 1I are cross-sectional views showing a manufacturing process of an embedded memory device according to a first embodiment of the present invention.

2 is a top plan view of a source region and a drain region of an embedded memory device according to an embodiment of the invention.

3A to 3C are cross-sectional views showing a part of a manufacturing process of an embedded memory device according to a second embodiment of the present invention.

4 is an image of a scanning electron microscope of a conventional embedded memory device.

Figure 5 is an image of a scanning electron microscope of an embedded memory device in accordance with a second embodiment of the present invention.

1A to 1I are cross-sectional views showing a manufacturing process of an embedded memory device according to a first embodiment of the present invention. 2 is a top plan view of a source region and a drain region of an embedded memory device according to an embodiment of the invention.

Referring to FIG. 1A, a substrate 100 is provided. Substrate 100 can be a semiconductor or a semiconductor compound such as germanium or germanium. The substrate 10 may also be a layer of germanium (SOI) on the insulating layer. The substrate 100 has a cell region 100a and a peripheral region 100b. Unit cell A plurality of gate structures 102 are formed on the substrate 100 of the region 100a, and at least one gate structure 110 is formed on the substrate 100 of the peripheral region 100b.

The gate structure 102 can be a gate structure of a non-volatile memory element, such as a gate structure of a flash memory element, such as a tunnel oxide layer 103, a conductor layer 104, and a gate inter-layer stacked on the substrate 100. Electrical layer 105 and conductor layer 106. The material that tunnels through the oxide layer 103 is, for example, cerium oxide. The conductor layer 104 acts as a floating gate, the material of which is, for example, doped polysilicon. The inter-gate dielectric layer 105 is, for example, a composite layer of hafnium oxide, tantalum nitride, and hafnium oxide (ONO). The conductor layer 106 serves as a control gate, the material of which is, for example, doped polysilicon. In addition, the gate structure 110 includes a gate dielectric layer 111 and a conductor layer 112 which are sequentially stacked on the substrate 100. The conductor layer 112 acts as a gate for the logic element, the material of which is, for example, doped polysilicon.

The method of forming the gate structure 102 and the gate structure 110 includes the following steps. First, different stacked material layers (not shown) are formed on the substrate 100 of the cell region 100a and the peripheral region 100b, respectively. Specifically, the tunneling oxide material layer, the first conductor material layer, the inter-gate dielectric material layer and the second conductor material layer are sequentially stacked on the cell region 100a of the substrate 100 on the peripheral region 100b of the substrate 100. The gate oxide material layer and the second conductor material layer are sequentially stacked, wherein the cell layer region 100a and the second conductor material layer on the peripheral region 100b are simultaneously formed. Then, the second conductor material layer on the cell region 100a is subjected to an ion implantation process. Thereafter, at least one patterning step is performed on the material layer to form a gate structure 102 on the substrate 100 of the cell region 100a and a gate structure 110 on the substrate 100 of the peripheral region 100b.

In an embodiment, the gate structure 102 may further comprise a stack of leads in sequence. The metal telluride layer 107, the lower mask layer 108 and the upper mask layer 109 on the bulk layer 106. The gate structure 110 may further include a metal germanide layer 113, a lower mask layer 114, and an upper mask layer 115 which are sequentially stacked on the conductor layer 112. The metal telluride layer 107 and the metal telluride layer 113 are formed in order to lower the resistance values of the conductor layer 106 and the conductor layer 112, respectively. The metal telluride layer 107 is the same material as the metal telluride layer 113, and is, for example, tungsten telluride.

In addition, the lower mask layer 108 and the upper mask layer 109 are formed to pull the shortest distance between the word line (consisting of the conductor layer 106 and the metal telluride layer 107 thereon) and the subsequently formed bit line. The lower mask layer 108 is the same material as the lower mask layer 114, such as tantalum nitride. The upper mask layer 109 is made of the same material as the upper mask layer 115, and is, for example, cerium oxide (TEOS-SiO ₂ ) formed of tetraethoxy siloxane. In this embodiment, the double-layer mask layer structure is taken as an example, but the invention is not limited thereto. In other embodiments, a single layer or more than two layers of the cover layer structure may also be used.

In particular, in FIG. 1A, a gate structure 110 is formed on the peripheral region 100b as an example, but the invention is not limited thereto. In other embodiments, a plurality of gate structures 110 may be formed on the peripheral region 100b. The peripheral region 100b may have a high voltage component region and a low voltage component region (not shown), and are formed on the high voltage component region and the low voltage component region. The gate dielectric layers have different thicknesses.

In addition, in FIG. 1A, the cell region 100a is illustrated by the gate structure 102 of the flash memory. However, the present invention is not limited thereto, and the gate structure 102 on the cell region 100a may be other. Gate structure of non-volatile memory, such as The bulk layer 104 can be replaced by a charge storage layer made of a dielectric layer.

Then, referring to FIG. 1A, a liner 117 is conformally formed on the substrate 100 to cover the gate structure 102 and the gate structure 110. The material of the liner layer 117 is, for example, a high-temperature oxide (HTO), and the formation method thereof is, for example, a chemical vapor deposition process. In one embodiment, at least one ion implantation step may be performed after the step of forming the gate structure 102 and the gate structure 110 and before the step of forming the liner layer 117, in the substrate 100 of the cell region 100a. A plurality of shallow doped regions (not shown) are formed, and a plurality of shallow doped regions (not shown) are formed in the substrate 100 of the high voltage device region of the peripheral region 100b.

Next, spacers 118 are formed on the sidewalls of each of the gate structures 102 and the gate structures 110. The material of the spacers 118 is, for example, tantalum nitride. The method of forming the spacers 118 includes depositing a layer of spacer material (not shown) on the substrate 100. An anisotropic etch process is then performed to remove a portion of the spacer material layer. In an embodiment (not shown), the step of removing a portion of the spacer material layer may also remove portions of the liner 117 between the gate structures.

Thereafter, referring to FIG. 1A, a stop layer 116 is conformally formed on the substrate 100 to cover the gate structure 102 and the gate structure 110. The material of the stop layer 116 is, for example, ruthenium dioxide (TEOS-SiO ₂ ) formed of tetraethoxy siloxane, and the formation method thereof is, for example, a chemical vapor deposition process. In one embodiment, after the step of forming the spacers 118 and before the step of forming the stop layer 116, at least one ion implantation step may be performed to form a plurality of heavily doped regions in the substrate 100 of the unit cell region 100a. (not shown), and a plurality of shallow doped regions (not shown) are formed in the substrate 100 of the low voltage device region of the peripheral region 100b.

Thereafter, referring to FIG. 1B, a spacer 119 may be formed on the sidewall of the stop layer 116 on the sidewall of the gate structure 110. The material of the spacer 119 is, for example, tantalum nitride, and the formation method is, for example, chemical vapor deposition, and the thickness is, for example, 20 nm to 200 nm. The method of forming the spacers 119 includes depositing a layer of spacer material (not shown) on the substrate 100. An anisotropic etch process is then performed to remove a portion of the spacer material layer. Thereafter, a conductor layer 124 is formed on the substrate 100 to cover the gate structure 110 and fill at least the gap between the gate structures 102. The material of the conductor layer 124 is, for example, polycrystalline germanium, which is formed by, for example, a chemical vapor deposition process having a thickness of, for example, about 60 nm. Thereafter, the conductor layer 124 can be selectively planarized so that the conductor layer 124 has a flat surface. Thereafter, a mask layer 125 is formed on the cell region 100a to expose the conductor layer 124 on the peripheral region 100b. The mask layer 125 is, for example, a photoresist layer.

Referring to FIG. 1C, the mask layer 125 is used as an etch mask to pattern the conductor layer 124, and the conductor layer 124 on the peripheral region 100b is removed to expose the stop layer 116. Thereafter, the mask layer 125 is removed. Then, a stop layer 120 is formed on the substrate 100, covering the conductor layer 124 of the cell region 100a and the first stop layer 116 of the peripheral region 100b. The material of the stop layer 120 is, for example, tantalum nitride, and the formation method is, for example, chemical vapor deposition, and the thickness is, for example, 20 nm to 200 nm. Thereafter, a dielectric layer 122 is formed on the stop layer 120 of the peripheral region 100b. The material of the dielectric layer 122 is, for example, a spin-on glass, which is formed by a spin coating method. The material of the dielectric layer 122 may be, for example, ruthenium oxide, which is formed by a chemical vapor deposition method. Thereafter, the stop layer 120 on the cell region 100a is used as a polishing stop layer, and the dielectric layer on the peripheral region 100b is processed by a chemical mechanical polishing process. 122 performs a flattening process.

Thereafter, referring to FIG. 1D, the stop layer 120 on the cell region 100a is removed. A cap layer 126 is then formed over the substrate 100 to cover the conductor layer 124 on the cell region 100a and the dielectric layer 122 on the peripheral region 100b. The material of the cap layer 126 is, for example, tantalum nitride, and the method of formation is, for example, plasma enhanced chemical vapor deposition, and the thickness may be from 100 nm to 300 nm.

Thereafter, referring to FIG. 1E, using the lithography and etching process, the stop layer 116 is used as the termination layer, and the cap layer 126 and the conductor layer 124 are patterned to form a dummy self-aligned contact window plug 127 in the cell region 100a. An opening 128 is formed around the virtual self-aligning contact window plug 127. Thereafter, the spacers 130 may be selectively formed on the sidewalls of the dummy self-aligning contact window plugs 127. The material of the spacers 130 is, for example, tantalum nitride, and the thickness is, for example, 5 nm to 20 nm. The method of forming the spacers 130 includes depositing a layer of spacer material (not shown) on the substrate 100. An anisotropic etch process is then performed to remove a portion of the spacer material layer.

Thereafter, referring to FIG. 1F, a stop layer 132 is formed on the substrate 100. The material of the stop layer 132 may be the same material as the cap layer 126, such as tantalum nitride, formed by, for example, chemical vapor deposition. The stop layer 132 covers the cap layer 126 and is filled in the opening 128. Referring to FIG. 2, the distance between two adjacent drain regions 150 is a, and the maximum distance between adjacent two drain regions 150 and source regions 160 is c, and c>a. In the present embodiment, the thickness t ₁ of the stop layer 132 of FIG. 1F is greater than 1/2 of the distance a between the adjacent two drain regions 150, for example, 30 nm to 100 nm. Since the thickness t _{1 of the} stop layer 132 is greater than 1/2 of the distance a between the adjacent two drain regions 150, the gap between the adjacent two drain regions 150 can be filled, but if the thickness is not up to Between the two adjacent drain regions 150 and the source regions 160, the gap between the two adjacent drain regions 150 and the source regions 160 will not be filled by the stop layer 132. The diameter of the remaining pores is less than ca, ie the radius is less than (ca)/2. The pores may be filled by a subsequently formed hard mask material layer 136.

In addition, referring to FIG. 1F, the surface of the stop layer 132 has high and low undulations due to the structure or material layer on the substrate 100, and has a plurality of recesses 134 at the corresponding openings 128. In an embodiment, the depth of the recess 134 is, for example, 600 angstroms.

Next, referring to FIG. 1F, a hard mask material layer 136 is formed on the substrate 100. The material of the hard mask material layer 136 is different from the stop layer 132, for example, cerium oxide (TEOS-SiO ₂ ) formed of tetraethoxy siloxane, and is formed by, for example, performing a chemical vapor deposition process.

Referring to FIG. 2, more specifically, the hard mask material layer 136 may fill the recess 134 (FIG. 1F) and have a thickness t ₂ greater than half the distance (a) between the adjacent two drain regions 150 ( a/2), and greater than the maximum distance between the adjacent two drain regions 150 and the source region 160 (c) minus half the distance (a) between the adjacent two drain regions 150 ((ca) /2), for example, 100 nm to 200 nm. In one embodiment, the depth of the recess 134 is, for example, 600 angstroms, and the thickness of the hard mask material layer 136 is, for example, 1000 angstroms. The thickness t ₁ of the stop layer 132 is greater than a/2, and the radius of the aperture between the adjacent two drain regions 150 and the source region 160 due to being unable to be filled by the stop layer 132 is less than (ca)/ 2. Since the thickness t _{2 of the} hard mask material layer 136 is larger than (ca)/2, the pores having a radius smaller than (ca)/2 may be filled.

Thereafter, referring to FIG. 1G, with the stop layer 132 as the termination layer, a planarization process is performed to remove the hard mask material layer 136 other than the recess 134, leaving the hard mask layer 136a in the recess 134, leaving The hard mask layer 136a and the stop layer 132 have a flat surface. The planarization process can be carried out using a chemical mechanical polishing process.

Thereafter, referring to FIG. 1H, the hard mask layer 136a, a portion of the stop layer 132, and the cap layer 126 of the dummy self-aligned contact window plug 127 are removed, and then the dummy self-aligned contact window plug 127 is removed. Conductor layer 124 to form opening 140. In one embodiment, the material of the hard mask layer 136a is different from the material of the stop layer 132, and the material of the cap layer 126 is the same as the material of the stop layer 132, and thus may have a choice for the hard mask layer 136a/stop layer 132. An etchant having substantially the same etch rate, for example, an etchant for the hard mask layer 136a: stop layer 132 = 1:1, etching the hard mask layer 136a and the stop layer 132, and etching the top with the same etchant The cap layer 126 and its surrounding stop layer 132. In one embodiment, the depth etched down from the surface of the stop layer 132 is, for example, about 1000 angstroms. Thereafter, an etchant having a high etch selectivity for stop layer 132/stop layer 116 and a high etch selectivity ratio for cap layer 126/stop layer 116 is selected, such as for stop layer 132: stop layer 116 = 100:1 And etching the etchant for the cap layer 126: stop layer 116 = 100:1, leaving the stop layer 132a over the gate structure 102 and the spacers 130. Next, the etchant is further changed to stop the layer 116 as a termination layer, and the conductor layer 124 is etched away to form the opening 140, exposing the stop layer 116.

Thereafter, referring to FIG. 1I, the exposed stop layer 116 of the opening 140 and the underlying lining 117 are removed to form a self-aligned contact window opening 142, and then The quasi-contact window opening 142 fills the barrier metal layer 144 and the conductor metal layer 146 to form a self-aligned contact window 148 and the like. The material of the barrier metal layer 144 is, for example, titanium or titanium nitride, and the formation method is, for example, chemical vapor deposition, and the thickness is, for example, 5 nm to 30 nm. The material of the conductor metal layer 146 is, for example, tungsten, and the formation method is, for example, chemical vapor deposition, and the thickness is, for example, 100 nm to 300 nm. These subsequent steps are well known to those of ordinary skill in the art and will not be described again.

In the above embodiment, referring to FIG. 1F, after the stop layer 132 is formed on the substrate 100, the hard mask material layer 136 is formed. However, the invention is not limited thereto. When the height of the surface of the stop layer 132 is large after the formation of the stop layer 132, other steps may be included between the steps of forming the stop layer 132 and the hard mask material layer 136 to reduce high and low undulations and avoid void formation.

3A to 3C are cross-sectional views showing a part of a manufacturing process of an embedded memory device according to a second embodiment of the present invention.

Referring to FIG. 3A, the method according to the above embodiment proceeds to form the stop layer 132 of FIG. 1F. To simplify the drawing, in FIGS. 3A to 3C, only the other direction of the cell region 100a of the substrate 100 is illustrated, and the dummy contact plug 27 and the peripheral region 100b of FIG. 1F are not illustrated. The substrate 100 includes a first zone 10 and a second zone 20. The distance between two adjacent gate structures 102 on the first region 10 is less than the distance between two adjacent gate structures 102 on the second region 20. The thickness t _{1 of the} stop layer 132 is greater than half (a/2) of the distance (a) between adjacent two drain regions 150 in FIG. 2, for example, 30 nm to 100 nm. Since the gap 162 between the two adjacent gate structures 102 of the first region 10 is smaller than the gap 164 between the two adjacent gate structures 102 of the second region 20, the thickness of the stop layer 132 is insufficient. To fill the gap 164 between the two adjacent gate structures 102 of the second region 20, therefore, the height of the stop layer 132 filled in the gap 164 may be lower than the stop layer 132 filled in the gap 162. the height of.

Thereafter, referring to FIG. 3B, the anisotropic etch back stop layer 132. In the second zone 20, the stop layer 132 at the bottom of the gap 164 between the two adjacent gate structures 102 that are further apart is thinner and thus removed, and two are formed in the second gap 164. Separate spacers 132b. In the first region 10, the gap 162 between the two adjacent gate structures 102 is closer, because the thickness of the stop layer 132 is thicker, and therefore, after the anisotropic etchback, two are formed. The associated spacers 132a are not exposed to the bottom of the gap 162.

3C, a stop layer 133 is formed on the substrate 100, overlying the stop layer 116 above the gate structure 102, as well as the spacers 132a and the spacers 132b, and filling the gaps 162 and 164. The material of the stop layer 133 may be the same as or different from the material of the stop layer 132. In the present embodiment, the material of the stop layer 133 and the material of the stop layer 132 may be the same as tantalum nitride, and the formation method is, for example, chemical vapor deposition. The thickness of the stop layer 133 is greater than the maximum distance c between the adjacent two drain regions 150 and the source region 160 in FIG. 2 minus half the distance a between the adjacent two drain regions 150 ((ca)/2 ), for example, 30 nm to 100 nm. The stop layer 133 can fill the gaps 162 and 164, avoiding the formation of voids, and can reduce the height difference on the surface of the substrate 100.

Subsequent steps are as shown in FIG. 1F to form a hard mask material layer 136, and then the fabrication of the embedded memory is completed in accordance with the steps of FIGS. 1G through 1I.

4 is an image of a scanning electron microscope of a conventional embedded memory device. Figure 5 is an image of a scanning electron microscope of an embedded memory device in accordance with a second embodiment of the present invention.

Referring to FIG. 4, the conventional embedded memory device has a maximum distance between two adjacent drain regions and source regions. Because the dielectric layer cannot be filled, the surface of the dielectric layer forms voids 166, resulting in Subsequent formation of a metal layer as a metal plug may be filled in these pores, causing a problem of electrical short between the bit line and the word line.

Referring to FIG. 5, the embedded memory device according to the second embodiment of the present invention has a maximum distance between two adjacent drain regions and source regions, because the gate structure is formed by means of repeated deposition and etch back. The gap between them is filled because the gaps are formed and the stop layer is formed, so there is no problem derived from the formation of pores.

According to the embodiment of the invention, the invention can avoid forming pores at the maximum distance between two adjacent drain regions and source regions, thereby avoiding subsequent metal filling into the pores, thereby causing bit lines and characters. The problem of short circuit.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧First District

20‧‧‧Second District

100‧‧‧Base

102‧‧‧ gate structure

116‧‧‧stop layer

117‧‧‧ lining

118, 132a, 132b‧‧‧ spacers

133‧‧‧stop layer

162, 164‧ ‧ gap

Claims (16)

A method of fabricating an embedded memory device, comprising: providing a substrate comprising a cell region and a peripheral region; forming a plurality of first gate structures on the cell region of the substrate; in a peripheral region of the substrate Forming a second gate structure; forming a dielectric layer on the substrate of the peripheral region; forming a plurality of dummy self-aligned contact window plugs in the cell region, and in the dummy self-aligning contact windows Forming a plurality of openings around the substrate; forming a first stop layer on the substrate, the first stop layer filling in the openings, wherein a plurality of recesses are formed on a surface of the first stop layer corresponding to the openings; Forming a hard mask layer in each of the recesses; removing the hard mask layer and a portion of the first stop layer; removing the dummy self-aligning contact window plugs to form a plurality of self-aligned contacts a window opening; and a plurality of self-aligning contact windows are formed in the self-aligning contact window openings. The method of manufacturing the embedded memory device of claim 1, wherein the forming the hard mask layer in the recesses comprises: forming a hard mask material layer on the substrate; The first stop layer is a termination layer, and a planarization process is performed to remove the hard mask material layer other than the recesses, leaving the hard mask layers in the recesses. The manufacturer of the embedded memory device as described in claim 1 of the patent application scope The method wherein the material of the first stop layer is different from the material of the hard mask layer. The method of manufacturing the embedded memory device of claim 2, wherein when the hard mask layer and a portion of the first stop layer are removed, the hard mask layer is used: the first stop The etch of the layer selects an etchant with a ratio of 1:1. The manufacturing method of the embedded memory device of claim 4, wherein the virtual self-aligning contact windows respectively comprise a top cover layer, the material of the top cover layer being the same as the material of the first stop layer, And further comprising, after removing the hard mask layer and a portion of the first stop layer, further comprising removing the first stop layer of the cap layer and another portion. The method of fabricating an embedded memory device according to claim 5, further comprising forming a second stop layer on the substrate before forming the dummy self-aligned contact window plug and the dielectric layer, and After removing the dummy self-aligning contact window plug, the second stop layer is further removed to form the self-aligning contact window openings. The method of manufacturing an embedded memory device according to claim 6, wherein when the top cover layer and the first stop layer of the other portion are removed, the top cover layer is used: the second stop layer The etch selectivity ratio is 100:1 etchant. The method for manufacturing an embedded memory device according to claim 1, further comprising forming a spacer on each side wall of the dummy self-aligning contact window plug. The method of manufacturing an embedded memory device according to claim 8, wherein the material of the spacers is the same as the material of the first stop layer. The method of manufacturing an embedded memory device according to claim 1, wherein t ₁ > a/2, t ₁ is a thickness of the first stop layer; a is a distance between adjacent two drain regions . The method of fabricating an embedded memory device according to claim 1, wherein the cell region includes a first region and a second region, and the first gate structures on the first region have a first gap, a second gap between the first gate structures on the second region, the first gap being smaller than the second gap, the height of the first stop layer in the second gap Lower than the height of the first stop layer in the first gap, after forming the first stop layer and before forming the hard mask layers in each of the recesses, further comprising: anisotropic etching a stop layer, forming a first gap in the first gap, and forming a second spacer separated from each other in the second gap; and forming a first layer on the first region and the second region The second stop layer fills the first gap and the second gap. The method of manufacturing an embedded memory device according to claim 11, wherein the second stop layer is the same material as the first stop layer. The method of manufacturing an embedded memory device according to claim 11, wherein t ₁ > a/2 and t ₂ > (ca)/2, wherein t ₁ is the thickness of the first stop layer; t ₂ The thickness of the second stop layer; a is the distance between two adjacent drain regions; and c is the maximum distance between the adjacent two drain regions and one source region. A method of fabricating an embedded memory device, comprising: providing a substrate, the substrate comprising a cell region, and the cell region includes a first region and a second region; forming a plurality of first gates on the substrate a first gap between the first gate structures on the first region, and a second gap between the first gate structures on the second region, the first gap being smaller than the first gap a second gap; forming a plurality of dummy self-aligning contact window plugs on the first area and the second area, and forming a plurality of openings around the virtual self-aligning contact windows; forming a first a stop layer, the first stop layer being filled in the openings, wherein a plurality of recesses are formed on a surface of the first stop layer corresponding to the openings, wherein the first stop layer in the second gap a height lower than a height of the first stop layer in the first gap; anisotropic etching of the first stop layer, forming a first gap in the first gap, and in the second gap Forming a second spacer separated from each other; and in the Region is formed on the second region and a second stop layer, fills the first gap and the second gap. The method of manufacturing an embedded memory device according to claim 14, wherein the second stop layer is made of the same material as the first stop layer. The method of manufacturing an embedded memory device according to claim 14, wherein t ₁ >a/2; and t ₂ > (ca) / 2, wherein t ₁ is the thickness of the first stop layer; t ₂ The thickness of the second stop layer; a is the distance between two adjacent drain regions; and c is the maximum distance between the adjacent two drain regions and one source region.