KR20120127026A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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Publication number
KR20120127026A
KR20120127026A KR1020110045222A KR20110045222A KR20120127026A KR 20120127026 A KR20120127026 A KR 20120127026A KR 1020110045222 A KR1020110045222 A KR 1020110045222A KR 20110045222 A KR20110045222 A KR 20110045222A KR 20120127026 A KR20120127026 A KR 20120127026A
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KR
South Korea
Prior art keywords
storage node
node contact
film
plug
forming
Prior art date
Application number
KR1020110045222A
Other languages
Korean (ko)
Inventor
이일용
Original Assignee
에스케이하이닉스 주식회사
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Priority to KR1020110045222A priority Critical patent/KR20120127026A/en
Publication of KR20120127026A publication Critical patent/KR20120127026A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/1085Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto
    • H01L27/10852Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor extending over the access transistor
    • H01L27/10855Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor extending over the access transistor with at least one step of making a connection between transistor and capacitor, e.g. plug

Abstract

The present invention provides a method of manufacturing a semiconductor device capable of increasing the capacitance of a capacitor, comprising the steps of: forming a first and a second insulating film on a substrate including a landing plug contact; Selectively etching the first and second insulating layers to form storage node contact plugs and bit lines respectively connected to the landing plug contacts; Forming a third insulating layer on the second insulating layer including the storage node contact plug; Selectively etching the third insulating layer to form an open portion exposing the storage node contact plug; Opening the storage node contact hole by removing the exposed storage node contact plug; And forming a lower electrode on sidewalls and a lower portion of the storage node contact hole and the open part, thereby increasing capacitance by the height of the storage node contact as the lower electrode is formed in the storage node contact region. In addition, the landing plug contact may be formed of a metal material to minimize the interface resistance and the contact resistance between the lower electrodes.

Description

Semiconductor device manufacturing method {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a method of manufacturing a capacitor.
In a conventional gate structure, a gate is formed on a substrate, a landing plug contact is formed between the gates, and is connected to a source / drain, and a storage node contact is formed on the landing plug contact. It has a structure for connecting the capacitor and the substrate.
Recently, a buried gate structure has been proposed in which a gate is buried after etching a substrate to form a trench without forming a gate on the substrate as a semiconductor device is reduced in size.
Meanwhile, as the size of the semiconductor device is reduced, the area of the capacitor is also reduced, so that the capacity of the capacitor required for sensing is also reduced. In addition, although it is difficult to apply a capacitor of a cylinder type (Cylinder Type) in the process, a capacitor of a concave or pillar type is used, but these have a problem in that the capacity is smaller than a cylindrical capacitor.
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device capable of increasing the capacity of a capacitor.
A semiconductor device manufacturing method according to an embodiment of the present invention for achieving the above object comprises the steps of forming a first and a second insulating film on a substrate including a landing plug contact; Selectively etching the first and second insulating layers to form storage node contact plugs and bit lines respectively connected to the landing plug contacts; Forming a third insulating layer on the second insulating layer including the storage node contact plug; Selectively etching the third insulating layer to form an open portion exposing the storage node contact plug; Opening the storage node contact hole by removing the exposed storage node contact plug; And forming a lower electrode on sidewalls and a lower portion of the storage node contact hole and the open portion.
In particular, the landing plug contact may be formed of a material having a wet selectivity different from that of the storage node contact plug material.
The semiconductor device manufacturing method according to the embodiment of the present invention described above has the effect of increasing the capacitance by the height of the storage node contact by forming the lower electrode in the storage node contact region.
In addition, the landing plug contact may be formed of a metal material to minimize the interface resistance and the contact resistance between the lower electrodes.
1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention.
1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
As shown in FIG. 1A, an isolation layer 12 is formed on a substrate 11 through a shallow trench isolation (STI) process. The device isolation layer 12 may include an oxide layer such as a high density plasma oxide layer (HDP oxide) or a spin on dielectric layer (Spin On Dielectric).
Subsequently, the trench 13 is formed by etching the active region of the substrate 11 defined by the device isolation layer 12. The trench 13 may be formed by using a pad film (not shown) used to form the device isolation film 12 as an etch barrier film.
Subsequently, a buried gate 14 filling a part of the trench 13 is formed. Before forming the buried gate 14, a gate insulating film (not shown) is formed on the surface of the trench 13. Then, a metal film filling the trench 13 is deposited, planarized, and formed by recessing the trench 13 so as to be embedded in a portion of the trench 13.
The metal film is a material for forming a buried gate and may include at least one selected from the group consisting of a tantalum nitride film (TaN), a titanium nitride film (TiN), and a tungsten film (W). For example, the metal film may be formed of a two-layer structure such as TiN / W or TaN / W, which uses TiN or TaN alone or laminates a tungsten film (W) on a titanium nitride film (TiN) or a tantalum nitride film (TaN). can do. In addition, it may include a two-layer structure of WN / W for stacking the tungsten film (W) on the tungsten nitride film (WN), in addition to a low resistance conductor metal material.
The planarization process may be a chemical mechanical polishing (CMP) process, and the recess of the metal film may be an etch back process.
Thus, the buried gate 14 partially embedded in the trench 13 is formed.
Subsequently, an upper portion of the buried gate 14 is gap-filled using the capping film 15. At this time, the capping film 15 uses an oxide film. The oxide film includes, for example, any one selected from the group consisting of SOD (Spin On Dielectric) oxide, Low Pressure TEOS (LP-TEOS), Plasma Enhanced TEOS (PE-TEOS), and High Density Plasma (HDP) oxide.
Subsequently, the pad film (not shown) used as an etch barrier film is removed when the device isolation film 12 and the buried gate 14 are formed. As a result, the grooves 16 are formed at the positions where the pad films (not shown) were present.
As shown in FIG. 1B, landing plug contacts 17, 18 are formed in the grooves 16 on the substrate 11. The landing plug contacts 17 and 18 may include a metal material film, and preferably have a stacked structure of the barrier metal film 17 and the metal material film 18. The barrier metal film 17 includes a laminated structure of a titanium film and a titanium nitride film, and the metal material film 18 includes a tungsten film.
In detail, the barrier metal film 17 is formed along the step of the entire structure including the groove 16, and the metal material film 18 gap-filling the groove 16 is formed on the barrier metal film 17. Thereafter, a planarization (for example, chemical mechanical polishing (CMP)) process is performed on the target on which the capping layer 15 is exposed to form the landing plug contacts 17 and 18. In this case, the landing plug contacts 17 and 18 between the buried gates 14 are connected to the bit lines, and the landing plug contacts 17 and 18 between the buried gates 14 and the device isolation layer 12 are formed through a subsequent process. Connected to the storage node.
As shown in FIG. 1C, the first insulating layer 19 is formed on the substrate 11 including the landing plug contacts 17 and 18. The first insulating layer 19 is for insulating between the buried gate 14 and the upper layer, and may be formed in a single layer or multiple layers.
Subsequently, a second insulating film 20 is formed on the first insulating film 19. The second insulating film 20 is preferably formed of an oxide film.
Subsequently, the second and first insulating layers 20 and 19 are selectively etched to form a damascene pattern for opening the landing plug contacts 17 and 18 between the buried gate 14 and the device isolation layer 12. The conductive material is embedded to form a storage node contact plug 21. In this case, the conductive material includes polysilicon.
Next, a hard mask layer 22 is formed on the second insulating layer 20 including the storage node contact plug 21. The hard mask layer 22 is an etch barrier for etching the second and first insulating layers 20 and 19 when the damascene pattern 23 for forming the bit line and the bit line contact is formed. Play a role. The hard mask layer 22 is formed of a material having an etching selectivity with respect to the first and second insulating layers 19 and 20. For example, the hard mask layer 22 is formed of a nitride layer.
Subsequently, the second and first insulating layers 20 and 19 are etched using the hard mask layer 22 as an etch barrier to form a damascene pattern 23 for bit lines and bit line contacts.
As shown in FIG. 1D, bit lines and bit line contacts 24 that partially fill the damascene pattern 23 are formed. The bit line and bit line contacts 24 are connected to the landing plug contacts 17 and 18 between the buried gates 14, and the landing plug contacts 17 and 18 are formed of a metal material, so that the bit line contacts and the bit line are formed. (24) Also when formed of a metal material has the effect of reducing the contact resistance and interface resistance.
Next, the hard mask film 22 (refer to FIG. 1C) is removed.
Subsequently, an etch barrier film 25 is formed on the entire structure including the bit lines and the bit line contacts 24. The etch barrier 25 fills the remaining portion of the damascene pattern 23 and is formed on the storage node contact 21 to prevent attack of the lower layer when forming an opening for a subsequent storage node. do. The etch barrier layer 25 is formed of a material having an etch selectivity with respect to the bit line and the bit line contact 24, the second insulating layer 20, and the third insulating layer 26. It is formed of a nitride film.
Subsequently, a third insulating layer 26 is formed on the etch barrier film 25. The third insulating layer 26 is provided to provide an open portion 27 for the storage node, and may be formed of, for example, an oxide layer.
Subsequently, the third insulating layer 26 and the etch barrier layer 25 are selectively etched to form an open portion 27 exposing the storage node contact 21.
As illustrated in FIG. 1E, the storage node contact hole 21A exposed by the open part 27 is removed to reopen the storage node contact hole 21A exposing the landing plug contacts 17 and 18. When the storage node contact 21 is formed of polysilicon, it may be removed by dip out.
By removing the storage node contact 21, the storage node contact hole 21A and the open part 27 on the landing plug contacts 17 and 18 are simultaneously opened.
As shown in FIG. 1F, the lower electrode 28 is formed along the steps between the storage node contact hole 21A and the open part 27. The lower electrode 28 may be formed of a metal material film, for example, a titanium nitride film (TiN).
In a subsequent process, a dielectric film and an upper electrode are formed on the lower electrode 28 to form a capacitor.
As described above, by removing the storage node contact 21 and forming the lower electrode 28 in the reopened storage node contact hole 21A, the capacitance of the storage node contact hole 21A, that is, the side area, is increased. ) Has the advantage of securing. In addition, since the lower portion of the lower electrode 28 is supported, the lowering of the lower electrode 28 may be prevented.
In addition, since the landing plug contacts 17 and 18 are formed of a metal material rather than polysilicon, contact resistance and interfacial resistance with the lower electrode 28 formed of the metal material may be minimized.
In the present embodiment, the concave type lower electrode 27 is formed, but the present invention is not limited thereto, and the present invention may be applied to a pillar type lower electrode or the like.
Although the technical spirit of the present invention has been described in detail according to the above embodiments, it should be noted that the above embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.
11 substrate 12 device isolation film
13: trench 14: buried gate
15: capping film 16: groove
17 barrier metal film 18 metal material film
19: first insulating film 20: second insulating film
21: Storage Node Contact 21A: Storage Node Contact Hole
22: hard mask film 23: damascene pattern
24: bit line and bit line contact 25: etch barrier
26: third insulating film 27: open portion
28: lower electrode

Claims (2)

  1. Forming first and second insulating films on the substrate including the landing plug contacts;
    Selectively etching the first and second insulating layers to form storage node contact plugs and bit lines respectively connected to the landing plug contacts;
    Forming a third insulating layer on the second insulating layer including the storage node contact plug;
    Selectively etching the third insulating layer to form an open portion exposing the storage node contact plug;
    Opening the storage node contact hole by removing the exposed storage node contact plug; And
    Forming a lower electrode on sidewalls and a lower portion of the storage node contact hole and the open portion
    ≪ / RTI >
  2. The method of claim 1,
    And the landing plug contact is formed of a material having a different wet selectivity from the storage node contact plug material.
KR1020110045222A 2011-05-13 2011-05-13 Method for fabricating semiconductor device KR20120127026A (en)

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KR1020110045222A KR20120127026A (en) 2011-05-13 2011-05-13 Method for fabricating semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10008505B2 (en) 2015-07-14 2018-06-26 Samsung Electronics Co., Ltd. Semiconductor device including capacitor and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10008505B2 (en) 2015-07-14 2018-06-26 Samsung Electronics Co., Ltd. Semiconductor device including capacitor and method of manufacturing the same

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