KR20040057485A - Method for fabricating semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to increase cell capacitance by reducing loading capacitance. CONSTITUTION: A plurality of conductive patterns including the first conductive layer(36) as a bit line and a nitride hard mask(37) are formed on a substrate(30). An interlayer dielectric(38) is formed on the resultant structure. The interlayer dielectric is recessed by partially etching. An etch stop layer is formed on the recessed interlayer dielectric. A self-aligned contact hole is formed to expose the substrate by etching the etch stop layer and the interlayer dielectric. A plug(42) is then formed by filling the second conductive layer in the contact hole.

Description

Semiconductor device manufacturing method {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of reducing parasitic capacitance of a semiconductor memory cell.

Hereinafter, the problems of the prior art will be described by using the storage node contact hole forming process as an example.

1A to 1D are cross-sectional views illustrating a storage node contact hole forming process according to the prior art.

First, an interlayer insulating film 13 (also called a word line insulating film) is deposited on a substrate 11 on which various elements for forming a semiconductor device such as a word line (not shown) and an impurity bonding layer 12 are formed, and then an interlayer insulating film ( 13) is selectively etched to form contact holes (not shown) that expose the impurity junction layer 12.

Subsequently, the contact hole is filled and the exposed impurity bonding layer 12 is contacted to form a plug 14 for the storage node and the bit line contact. As the plug 14 material, polysilicon is generally used. In recent years, there has been an increase in the use of a multilayered structure in which a barrier metal layer such as Ti / TiN and tungsten are laminated in addition to polysilicon.

Subsequently, a diffusion barrier 15 having a conventional Ti / TiN structure is used to prevent the source gas used in the subsequent deposition of the metal film for the bit line such as tungsten with the plug 14 or the impurity bonding layer 12. On the plug 14, a bit line metal film 16 is formed on the diffusion barrier film 15 using a metal such as polysilicon or tungsten or a metal alloy thin film such as tungsten nitride or tungsten silicide. .

Subsequently, the buffer layer 17 is formed by using a USG (Undoped Silicate Glass) film or the like to reduce the stress that is likely to occur between the metal film 16 and the nitride film mainly used as a subsequent hard mask. Here, the process of forming the buffer layer 17 can be omitted.

Nitride layer 18 for hard mask through plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD) on the buffer layer 17. Deposit. 1A shows a state in which a hard mask nitride film 18 is deposited.

The hard mask nitride film 18 includes a conventional nitride film-based material such as a silicon oxynitride film or a silicon nitride film.

As illustrated in FIG. 1B, a bit line is selectively formed by selectively etching the hard mask nitride layer 18, the buffer layer 17, the metal layer 16, and the diffusion barrier 15 using the bit line etching mask.

As the degree of integration of semiconductor devices is improved, it is difficult to stably secure the margins and overlay accuracy of the pattern forming process itself using photoresist, and thus a Self Align Contact (SAC) process is introduced. As a result, the SAC process plays a significant role in reducing the cost by forming a contact hole or the like by using an already deposited material instead of using a mask. The SAC process itself uses a variety of methods, but a representative method uses a nitride film as an etch stop film. Therefore, in the SAC etching process, the insulating layer is etched under the condition that the oxide film is etched faster than the nitride film after the sidewalls and the upper part of the conductive pattern such as the gate electrode or the bit line are wrapped with the nitride film.

Since the storage node contact forming process also applies the SAC process, a nitride-based etch stop layer 19 is deposited on the entire structure in which the bit lines are formed in order to prevent loss of the bit lines by the SAC process.

FIG. 1C illustrates a cross-sectional profile in which an etch stop layer 19 is formed along the upper sidewalls and the bit lines.

Subsequently, as shown in FIG. 1D, an interlayer insulating film 21 (aka bit line insulating film) is formed on the entire surface where the etch stop film 19 is formed. At this time, a low temperature USG film is usually used as the interlayer insulating film 21.

Subsequently, the interlayer insulating layer 21 is subjected to chemical mechanical polishing (hereinafter referred to as CMP) to a target such that the interlayer insulating layer 21 remains a certain thickness on the nitride layer 18 for the hard mask. A plug between the bit lines is formed through a SAC process in which a photoresist pattern 22 for forming a code contact is formed and the interlayer insulating layer 21 and the etch stop layer 19 are sequentially etched using the photoresist pattern 22 as an etch mask. (14) A contact hole 23 exposing the surface is formed.

Before forming the contact hole, a process of forming a contact pad is additionally performed in order to improve the overlap margin at the time of contact formation, which is omitted for simplicity of description.

In the typical process cross-section after the SAC process, as shown in FIG. 1D, the nitride stop layer 19 is etched in the SAC etching process to remain in the spacer 20 shape.

On the other hand, the silicon nitride film is a representative example of the nitride film has a dielectric constant of 7.5 has a high dielectric constant compared to 3.9 of the silicon oxide film is a representative example of the oxide film.

This is because the plug structure using the contact hole formed by the SAC process is applied to a semiconductor memory device such as DRAM (Dynamic Random Access Memory) to form the capacitor contact hole as the SAC process for the bit line, that is, between the bit lines in the SAC etching process. When forming a capacitor contact hole by etching, the capacitance of the bit line is increased as compared to a conventional contact structure in which the bit line and the capacitor contact plug (in principle, the charge storage electrode) are insulated with an oxide film such as a silicon oxide film. This means an increase in capacitance (loading capacitance), which causes a decrease in cell capacitance.

Therefore, there is an urgent need to establish a process capable of minimizing the cell capacitance reduction due to the nitride film while obtaining such a SAC profile.

The present invention has been proposed to solve the above problems of the prior art, and has an object of the present invention to provide a method for manufacturing a semiconductor device that can increase the cell capacitance by reducing the loading capacitance.

1A to 1D are cross-sectional views illustrating a storage node contact hole forming process according to the prior art.

2A to 2F are cross-sectional views illustrating a storage node contact plug forming process according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

30 substrate 31 impurity bonding layer

32, 34, 38: interlayer insulating film 33, 42: plug

35 diffusion barrier film 36 bit line metal film

37: hard mask nitride film

In order to achieve the above object, the present invention comprises the steps of: forming a plurality of conductive patterns having a gap therebetween with a first conductive film and a Haasmask nitride film laminated on the first conductive film on a substrate; Forming a planarized interlayer insulating film on an entire surface on which the conductive pattern is formed; Recessing the interlayer dielectric layer to a height lower than an upper end of the hard mask nitride layer through a wet process or a dry process; Forming an etch stop film along the entire profile of the interlayer insulating film recessed; Selectively etching the etch stop layer and the interlayer dielectric layer to form a self-aligned contact hole exposing the substrate over the gap and partially extending over each conductive pattern; And filling the self-aligned contact hole with a second conductive layer to form a self-aligned contact structure.

According to the present invention, after the bit line is formed, the upper portion of the bit line insulating layer is made lower than the bit line through a wet removal process after depositing and planarizing the interlayer insulating layer (bit line insulating layer), and then forming an etch stop layer on the storage node. A SAC process is performed to form contacts.

As a result, almost all of the etch stop layer based on the nitride film is removed by the SAC process, and a contact hole is formed through which the lower plug between the bit lines is exposed. Accordingly, the nitride-based etch stop layer remaining in the spacer form on the sidewall of the bit line can be removed while obtaining the SAC profile as in the related art, thereby preventing an increase in the loading capacitance according to the nitride layer, thereby increasing the cell capacitance. Can be.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2A through 2F are cross-sectional views illustrating a storage node contact plug forming process according to an exemplary embodiment of the present invention.

First, an interlayer insulating film 32 (also known as a word line insulating film) is deposited on a substrate 30 on which various elements for forming a semiconductor device such as a word line (not shown) and an impurity bonding layer 31 are formed, and then an interlayer insulating film ( 32 is selectively etched to form contact holes (not shown) that expose the impurity junction layer 31.

Subsequently, the contact hole is filled and the exposed impurity bonding layer 31 is contacted to form a plug 33 for the storage node and the bit line contact. Here, the plug 33 may include a conventional landing plug contact that contacts the impurity bonding layer 31 of the substrate 30 for bit line contact, storage node contact, or the like.

As the plug 33 material, polysilicon is generally used. In recent years, there has been an increase in the use of a multilayer structure in which a barrier metal layer such as Ti / TiN and tungsten, which are mainly used as diffusion barriers, are laminated in addition to polysilicon.

Subsequently, a process of forming a contact pad or the like is performed on the plug 33, which is omitted for the sake of simplicity of the drawings, and only the process of forming the interlayer insulating film 34 is shown.

Subsequently, in order to suppress reaction of the source gas used in the subsequent deposition of the metal film for the bit line such as tungsten with the plug 33 or the impurity bonding layer 31, a diffusion barrier 35 having a conventional Ti / TiN structure is used. On the interlayer insulating film 34, a metal film 36 for bit lines is formed on the diffusion barrier 35 by using a metal such as polysilicon or tungsten or a metal alloy thin film such as tungsten nitride or tungsten silicide. do.

The nitride film 37 for a hard mask is deposited on the diffusion barrier layer 35 through PECVD or LPCVD. 2A shows a state in which a hard mask nitride film 37 is deposited.

The hard mask nitride film 37 includes a conventional nitride film-based material such as a silicon oxynitride film or a silicon nitride film, and in the embodiment of the present invention, the thickness of the hard mask nitride film 37 is applied in a thickness of 1000 kPa to 5000 kPa. Indicates.

On the other hand, an additional process of forming a buffer layer (not shown) using a USG film or the like may be performed to reduce the stress likely to occur between the metal film 36 and the nitride film mainly used as a subsequent hard mask.

As illustrated in FIG. 2B, the hard mask nitride layer 37, the metal layer 36, and the diffusion barrier layer 35 are selectively etched using the bit line etching mask to form the nitride layer 37, the metal layer 36, and the like. A bit line having a structure in which the diffusion barrier 35 is stacked is formed.

An interlayer insulating film 38 (also called a bit line insulating film) is formed on the entire surface where the bit lines are formed. At this time, the interlayer insulating film 38 may include a BPSG (BoroPhospho Silicate Glass) film, a HTO (High Temperature Oxide) film, an MTO (Medium Temperature Oxide) film, an HDP (High Density Plasma) oxide film, a TEOS (TetraOrthoOrtho Silicate) film, or an APL (APL) film. Advanced Planarization Layer) may be used.

Subsequently, CMP is applied to a target such that the interlayer insulating film 38 is substantially the same height as the nitride film 37 for a hard mask to planarize the interlayer insulating film 38, and then wet such as BOE (Buffered Oxide Etchant) or HF. The interlayer insulating layer 38 is recessed through a wet etching process using a solution, so that the height of the interlayer insulating layer 38 is lower than that of the hard mask nitride layer 37 as shown in FIG.

On the other hand, in addition to the above-described wet etching method is also possible through a dry process.

In the present embodiment, the etching is performed to a depth of about 300 kPa to 1500 kPa from the top of the hard mask nitride film 37. FIG. 2C shows a state where the interlayer insulating film 38 is recessed.

Subsequently, since the SAC process is applied to the storage node contact formation as described above, the interlayer insulating film 38 recessed to prevent loss of bit lines by the SAC process and to have an etching selectivity of the interlayer insulating film 38 which is an oxide film series. A nitride stop film 39 is deposited along the profile.

Subsequently, the photoresist pattern 40 for forming a storage node contact is formed on the etch stop layer 39.

FIG. 2D illustrates a cross-sectional profile in which an etch stop layer 39 is formed over the bit line and the surface of the recessed interlayer insulating layer 38, and the photoresist pattern 40 is formed thereon.

Here, the etch stop film 39 is formed of a nitride film-based material such as a silicon nitride film or a silicon oxynitride film, and is preferably formed to have a thickness of about 50 kPa to about 500 kPa.

The contact hole 41 exposing the surface of the plug 33 between bit lines through an SAC process in which the etch stop layer 39 and the interlayer dielectric layers 38 and 34 are sequentially etched using the photoresist pattern 40 as an etch mask. ).

In the typical process cross-section after the SAC process, the nitride-based etch stop layer 39 must be etched in the SAC etching process and remain in the spacer shape on the sidewall of the contact hole 41 as in the above-described conventional technique. Do not.

Therefore, it is important to appropriately apply the thickness and the etch recipe according to the applied design rules so that the etch stop layer 39 does not remain on the sidewall of the contact hole 41 while obtaining the desired etch profile.

2E illustrates a process cross section in which a storage node contact hole 41 is formed.

Meanwhile, before forming the contact hole, a process of forming a contact pad is additionally performed in order to improve the overlap margin at the time of forming the contact, which is omitted for simplicity of description.

After depositing a conductive material for the storage node contact plug to fill the contact hole 41, the etch stop layer 39 and the conductive material remaining as an etch target to which the surface of the interlayer insulating layer 38 is exposed are removed by a CMP process. Form planarized and isolated storage node contact plugs.

FIG. 2F shows a process cross section in which the storage node contact plug 42 is connected to the lower plug 33 through the bit lines.

Meanwhile, in the present invention, an oxide-based interlayer insulating film 38 having a low dielectric constant is present between the plug 42 and the bit line. This reduces the loading capacitance of the parasitic capacitor constituted by the plug 42 and the bit line and the interlayer insulating film 38 therebetween.

In this way, the loading capacitance can be reduced, and the effect of increasing the overall cell capacitance can be expected.

In the present invention made as described above, the bit line insulating film is recessed lower than the top of the bit line hard mask through the planarization and wet etching process after the bit line insulating film deposition, and then the profile having the recessed step is applied. After forming the nitride-based etch stop layer, a contact hole for forming a storage node is formed between the bit lines through the SAC process, so that the etch-stop layer of the nitride-based layer does not remain on the sidewall of the bit line so that subsequent storage node contact plugs and bit lines are formed. It was found through the examples that the loading capacitance formed by the present invention can be reduced.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, the present invention can be applied to all semiconductor processes to which the SAC process is applied, such as not only a storage node contact plug but a process of opening an active region between gate electrodes.

As described above, the present invention can improve the cell capacitance by reducing the loading capacitance of the bit line or the like, and ultimately, an excellent effect of improving the performance of the semiconductor device can be expected.

Claims (7)

Forming a plurality of conductive patterns having a first conductive film and a Haasmask nitride film stacked on the first conductive film on a substrate, and having a gap therebetween; Forming a planarized interlayer insulating film on an entire surface on which the conductive pattern is formed; Recessing the interlayer dielectric layer to a height lower than an upper end of the hard mask nitride layer through a wet process or a dry process; Forming an etch stop film along the entire profile of the interlayer insulating film recessed; Selectively etching the etch stop layer and the interlayer dielectric layer to form a self-aligned contact hole exposing the substrate over the gap and partially extending over each conductive pattern; And Filling the self-aligned contact hole with a second conductive layer to form a self-aligned contact structure Semiconductor device manufacturing method comprising a. The method of claim 1, The etch stop layer is a nitride film-based, the semiconductor device manufacturing method, characterized in that formed in a thickness of 50 ~ 500Å. The method of claim 2, The layered insulating film is a semiconductor device manufacturing method characterized in that the oxide film series. The method of claim 1, The hard mask nitride film is formed to a thickness of 1000 ~ 5000 Å semiconductor device manufacturing method. The method of claim 4, wherein In the step of recessing the interlayer insulating film, the semiconductor device manufacturing method being recessed so as to be as low as about 300 mW to about 1500 mW from an upper end of the hard mask nitride film. The method of claim 5, wherein The interlayer insulating film is a BPSG (BoroPhospho Silicate Glass) film, HTO (High Temperature Oxide) film, MTO (Medium Temperature Oxide) film, HDP (High Density Plasma) oxide film, TEO (TetraOrthoOrtho Silicate) film, APL (Advanced Planarization Layer) film A semiconductor device manufacturing method, characterized in that any one film selected from the group consisting of. The method of claim 1, And the first conductive layer is a bit line, and the second conductive layer is a storage node contact plug-in.