KR20050003296A - Method for forming the semiconductor memory device having a self-aligned contact hole - Google Patents

Abstract

PURPOSE: A method of forming a semiconductor memory device having a self-aligned contact hole is provided to protect a bit line from an etching process by forming a buffer insulating layer only on a lateral part of a bit line and a surface of a second interlayer dielectric. CONSTITUTION: A first interlayer dielectric is formed on a semiconductor substrate including a transistor. A conductive layer plug(102) is formed on the first interlayer dielectric. A second interlayer dielectric(104) is formed thereon. A bit line(106) connected vertically to the conductive layer plug is formed on the second interlayer dielectric. A hard mask(108) is laminated thereon. A buffer insulating layer(110a) is formed on a lateral part of the bit line and an upper part of the second interlayer dielectric. A barrier insulating layer and a third interlayer dielectric are formed on the entire surface of the hard mask layer and the buffer insulating layer. A self-aligned contact hole is formed by etching the third and second interlayer dielectrics between the bit lines.

Description

Method for forming the semiconductor memory device having a self-aligned contact hole}

The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a semiconductor memory device having a bit line and a self-aligned contact hole (hereinafter referred to as SAC).

In general, in accordance with high integration of semiconductor memory devices, the area of cells and the like of semiconductor memory devices has been reduced to a minimum. To this end, techniques for continuously miniaturizing the line width of metal wiring have been researched and developed. Recently, as the importance of tungsten (W) wiring having good step coverage characteristics instead of aluminum wiring is highlighted, tungsten wiring technology has been widely used for forming bit lines.

Meanwhile, as the semiconductor memory is highly integrated and design rules are scaled down, the SAC process is inevitably introduced to form bit line contacts or storage node contacts. In the conventional SAC process, tungsten (W) using bit resistance is excellent in low resistance and step coverage.

1A to 1E are diagrams illustrating a manufacturing process of a semiconductor memory device having a self-aligning contact (SAC) hole according to the prior art, and the SAC contact hole manufacturing process of the prior art will be described with reference to these drawings.

First, as shown in FIG. 1A, a first interlayer insulating film 10 is formed on a front surface of the semiconductor substrate (not shown) in which the device isolation layer and the cell transistor are formed to insulate the transistor and the wiring to be formed later. Next, the first interlayer insulating film 10 is etched to form a contact hole for exposing an active region of the semiconductor substrate, and for example, a conductive layer such as doped polysilicon or tungsten (W) is deposited and chemical mechanical polishing (CMP) is performed. : Chemical Mechanical Polishing) to form a conductive layer plug 12 connected to the junction region of the transistor. A second interlayer insulating film 14 covering the resultant is formed to insulate the plugs 12, and a metal such as tungsten (W) or a metal silicide thereof is deposited thereon. Subsequently, an insulating film for a hard mask is deposited on the metal or the metal silicide layer using silicon nitride or the like. Then, the insulating layer stacked sequentially and a metal or metal silicide layer below are patterned by a photo and etching process using a bit line mask to form a bit line 16 connected to any one of the plugs 12 and a hard mask layer thereon. 18).

Then, as shown in FIG. 1B, the hard mask layer 18 and the second layer serve as a buffer between the bit line 16 and the barrier insulating film for SAC to be formed later while preventing partial oxidation of the bit line 16. The buffer insulating film 20 is thinly deposited on the entire surface of the interlayer insulating film 14 with silicon oxide or the like.

Subsequently, as shown in FIG. 1C, a barrier insulating layer 22 is formed of silicon nitride or the like to prevent etching of the lower structure during the SAC contact hole etching process.

As shown in FIG. 1D, a third interlayer insulating film 24 is formed on the entire surface of the resultant having the barrier insulating film 22.

Then, as shown in FIG. 1E, an etching process using a SAC contact hole mask is performed to etch the third interlayer insulating film 24 between the bit lines 16 to the second interlayer insulating film 14 to form a lower plug ( A SAC contact hole 26 through which 12 is exposed is formed. Although not shown in the drawings, a doped polysilicon film is deposited on the entire surface, for example, on the resultant formed SAC contact hole 26, and then a chemical mechanical polishing (CMP) process is buried in the contact hole and A SAC contact electrode of the storage node connected with the junction region is formed.

However, even when the buffer insulating film 20 and the barrier insulating film 24 are etch selectivity with different insulating materials in the aforementioned SAC contact hole etching process, the buffer insulating film 20 may be formed of the third interlayer insulating film 24. When the silicon oxide is made of similar silicon oxide, the etching speed is faster than that of the barrier insulating layer (silicon nitride), and the surface of the lower tungsten bit line 16 is etched as shown in FIG. When the SAC process is performed on the exposed tungsten bit line, the SAC contact electrode and the bit line of the storage node of the semiconductor memory are shorted.

An object of the present invention is to form a buffer insulating film on the bit line side and the second interlayer insulating film surface without forming the buffer insulating film to the upper side of the hard mask film in order to solve the problems of the prior art as described above bit line during the SAC contact hole etching process The present invention provides a method of manufacturing a semiconductor memory device having a self-aligning contact hole that etch-protects a bit line while the barrier insulating film on the side of the hard mask film is etched while serving as a sufficient buffer in the barrier insulating film.

1A to 1E are views illustrating a manufacturing process of a semiconductor memory device having a self-aligning contact hole according to the prior art;

2A to 2F are flowcharts illustrating a method of manufacturing a semiconductor memory device having a self-aligning contact hole according to the present invention.

Explanation of symbols on the main parts of the drawings

100: first interlayer insulating film 102: conductive layer plug

104: second interlayer insulating film 106: bit line

108: hard mask film 110a: buffer insulating film

112 gap gap film 114 barrier film

116: third interlayer insulating film 118: self-aligned contact hole

In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor memory device, comprising: forming a first interlayer insulating film covering a semiconductor substrate on which a transistor is formed; and a conductive layer connected to the semiconductor substrate on the first interlayer insulating film. Forming a plug, forming a second interlayer insulating film covering the resultant on which the conductive layer plug is formed, a bit line vertically connected to any one of the upper conductive plugs on the second interlayer insulating film, and a hard mask stacked thereon Forming a buffer insulating film on the side of the bit line and the upper portion of the second interlayer insulating film, sequentially forming a barrier insulating film and a third interlayer insulating film on the hard mask film and the buffer insulating film, respectively, When any of the conductive layer plugs is exposed by etching to the third interlayer insulating film and the second interlayer insulating film between It forms a self-aligned contact hole.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2F are flowcharts illustrating a method of manufacturing a semiconductor memory device having a self-aligned contact (SAC) hole according to the present invention. Referring to these drawings, a SAC manufacturing process according to an embodiment of the present invention will be described. Explain.

As shown in FIG. 2A, a first interlayer insulating film 100 is formed on the entire surface of the semiconductor substrate (not shown) in which the device isolation layer and the cell transistor are formed to insulate the cell transistor and the wiring to be formed later. Next, the first interlayer insulating layer 100 is etched to form a contact hole for exposing an active region of the semiconductor substrate, and a conductive layer such as doped polysilicon or tungsten (W) is deposited and chemically mechanically polished (CMP) to form a contact hole. The conductive layer plug 102 connected to the junction region of is formed. In order to insulate the plugs 102, a second interlayer insulating layer 104 is formed to cover the resultant. The second interlayer insulating layer 104 is formed thereon, and is formed of a metal such as tungsten (W) or a metal silicide thereof, and any one of the lower plugs 12. A hard mask layer 108 formed of a bit line 106 connected thereto and a nitride material (SiN) or a composite material thereof (eg, SiON) is formed thereon.

Then, as shown in FIG. 2B, the hard mask layer 108 and the second layer serve as a buffer between the bit line 106 and the barrier insulating film for SAC to be formed later while preventing partial oxidation of the bit line 106. The buffer insulating film 110 is deposited on the entire surface of the interlayer insulating film 104 by silicon oxide or the like.

Subsequently, as shown in FIG. 2C, a resist, which is a flowable material, is additionally embedded as a gap-fill film 112 in the space between the bit lines 106. In this case, the gap fill layer 112 may be formed to a height up to the bit line 106, and may use a fluid material having an etch selectivity with the hard mask layer 108 and the second interlayer insulating layer 104.

Next, as shown in FIG. 2D, the buffer insulating film on the upper surface of the hard mask film 108 is selectively etched and removed so that the buffer insulating film 110a remains only on the side surfaces of the bit lines 106 and the second interlayer insulating film 104. After that, the gapfill film is removed.

Subsequently, as shown in FIG. 2E, the barrier insulating layer 114 may be formed of silicon nitride or the like on the upper surface of the remaining buffer insulating layer 110a and the hard mask layer 108 to prevent etching of the underlying structure during the SAC contact hole etching process. It is formed to a thickness of 30 to 700 microns. In this case, the barrier insulating layer 114 may be replaced with another insulating material having an etching selectivity with respect to the buffer insulating layer 110. A third interlayer insulating film 116 is formed on the entire surface of the resultant product having the barrier insulating film 114.

Then, as shown in FIG. 2F, an etching process using a SAC contact hole mask is performed to etch the third interlayer insulating layer 116 to the second interlayer insulating layer 104 between the bit lines 106 to form a lower plug ( 102 forms a SAC contact hole 118 exposed. Therefore, during the SAC contact hole etching process of the present invention, the buffer insulating film 110a protects the bit line 106 side surface from the etching while the barrier insulating film 114 is etched together with the interlayer insulating films 116 and 104.

Although not shown in the drawings, for example, a doped polysilicon film is deposited on the entire surface on the resultant formed SAC contact hole 118, and then subjected to a chemical mechanical polishing (CMP) process to be buried in the contact hole and A SAC contact electrode of the storage node connected with the junction region is formed.

Meanwhile, in the present invention, the process of allowing the buffer insulating film 110a to remain only on the side surface of the bit line 106 and the upper portion of the second interlayer insulating film 104 is performed by etching the hard mask film 108 without using a gap fill film. The buffer insulating film on the upper side may be selectively etched.

As described above, the present invention does not form the buffer insulating film to the upper surface of the hard mask film, but only to the bit line side surface and the second interlayer insulating film surface, thereby providing a sufficient buffer role in the bit line and barrier insulating film in the subsequent SAC contact hole etching process. While the barrier insulating film on the side of the hard mask film is etched, the bit line is etched to improve the manufacturing yield of the semiconductor memory device having the SAC contact.

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

Claims (8)

In the method of manufacturing a semiconductor memory device, Forming a first interlayer insulating film covering the semiconductor substrate on which the transistor is formed; Forming a conductive layer plug connected to the semiconductor substrate on the first interlayer insulating film; Forming a second interlayer insulating film covering a resultant product in which the conductive layer plug is formed; Forming a bit line vertically connected to any one of the conductive layer plugs and a hard mask stacked thereon on the second interlayer insulating layer; Forming a buffer insulating film on the side of the bit line and on the second interlayer insulating film; Sequentially forming a barrier insulating film and a third interlayer insulating film over the hard mask film and the buffer insulating film; And Etching to the third interlayer insulating film and the second interlayer insulating film between the bit lines to form a self-aligning contact hole exposing any of the conductive layer plugs. Method of manufacturing a memory device. The method of claim 1, wherein the conductive layer plug is formed of doped polysilicon or metal, and the bit line is formed of metal or metal silicide. The method of claim 1, wherein the hard mask layer is formed of a silicon nitride material or a composite insulating material thereof. The method of claim 1, wherein the buffer insulating layer is formed of an oxide material and has a thickness of about 20 μs to about 500 μs. The method of claim 1, wherein the barrier insulating layer is formed of an insulating material having an etch selectivity with respect to the buffer insulating layer, and has a thickness of 30 μm to 700 μm. The method of claim 1, wherein forming a buffer insulating film on the side of the bit line and on the second interlayer insulating film, Depositing a buffer insulating film on the entire surface of the hard mask film and the second interlayer insulating film, and filling a gap fill film in the space between the bit lines, selectively etching the buffer insulating film on the upper surface of the hard mask film, and removing the gap fill film. A method of manufacturing a semiconductor memory device having a self-aligning contact hole. The method of claim 6, wherein the gap fill layer is a fluid material having an etching selectivity with a resist or the hard mask layer and the second interlayer insulating layer. The method of claim 1, wherein forming a buffer insulating film on the side of the bit line and on the second interlayer insulating film, And depositing a buffer insulating film on the entire surface of the hard mask film and the second interlayer insulating film, and selectively etching the buffer insulating film on the upper surface of the hard mask film by etching the entire surface.