KR20010058958A - A method for forming of a semiconductor device - Google Patents
A method for forming of a semiconductor device Download PDFInfo
- Publication number
- KR20010058958A KR20010058958A KR1019990066334A KR19990066334A KR20010058958A KR 20010058958 A KR20010058958 A KR 20010058958A KR 1019990066334 A KR1019990066334 A KR 1019990066334A KR 19990066334 A KR19990066334 A KR 19990066334A KR 20010058958 A KR20010058958 A KR 20010058958A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- insulating film
- interlayer insulating
- film
- semiconductor device
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 91
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000011229 interlayer Substances 0.000 claims abstract description 43
- 238000005530 etching Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 150000004767 nitrides Chemical class 0.000 claims description 36
- 229910021332 silicide Inorganic materials 0.000 claims description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims 1
- 238000002844 melting Methods 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 39
- 238000005498 polishing Methods 0.000 abstract description 2
- 239000000126 substance Substances 0.000 abstract description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 5
- 229910021342 tungsten silicide Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000004151 rapid thermal annealing Methods 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 101100464308 Pithecopus azureus psn15 gene Proteins 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 125000001495 ethyl group Chemical group [H]C([H])([H])C([H])([H])* 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체소자의 형성방법에 관한 것으로, 특히 제1도전층을 형성하고 그 상부에 층간절연막을 형성하는데 있어서, 상기 층간절연막 평탄화공정시 CMP 공정을 사용하는 대신 에치백 ( etch back ) 공정을 실시함으로써 예정된 크기로 예정된 위치에 제1도전층과 제2도전층을 형성할 수 있도록 하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device. In particular, in forming a first conductive layer and forming an interlayer insulating layer thereon, an etch back process is used instead of using a CMP process during the planarization of the interlayer insulating layer. The present invention relates to a technique for forming the first conductive layer and the second conductive layer at a predetermined position with a predetermined size.
기존 공정에서 제1층간절연막을 화학기계연마 ( chemical mechanical polishing, 이하에서 CMP 라 함 ) 하고 랜딩 플러그 콘택 ( landing plug contact, 이하에서 LPC 라 함 ) 마스크 형성공정시 감광막과 층간절연막인 비.피.에스.지. ( boro phospho silicate glass, 이하에서 BPSG 라 함 ) 의 반응을 억제하기 위해 산화막을 얇게 증착한다.In the existing process, the first interlayer insulating film is chemical mechanical polishing (hereinafter referred to as CMP), and the landing plug contact (hereinafter referred to as LPC) is a B.P. S.G. A thin layer of oxide is deposited to inhibit the reaction of boro phospho silicate glass (hereinafter referred to as BPSG).
이후, LPC 마스크 형성공정 및 이를 이용한 식각공정후 랜딩 플러그 폴리 ( landing plug poly, 이하에서 LPP 함 ) 를 증착하고 LPP CMP 공정을 실시한 다음, 제2도전층인 폴리2와 LPP 의 절연방지를 위한 산화막을 얇게 증착하고 폴리2 콘택공정과 폴리2 증착공정을 실시한다.After the LPC mask forming process and the etching process using the same, the landing plug poly (LPP) is deposited and subjected to LPP CMP process, and then an oxide film for preventing insulation between poly2 and LPP, the second conductive layer. Is deposited thinly and then poly 2 contact process and poly 2 deposition process are performed.
한편, 최근에 제2도전층으로 폴리실리콘과 텅스텐 실리사이드를 적층하여 사용함으로써 텅스텐 실리사이드가 축소 ( shrink ) 되는 문제와 패턴이 치밀하지 않은 지역에서 얇은 폴리2 라인이 쉬프트 ( shift ) 되는 문제점을 안고 있다.On the other hand, the recent use of polysilicon and tungsten silicide by laminating polysilicon as the second conductive layer has problems such as shrinkage of tungsten silicide and shift of thin poly2 lines in areas where the pattern is not dense. .
이를 해결하기 위하여 폴리2 와 LPP 를 절연하기 위해 증착하는 산화막의 두께를 높여주거나 산화막 대신 질화막으로 사용하는 것이 시도되고 있다.In order to solve this problem, it is attempted to increase the thickness of the oxide film deposited to insulate the poly2 and the LPP or to use the nitride film instead of the oxide film.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 제1도전층 상부를평탄화시키는 제1층간절연막의 편탕화공정으로 에치백공정으로 실시하여 LPP 의 손상을 방지하고 후속공정으로 형성되는 제2층간절연막인 폴리2 의 축소 및 쉬프트를 방지함으로써 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the second interlayer insulating film to flatten the first conductive layer is etched back to prevent damage to the LPP and to be formed in a subsequent process. It is an object of the present invention to provide a method of forming a semiconductor device which improves the characteristics and reliability of the semiconductor device and thereby enables high integration of the semiconductor device by preventing shrinkage and shifting of the poly 2, an interlayer insulating film.
도 1a 내지 도 1g 는 본 발명의 실시예에 따른 반도체소자의 형성방법을 도시한 단면도.1A to 1G are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
1 : 반도체기판 2 : 제1도전층, 게이트전극, 워드라인1: semiconductor substrate 2: first conductive layer, gate electrode, word line
3 : 캐핑 마스크산화막 4 ; 제1캐핑 마스크질화막3: capping mask oxide film 4; First capping mask nitride film
5 : 제1절연막 6 : 제1층간절연막5: first insulating film 6: first interlayer insulating film
7 : 제2질화막 8 : 랜딩 플러그 폴리7: second nitride film 8: landing plug poly
9 : 플라즈마 테오스 10 : 제2도전층, 비트라인9 plasma theos 10 second conductive layer, bit line
11 : 제2캐핑 마스크질화막 12 : 제3질화막11 second capping mask nitride film 12 third nitride film
13 : 제2층간절연막 14 : 감광막패턴13 second interlayer insulating film 14 photosensitive film pattern
15 : PPP 20 : 제1콘택홀15: PPP 20: 1st contact hole
30 : 제2콘택홀30: 2nd contact hole
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 형성방법은,In order to achieve the above object, a method of forming a semiconductor device according to the present invention,
반도체기판 상부에 제1캐핑 마스크질화막가 구비되는 게이트전극을 형성하고 그 상부를 평탄화시키는 제1층간절연막을 형성하는 공정과,Forming a gate electrode including a first capping mask nitride film on the semiconductor substrate and forming a first interlayer insulating film to planarize the upper portion thereof;
상기 제1층간절연막 상부에 절연막을 형성하고 이들을 건식 및 습식방법으로 콘택식각하여 상기 반도체기판을 노출시키는 제1콘택홀을 형성하는 공정과,Forming a first contact hole for exposing the semiconductor substrate by forming an insulating film on the first interlayer insulating film and contact-etching them by dry and wet methods;
상기 제1콘택홀을 매립하는 랜딩 플러그 폴리 ( LPP ) 를 전체표면상부에 형성하고 상기 절연막을 식각장벽으로 하여 상기 LPP 를 에치백하여 평탄화시키는 공정과,Forming a landing plug poly (LPP) filling the first contact hole on the entire surface, and etching and flattening the LPP by using the insulating film as an etch barrier;
하측에 산화막이 구비되고 상측에 제2캐핑 마스크질화막이 구비되는 비트라인을 형성하는 공정과,Forming a bit line having an oxide film on the lower side and a second capping mask nitride film on the upper side;
전체표면상부를 평탄화시키는 제2층간절연막을 형성하는 공정과,Forming a second interlayer insulating film to planarize the entire upper surface;
상기 제2층간절연막을 건식 및 습식방법으로 식각하여 상기 LPP 를 노출시키는 제2콘택홀을 형성하는 공정과,Forming a second contact hole exposing the LPP by etching the second interlayer insulating film by dry and wet methods;
상기 제2콘택홀을 매립하며 상기 제1콘택플러그에 접속되는 폴리3 플러그 폴리 ( PPP ) 를 형성하는 공정과,Filling the second contact hole and forming a poly3 plug poly (PPP) connected to the first contact plug;
상기 PPP 를 CMP 하여 평탄화시켜 제2콘택플러그를 형성하는 공정을 포함하는 것을 특징으로한다.And CMP to planarize the PPP to form a second contact plug.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1g 는 본 발명의 실시예에 따른 반도체소자의 형성방법을 도시한 단면도1A to 1G are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.
먼저, 반도체기판(1)의 소자분리영역에 활성영역을 정의하는 소자분리막(도시안됨)을 형성한다.First, an isolation layer (not shown) defining an active region is formed in the isolation region of the semiconductor substrate 1.
그리고, 상기 반도체기판(1) 상부에 게이트전극(2)을 형성한다. 이때, 상기 게이트전극(2)은 게이트전극(2)은 폴리실리콘과 텅스텐 실리사이드의 적층구조로 형성한다.The gate electrode 2 is formed on the semiconductor substrate 1. In this case, the gate electrode 2 is formed of a stacked structure of the polysilicon and tungsten silicide.
그 다음, 상기 게이트전극(2) 상부에 캐핑 마스크산화막 ( capping mask oxide ) (3)을 형성한다.Next, a capping mask oxide 3 is formed on the gate electrode 2.
그리고, 상기 캐핑 마스크산화막(3) 상부에 캐핑 마스크질화막 ( capping mask nitride ) (4)을 형성한다.A capping mask nitride layer 4 is formed on the capping mask oxide layer 3.
그리고, 게이트전극 마스크(도시안됨)를 이용한 사진식각공정으로 상기 게이트전극(2), 캐핑 마스크산화막(3), 캐핑 마스크질화막(4)의 적층구조를 패터닝한다.The stacked structure of the gate electrode 2, the capping mask oxide film 3, and the capping mask nitride film 4 is patterned by a photolithography process using a gate electrode mask (not shown).
그리고, 상기 패터닝된 적층구조 측벽에 제1질화막(5) 스페이서를 형성한다.A spacer of the first nitride film 5 is formed on the sidewall of the patterned stacked structure.
이때, 상기 제1질화막(5) 스페이서는 전체표면상부에 제1질화막(5)을 일정두께 형성하고 이를 증착된 두께 만큼 이방성식각하여 형성한다.In this case, the first nitride film 5 spacer is formed by forming a first thickness of the first nitride film 5 on the entire surface and anisotropically etched by the deposited thickness.
그 다음, 전체표면상부에 제1층간절연막(6)을 형성한다.Then, the first interlayer insulating film 6 is formed over the entire surface.
이때, 상기 제1층간절연막(6)은 BPSG 와 같이 유동성이 우수한 절연물질로 형성한다.In this case, the first interlayer insulating film 6 is formed of an insulating material having excellent fluidity, such as BPSG.
그 다음, 상기 제1층간절연막(6)을 CMP 공정으로 평탄화식각한다.Next, the first interlayer insulating film 6 is planarized by a CMP process.
이때, 상기 CMP 공정은 상기 제1층간절연막(6)인 BPSG 를 0 ∼ 2000 Å 정도만 남겨 후속공정으로 진행되는 SAC 공정을 용이하게 한다. (도 1a)At this time, the CMP process leaves the BPSG, which is the first interlayer insulating film 6, at about 0 to 2000 kPa, thereby facilitating the SAC process proceeding to the subsequent process. (FIG. 1A)
그 다음, 상기 제1층간절연막(6) 상부에 제2질화막(7)을 200 ∼ 1000 Å 정도로 형성한다.Next, a second nitride film 7 is formed on the first interlayer insulating film 6 at about 200 to 1000 1000.
여기서, 상기 제2질화막(7)은 후속공정으로 제3도전층인 폴리3 콘택공정시 습식식각으로 실시하면 제1층간절연막인 BPSG 가 손실되는 현상을 억제하기 위한 것으로, 후속공정으로 형성되는 LPP 의 평탄화공정인 에치백공정시 그대로 남아있어 제1층간절연막(6)인 BPSG 의 리플로우 ( reflow ) 에 의한 폴리2 쉬프트 및 축소 문제를 해결할 수 있다.Here, the second nitride film 7 is to prevent the loss of the BPSG, which is the first interlayer insulating film, when the wet etching is performed during the poly3 contact process as the third conductive layer in a subsequent process. It remains intact during the etch back process, which is a planarization process, to solve the poly2 shift and shrinkage problem caused by the reflow of the BPSG, which is the first interlayer insulating film 6.
그 다음, 랜딩 플러그 콘택 ( LPC ) 공정을 자기정렬적으로 실시하여 상기 제2질화막(7)과 제1층간절연막(6)을 식각함으로써 상기 반도체기판(1)을 노출시키는 제1콘택홀(20)을 형성한다.Next, a first contact hole 20 exposing the semiconductor substrate 1 by etching the second nitride film 7 and the first interlayer insulating film 6 by performing a self-aligned landing plug contact (LPC) process. ).
그리고, 상기 제1콘택홀(20)을 매립하며 상기 반도체기판(1)에 접속되는 랜딩 플러그 폴리 ( LPP ) (8)를 전체표면상부에 형성한다. (도 1b)Then, the first contact hole 20 is filled and a landing plug poly (LPP) 8 connected to the semiconductor substrate 1 is formed on the entire surface. (FIG. 1B)
그 다음, 상기 제2질화막(7)을 노출시킬때까지 상기 LPP (8) 를 에치백하여 평탄화시킴으로써 상기 LPP (8)로 제1 콘택플러그를 형성한다. 이때, 상기 에치백공정은 상기 제2질화막(7)을 식각장벽으로 하여 실시한다. 그리고, 상기 제1콘택플러그는 제2도전층인 비트라인과 제3도전층인 저장전극의 콘택플러그로 사용된다. (도 1c)Then, the first contact plug is formed with the LPP 8 by etching and flattening the LPP 8 until the second nitride film 7 is exposed. In this case, the etch back process is performed using the second nitride film 7 as an etch barrier. The first contact plug is used as a contact plug between a bit line serving as a second conductive layer and a storage electrode serving as a third conductive layer. (FIG. 1C)
그리고, 상기 전체표면상부에 플라즈마 테오스 ( PE-TEOS ) 막(9)을 형성한다. 이때, 상기 플라즈마 테오스막(9)은 후속공정으로 형성된 제2도전층과 상기 제1콘택플러그가 쇼트되는 현상을 방지하기 위한 것이다.Then, a plasma teos (PE-TEOS) film 9 is formed on the entire surface. At this time, the plasma theos film 9 is intended to prevent a phenomenon in which the second conductive layer and the first contact plug formed in a subsequent process are short-circuited.
이때, 상기 플라즈마 테오스막(9)은 언도프드 산화막으로서 고온산화막 ( high temperature oxide, 이하에서 HTO라 함 ), 저압플라즈마 테오스 ( low plasma - Tetra ethyl ortho silcate, 이하에서 LP-TEOS 라 함 ) 등으로 대신 형성할 수 있다.In this case, the plasma theos film 9 is an undoped oxide film, which is referred to as high temperature oxide (hereinafter referred to as HTO), low pressure plasma theos (low plasma-tetra ethyl ortho silcate, hereinafter referred to as LP-TEOS), and the like. Can be formed instead.
그 다음, 상기 플라즈마 테오스막(9) 상부에 제2도전층(10)을 형성한다. 이때, 상기 제2도전층(10)은 폴리실리콘과 텅스텐 실리사이드의 적층구조로 형성한다.Next, a second conductive layer 10 is formed on the plasma theos film 9. In this case, the second conductive layer 10 is formed of a laminated structure of polysilicon and tungsten silicide.
그리고, 상기 제2도전층(10) 상부에 제2캐핑 마스크질화막(11)을 형성한다.In addition, a second capping mask nitride layer 11 is formed on the second conductive layer 10.
이때, 상기 제2캐핑 마스크질화막(11)은 플라즈마-질화막, 실리콘산화질화막 또는 실리콘 리치 실리콘산화질화막 ( Si-rich SiON ) 으로 형성한다.In this case, the second capping mask nitride layer 11 is formed of a plasma-nitride layer, a silicon oxynitride layer, or a silicon rich silicon oxynitride layer (Si-rich SiON).
그 다음, 비트라인 마스크(도시안됨)를 이용한 사진식각공정으로 패터닝한다.Then, patterning is performed by a photolithography process using a bit line mask (not shown).
그 다음, 상기 패터닝된 플라즈마 테오스막(9), 제2도전층(10) 및 제1캐핑 마스크질화막(11)의 적층구조 측벽에 제3질화막(12) 스페이서를 형성한다.Next, a third nitride layer 12 spacer is formed on sidewalls of the laminated structure of the patterned plasma theos layer 9, the second conductive layer 10, and the first capping mask nitride layer 11.
이때, 상기 제3질화막(12) 스페이서는 전체표면상부에 제3질화막(12)을 일정두께 형성하고 이를 이방성식각하여 형성한다.In this case, the third nitride film 12 spacer is formed by forming a third thickness of the third nitride film 12 on the entire surface and anisotropically etched it.
그 다음, 전체표면상부에 제2층간절연막(13)을 일정두께 형성한다. 이때, 상기 제2층간절연막(13)은 BPSG 와 같이 유동성이 우수한 절연물질로 형성한다.Then, a second interlayer insulating film 13 is formed on the entire surface at a constant thickness. In this case, the second interlayer insulating layer 13 is formed of an insulating material having excellent fluidity, such as BPSG.
그리고, 상기 제2층간절연막(13)을 CMP 공정으로 평탄화식각한다.The second interlayer insulating film 13 is planarized by a CMP process.
이때, 상기 CMP 공정은 상기 제2층간절연막(13)이 상기 제2캐핑 마스크질화막(11)의 상부로 500 ∼ 3000 Å 정도 남도록 실시한다.In this case, the CMP process may be performed such that the second interlayer insulating film 13 remains about 500 to 3000 m 3 above the second capping mask nitride film 11.
그 다음, 상기 제2층간절연막(13) 상부에 감광막패턴(14)을 형성한다. 이때, 상기 감광막패턴(14)은 상기 제1콘택플러그, 즉 LPP (8)를 노출시킬 수 있도록 저장전극 콘택마스크를 이용한 노광 및 현상공정으로 형성한다.Next, a photosensitive film pattern 14 is formed on the second interlayer insulating film 13. In this case, the photoresist pattern 14 is formed by an exposure and development process using a storage electrode contact mask to expose the first contact plug, that is, the LPP 8.
그리고, 상기 감광막패턴(14)은 패터닝후 100 ∼ 150 ℃ 의 온도에서 열을 가하여 리플로우시켜 예정된 제3도전층의 콘택홀 보다 작은 크기로 형성한다. (도 1d)After the patterning, the photoresist pattern 14 is reflowed by applying heat at a temperature of 100 to 150 ° C. to form a smaller size than the predetermined contact hole of the third conductive layer. (FIG. 1D)
그 다음, 상기 감광막패턴(14)을 마스크로하여 상기 제2층간절연막(13)을 일정두께 건식식각한다. 이때, 상기 건식식각공정은 상기 제2층간절연막(13)이 0 ∼ 3000 Å 정도 남도록 실시한다.Next, the second interlayer insulating film 13 is dry-etched to a predetermined thickness using the photosensitive film pattern 14 as a mask. In this case, the dry etching process may be performed such that the second interlayer insulating film 13 is left in the range of about 0 to about 3000 kPa.
여기서, 상기 감광막패턴(14)의 패턴 크기는 실제 저장전극 콘택마스크보다 작게 형성하여 후속공정으로 형성되는 제3도전층인 저장전극과 제2도전층인 비트라인의 쇼트를 방지할 수 있도록 한다. 아울러, 저장전극 간의 브릿지 ( bridge ) 문제를 방지할 수도 있다.The pattern size of the photoresist pattern 14 may be smaller than the actual storage electrode contact mask to prevent a short between the storage electrode, which is the third conductive layer, and the bit line, which is the second conductive layer, formed in a subsequent process. In addition, it is possible to prevent a bridge problem between the storage electrodes.
그 다음, 상기 감광막패턴(14)을 제거한다. (도 1e)Next, the photoresist pattern 14 is removed. (FIG. 1E)
그 다음, 상기 습식식각공정으로 상기 LPP (8)를 노출시키는 제2콘택홀(30)을 형성한다.Next, a second contact hole 30 exposing the LPP 8 is formed by the wet etching process.
이때, 상기 습식식각공정은, 등방성으로 식각공정이 이루어지므로 제2콘택홀(30)의 펴면으로도 크기가 크게 증가하게 되지만, X 축 방향으로 스페이스 간격이 충분하여 브릿지의 염려가 업고 Y 축 방향으로는 스페이스 마진이 부족하긴 하지만, 이후 공정에서 제2캐핑 마스크질화막(11)을 장벽 역할을 하여 CMP 공정시 저장전극 콘택 간의 절연특성과는 무관하다.At this time, the wet etching process is an isotropic etching process, so the size of the second contact hole 30 is greatly increased, but there is enough space in the X-axis direction, so there is no concern about the bridge and the Y-axis direction. Although the space margin is insufficient, the second capping mask nitride layer 11 serves as a barrier in a subsequent process, and is not related to the insulation characteristics between the storage electrode contacts during the CMP process.
여기서, 상기한 건식 및 습식식각공정에 의한 제2콘택홀(30)은 상측은 크고 하측은 작은 임계면적 ( critical dimension ) 을 갖는 크기로 형성되어 후속공정인 상기 제2콘택홀(30)의 매립공정을 용이하게 한다.Here, the second contact hole 30 by the dry and wet etching process is formed to a size having a critical dimension of the upper side is large and the lower side is a buried of the second contact hole 30 is a subsequent process. To facilitate the process.
그리고, 상기 습식식각공정은 HF 나 BOE 용액과 같은 산화막 식각공정으로 실시한다.The wet etching process is performed by an oxide film etching process such as HF or BOE solution.
그 다음, 상기 LPP(8) 에 접속되도록 상기 제2콘택홀(30)을 매립하는 폴리3 플러그 폴리 ( poly3 plug poly, 이하에서 PPP 라 함 ) (15)를 전체표면상부에 형성한다. (도 1f)Next, a poly3 plug poly 15 (hereinafter referred to as PPP) 15 which fills the second contact hole 30 so as to be connected to the LPP 8 is formed on the entire surface. (FIG. 1F)
그리고, 상기 제2캐핑 마스크질화막(11)을 식각장벽으로 하여 상기 PPP(15)를 CMP 하되, 상기 제2캐핑 마스크질화막(11)이 100 ∼ 1500 Å 정도 식각되도록 실시함으로써 제2콘택플러그를 형성한다.The PPP 15 is CMP with the second capping mask nitride film 11 as an etch barrier, and the second contact plug is formed by etching the second capping mask nitride film 11 at about 100-1500 mm 3. do.
이때, 상기 제2콘택플러그는 후속공정으로 저장전극에 접속되는 저장전극 콘택플러그로 사용된다.In this case, the second contact plug is used as a storage electrode contact plug connected to the storage electrode in a subsequent process.
후속공정으로 상기 제2콘택플러그에 접속되는 제3도전층(도시안됨)으로 저장전극을 형성한다. (도 1g)In a subsequent process, a storage electrode is formed of a third conductive layer (not shown) connected to the second contact plug. (Fig. 1g)
본 발명의 다른 실시예는 상기 도 1c 의 공정후 SAS ( self alinged silicide ) 공정으로 상기 LPP(8) 상부에 실리사이드를 형성함으로써 후속공정으로 상기 LPP(8)에 접속되는 제2콘택플러그의 콘택저항을 감소시킬 수 있다.Another embodiment of the present invention is a contact resistance of the second contact plug connected to the LPP (8) in a subsequent process by forming a silicide on the LPP (8) by the SAS (self alinged silicide) process after the process of Figure 1c Can be reduced.
여기서, 상기 실리사이드는 Ti, Co, Ni 등과 같은 물질을 이용하여 형성한다.Here, the silicide is formed using a material such as Ti, Co, Ni, and the like.
그리고, 상기 실리사이드 형성공정은 600 ∼ 900 ℃ 의 온도에서 RTA ( rapid thermal annealing ) 공정으로 형성한다.In addition, the silicide forming process is formed by a rapid thermal annealing (RTA) process at a temperature of 600 ~ 900 ℃.
또는, 600 ∼ 800 ℃ 의 온도에서 RTA 공정으로 형성하고 표면을 습식세정한 다음, 700 ∼ 900 ℃ 의 온도에서 RTA 하여 실리사이드를 형성할 수도 있다.Alternatively, the surface may be formed by an RTA process at a temperature of 600 to 800 ° C., the surface may be wet-washed, and then RTA may be formed at a temperature of 700 to 900 ° C. to form silicide.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 형성방법은, 제1층간절연막 상부에 질화막을 형성하고 이를 식각장벽으로 하여 후속공정으로 형성되는 LPP 를 CMP 공정 대신 에치백공정으로 평탄화식각함으로써 상기 제1층간절연막에 구비되는 워드라인, 즉 게이트전극 상부에 형성되는 상기 제1층간절연막의 두께를 낮출 수 있어 반도체소자의 고집적화를 가능하게 하는 효과를 제공한다.As described above, the method of forming a semiconductor device according to the present invention includes forming a nitride film on the first interlayer insulating film and etching the LPP, which is formed in a subsequent process, as an etch barrier by planarization etching instead of the CMP process. The thickness of the word line provided on the interlayer insulating film, that is, the first interlayer insulating film formed on the gate electrode can be reduced, thereby providing an effect of enabling high integration of the semiconductor device.
또한, 제2도전층인 비트라인을 산화막, 폴리실리콘, 텅스텐 실리사이드 및 캐핑 마스크질화막의 적층구조로 형성하여 상기 비트라인과 제1콘택플러그와의 절연특성을 향상시키고, 후속평탄화식각공정시 상기 캐핑 마스크질화막 식각장벽으로 사용되어 상기 비트라인의 손상을 방지할 수 있는 효과를 제공한다.In addition, the bit line, which is a second conductive layer, may be formed as a stacked structure of an oxide film, polysilicon, tungsten silicide, and a capping mask nitride film to improve insulation characteristics between the bit line and the first contact plug, and to perform the capping during the subsequent planarization etching process. It is used as a mask nitride film etch barrier to provide the effect of preventing damage to the bit line.
따라서, 상기한 효과들로 인하여 반도체소자의 두께를 감소시킬 수 있어 반도체소자의 고집적화를 가능하게 하는 효과를 제공한다.Therefore, the thickness of the semiconductor device can be reduced due to the above effects, thereby providing an effect of enabling high integration of the semiconductor device.
Claims (14)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990066334A KR20010058958A (en) | 1999-12-30 | 1999-12-30 | A method for forming of a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990066334A KR20010058958A (en) | 1999-12-30 | 1999-12-30 | A method for forming of a semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20010058958A true KR20010058958A (en) | 2001-07-06 |
Family
ID=19633473
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990066334A KR20010058958A (en) | 1999-12-30 | 1999-12-30 | A method for forming of a semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20010058958A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100781547B1 (en) * | 2006-10-20 | 2007-12-03 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
-
1999
- 1999-12-30 KR KR1019990066334A patent/KR20010058958A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100781547B1 (en) * | 2006-10-20 | 2007-12-03 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
| US7833902B2 (en) | 2006-10-20 | 2010-11-16 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100322536B1 (en) | Forming method of a polysilicon contact plug using etch-back and manufacturing method of a semiconductor device using the same | |
| KR100846099B1 (en) | Method of manufacturing semiconductor device including recessed channel transistor | |
| US20020001889A1 (en) | Methods for forming conductive contact body for integrated circuits using dummy dielectric layer | |
| JP4860189B2 (en) | Method for forming metal wiring of semiconductor memory device | |
| KR100505450B1 (en) | Method for fabricating semiconductor device using damascene process | |
| TW200818409A (en) | Method for fabricating storage node contact in semiconductor device | |
| JP2008166750A (en) | Manufacturing method of semiconductor device including landing plug contact | |
| KR100507862B1 (en) | Method for fabricating semiconductor device | |
| KR20050068061A (en) | Method of forming interconnection lines in a semiconductor device | |
| KR20010058958A (en) | A method for forming of a semiconductor device | |
| KR100961193B1 (en) | Method for forming the semiconductor memory device having a self-aligned contact hole | |
| KR100721548B1 (en) | Method for forming storage node of capacitor in semiconductor device | |
| KR101204919B1 (en) | Semiconductor device and method for fabricating the same | |
| KR20070002325A (en) | Method for manufacturing a semiconductor device | |
| KR100333541B1 (en) | Manufacturing method of semiconductor device | |
| KR100682166B1 (en) | Manufacturing method for semiconductor device | |
| KR20050024977A (en) | Semicondcutor device having self-alinged contact and method of the same | |
| KR100772077B1 (en) | A method for forming contact hole of semiconductor device | |
| KR100310543B1 (en) | Method of forming a semiconductor device | |
| KR100369355B1 (en) | Method for fabricating highly integrated semiconductor device | |
| KR19980068806A (en) | Method for forming self-aligned contacts in memory devices | |
| KR20060002182A (en) | A method for forming a semiconductor device | |
| KR100327663B1 (en) | Forming method for inter layer oxide of semiconductor device | |
| KR20010004929A (en) | Method of forming polysilicon plug for semiconductor device | |
| KR20050066192A (en) | A method for forming a contact of a semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |