KR20010004929A - Method of forming polysilicon plug for semiconductor device - Google Patents

Method of forming polysilicon plug for semiconductor device Download PDF

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Publication number
KR20010004929A
KR20010004929A KR1019990025697A KR19990025697A KR20010004929A KR 20010004929 A KR20010004929 A KR 20010004929A KR 1019990025697 A KR1019990025697 A KR 1019990025697A KR 19990025697 A KR19990025697 A KR 19990025697A KR 20010004929 A KR20010004929 A KR 20010004929A
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South Korea
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film
insulating film
substrate
forming
polysilicon
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KR1019990025697A
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Korean (ko)
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KR100345069B1 (en
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배경진
김성식
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김영환
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Abstract

PURPOSE: A method for forming a polysilicon plug of a semiconductor device is provided to enhance an element reliability by easily controlling CMP process in forming a polysilicon plug. CONSTITUTION: A word line is formed on a semiconductor substrate(10). A hard mask(13) and ARC(anti-reflective coating) layer are sequentially stacked in the word line. An insulation spacer is formed on sidewalls of the word line, hard mask, and ARC layer. An interfacial insulating layer is formed on the substrate. The interfacial insulating layer is fully etched to expose a surface of the hard mask, thereby smoothing a surface of the substrate. An insulating layer pattern is formed on the hard mask. The second insulating layer is removed, thereby forming a self-aligned contact hole which exposes a substrate between the insulating layer spacers. A polysilicon layer(11) is formed on the substrate, and is buried in the contact hole. The polysilicon layer is fully etched to expose a surface of the insulating layer pattern, thereby forming a polysilicon plug(19A).

Description

반도체 소자의 폴리실리콘 플러그 형성방법{Method of forming polysilicon plug for semiconductor device}Method of forming polysilicon plug for semiconductor device

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 반도체 소자의 폴리실리콘 플러그 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a polysilicon plug of a semiconductor device.

일반적으로, 디램(DRAM; Dynamic Random Access Memory)에서 비트라인의 형성시 콘택에서의 전기적 특성을 향상시키기 위하여 폴리실리콘 플러그를 이용한다. 이러한, 폴리실리콘 플러그를 형성하기 위하여, 2번의 CMP 공정이 진행된다. 즉, 폴리실리콘 플러그의 형성전에 기판 표면을 평탄화시키기 위하여 층간절연막으로서의 산화막에 대하여 제 1 CMP를 진행하고, 폴리실리콘막에 대하여 제 2 CMP를 진행한다.In general, polysilicon plugs are used to improve electrical characteristics at the contact when forming bit lines in a dynamic random access memory (DRAM). In order to form such a polysilicon plug, two CMP processes are performed. That is, in order to planarize the substrate surface before forming the polysilicon plug, the first CMP is performed on the oxide film as the interlayer insulating film, and the second CMP is performed on the polysilicon film.

그러나, 상기한 2번의 CMP 공정시 공정제어가 용이하지 못하여 심한 변동격차가 발생되어, 웨이퍼 및 필드 간 차이가 심해져서 후속 공정에 악영향을 미치게 됨으로써 소자의 신뢰성이 저하되는 문제가 있다.However, in the above two CMP processes, the process control is not easy and a serious fluctuation gap occurs, and the difference between the wafer and the field is increased, which adversely affects subsequent processes, thereby deteriorating the reliability of the device.

따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로서, 폴리실리콘 플러그의 형성에 따른 CMP 공정을 용이하게 제어함으로써 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 폴리실리콘 플러그 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention is to solve the above-mentioned problems, and to provide a method for forming a polysilicon plug of a semiconductor device that can improve the reliability of the device by easily controlling the CMP process according to the formation of the polysilicon plug. There is a purpose.

도 1a 내지 도 1e는 본 발명의 실시예에 따른 반도체 소자의 폴리실리콘 플러그 형성방법을 설명하기 위한 단면도.1A to 1E are cross-sectional views illustrating a method of forming a polysilicon plug of a semiconductor device according to an embodiment of the present invention.

도 2a 내지 도 2e는 본 발명의 다른 실시예에 따른 반도체 소자의 폴리실리콘 플러그 형성방법을 설명하기 위한 단면도.2A to 2E are cross-sectional views illustrating a method of forming a polysilicon plug of a semiconductor device according to another exemplary embodiment of the present invention.

(도면의 주요부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)

10, 20 : 반도체 기판 11, 21 : 폴리실리콘막10, 20: semiconductor substrate 11, 21: polysilicon film

12, 22 : 금속 실리사이드막 13, 23 : 하드 마스크12, 22: metal silicide film 13, 23: hard mask

14, 24 : ARC막 15, 25 : 스페이서14, 24: ARC film 15, 25: spacer

16, 26 : 층간절연막 17A : 질화막 패턴16, 26 interlayer insulating film 17A nitride film pattern

18, 27 : 포토레지스트막 19A, 28A : 폴리실리콘 플러그18, 27: photoresist film 19A, 28A: polysilicon plug

상기한 본 발명의 목적을 달성하기 위하여, 본 발명의 실시예에 따라, 상부에 하드 마스크 및 ARC이 순차적으로 적층된 워드라인이 형성된 반도체 기판을 제공하고, 워드라인, 하드 마스크 및 ARC막의 측벽에 절연막 스페이서를 형성한다. 그런 다음, 기판 전면에 층간절연막을 형성하고, 하드 마스크의 표면이 노출되도록 상기 층간절연막을 전면식각하여 기판 표면을 평탄화시킨 후, 하드 마스크 상에 절연막 패턴을 형성한다. 그리고 나서, 제 2 절연막을 제거하여 상기 절연막 스페이서 사이의 기판을 노출시키는 자기정렬 콘택홀을 형성하고, 콘택홀에 매립되도록 기판 전면에 폴리실리콘막을 형성한 다음, 절연막 패턴의 표면이 노출되도록 상기 폴리실리콘막을 전면식각하여 폴리실리콘 플러그를 형성한다.In order to achieve the above object of the present invention, in accordance with an embodiment of the present invention, there is provided a semiconductor substrate having a word line formed by sequentially stacking a hard mask and ARC, and on the sidewalls of the word line, hard mask and ARC film An insulating film spacer is formed. Then, an interlayer insulating film is formed on the entire surface of the substrate, and the surface of the interlayer insulating film is etched to expose the surface of the hard mask to planarize the substrate surface, and then an insulating film pattern is formed on the hard mask. Then, a self-aligned contact hole is formed to remove the second insulating film to expose the substrate between the insulating film spacers, a polysilicon film is formed on the entire surface of the substrate to be filled in the contact hole, and then the poly is exposed to expose the surface of the insulating film pattern. The silicon film is etched entirely to form a polysilicon plug.

또한, 층간절연막 및 폴리실리콘막의 전면식각은 화학적기계적연마로 진행하고, 절연막 스페이서 및 절연막 패턴은 질화막으로 형성하고, 층간절연막은 산화막으로 형성한다.Further, the entire surface etching of the interlayer insulating film and the polysilicon film is performed by chemical mechanical polishing, the insulating film spacer and the insulating film pattern are formed of a nitride film, and the interlayer insulating film is formed of an oxide film.

또한, 본 발명의 다른 실시예에 따라, 상부에 하드 마스크 및 ARC이 순차적으로 적층된 워드라인이 형성된 반도체 기판을 제공하고, 워드라인, 하드 마스크 및 ARC막의 측벽에 절연막 스페이서를 형성한 다음, 기판 전면에 층간절연막을 형성한다. 그런 다음, ARC막의 표면이 노출되도록 층간절연막을 전면식각하여 기판 표면을 평탄화시키고, 층간절연막을 제거하여 절연막 스페이서 사이의 기판을 노출시키는 자기정렬 콘택홀을 형성한 후, 콘택홀에 매립되도록 기판 전면에 폴리실리콘막을 형성한다. 그리고 나서, ARC막의 표면이 노출되도록 상기 폴리실리콘막을 전면식각하여 폴리실리콘 플러그를 형성한다.In addition, according to another embodiment of the present invention, there is provided a semiconductor substrate having a word line formed by sequentially stacking a hard mask and ARC on top, forming an insulating film spacer on the sidewalls of the word line, hard mask and ARC film, and then An interlayer insulating film is formed on the entire surface. Then, the surface of the ARC film is etched to expose the surface of the ARC film to planarize the surface of the substrate, and the interlayer insulating film is removed to form a self-aligning contact hole exposing the substrate between the insulating film spacers, and then the front surface of the substrate is embedded in the contact hole. A polysilicon film is formed on the film. Then, the polysilicon film is etched entirely so that the surface of the ARC film is exposed to form a polysilicon plug.

또한, 층간절연막 및 상기 폴리실리콘막의 전면식각은 화학적기계적연마로 진행하고, 절연막 스페이서는 질화막으로 형성하고 층간절연막은 산화막으로 형성한다.In addition, the front surface etching of the interlayer insulating film and the polysilicon film is performed by chemical mechanical polishing, the insulating film spacer is formed of a nitride film, and the interlayer insulating film is formed of an oxide film.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

도 1a 내지 도 1e는 본 발명의 실시예에 따른 반도체 소자의 폴리실리콘 플러그 형성방법을 설명하기 위한 단면도이다.1A to 1E are cross-sectional views illustrating a method of forming a polysilicon plug of a semiconductor device according to an exemplary embodiment of the present invention.

도 1a를 참조하면, 도핑된 폴리실리콘막(11)과 금속 실리사이드막(12)의 적층구조로 이루어지고, 그의 상부에 절연막의 하드 마스크(13) 및 ARC(Anti-Reflective Coating)막(14)이 순차적으로 적층된 워드라인(100)이 형성된 반도체 기판(10) 상에 제 1 질화막을 증착하고 블랭킷 식각하여 워드라인(100), 하드 마스크(13) 및 ARC막(14)의 측벽에 스페이서(15)를 형성한다. 그런 다음, 기판 전면에 층간절연막으로서 산화막(16)을 형성하고, 하드 마스크(13)의 표면이 노출되도록 CMP로 산화막(16)을 전면식각하여 도 1b에 도시된 바와 같이, 기판 표면을 평탄화시킨다.Referring to FIG. 1A, a doped polysilicon layer 11 and a metal silicide layer 12 are laminated, and a hard mask 13 and an anti-reflective coating (ARC) layer 14 of an insulating layer are disposed thereon. The first nitride layer is deposited and blanket-etched on the semiconductor substrate 10 on which the sequentially stacked word lines 100 are formed, and spacers are formed on sidewalls of the word line 100, the hard mask 13, and the ARC layer 14. 15). Then, an oxide film 16 is formed as an interlayer insulating film on the entire surface of the substrate, and the entire surface of the hard mask 13 is etched with CMP to expose the surface of the hard mask 13 to planarize the substrate surface as shown in FIG. 1B. .

도 1c를 참조하면, 평탄화된 기판 전면에 제 2 질화막(17)을 증착하고, 하드 마스크(13) 상의 제 2 질화막(17) 상부에 포토레지스트 패턴(18)을 형성한다. 도 1d를 참조하면, 포토레지스트 패턴(18)을 식각 마스크로하여 제 2 질화막(17)을 식각하여, 하드 마스크(13) 상에 질화막 패턴(17A)을 형성한다. 그런 다음, 공지된 방법으로 포토레지스트 패턴(18)을 제거하고, 질화막 패턴(17A) 및 질화막으로 이루어진 스페이서(15)를 식각 마스크로하여 습식식각으로 산화막(16)을 제거하여, 스페이서(15) 사이의 기판을 노출시키는 자기정렬 콘택홀을 형성한다.Referring to FIG. 1C, a second nitride film 17 is deposited on the entire planarized substrate, and a photoresist pattern 18 is formed on the second nitride film 17 on the hard mask 13. Referring to FIG. 1D, the second nitride film 17 is etched using the photoresist pattern 18 as an etching mask to form the nitride film pattern 17A on the hard mask 13. Then, the photoresist pattern 18 is removed by a known method, and the oxide film 16 is removed by wet etching using the spacer 15 made of the nitride film pattern 17A and the nitride film as an etching mask. A self-aligned contact hole is formed to expose the substrate therebetween.

그리고 나서, 상기 콘택홀에 매립되도록 기판 전면에 폴리실리콘막(19)을 증착하고, 질화막 패턴(17A)의 표면이 노출되도록 폴리실리콘막(19)을 CMP로 전면식각하여, 도 1e에 도시된 바와 같이, 폴리실리콘 플러그(19A)를 형성한다.Then, a polysilicon film 19 is deposited on the entire surface of the substrate so as to be filled in the contact hole, and the polysilicon film 19 is etched with CMP so that the surface of the nitride film pattern 17A is exposed. As described above, the polysilicon plug 19A is formed.

상기 실시예에 의하면, 산화막(16) 및 폴리실리콘막(19)에 대한 CMP를 하드 마스크(13) 및 질화막 패턴(17A)을 식각 정지층으로하여 각각 진행하므로, CMP가 용이해진다.According to the above embodiment, the CMP for the oxide film 16 and the polysilicon film 19 proceeds with the hard mask 13 and the nitride film pattern 17A as the etch stop layer, respectively, so that the CMP becomes easy.

또한, 상기한 방법과는 달리 별도의 질화막 패턴을 이용하는 것 없이 ARC막을 식각 정지층으로 하여 산화막 및 폴리실리콘막에 대한 CMP를 진행할 수 있다.In addition, unlike the above method, CMPs for the oxide film and the polysilicon film may be performed using the ARC film as an etch stop layer without using a separate nitride film pattern.

즉, 도 2a 내지 도 2e는 본 발명의 다른 실시예에 따른 반도체 소자의 폴리실리콘 플러그 형성방법을 설명하기 위한 단면도이다.2A to 2E are cross-sectional views illustrating a method of forming a polysilicon plug of a semiconductor device according to another exemplary embodiment of the present invention.

도 2a를 참조하면, 도핑된 폴리실리콘막(21)과 금속 실리사이드막(22)의 적층구조로 이루어지고, 그의 상부에 절연막의 하드 마스크(23) 및 ARC(Anti-Reflective Coating)막(24)이 순차적으로 적층된 워드라인(200)이 형성된 반도체 기판(20) 상에 제 1 질화막을 증착하고 블랭킷 식각하여 워드라인(200), 하드 마스크(23) 및 ARC막(24)의 측벽에 스페이서(25)를 형성한다. 그런 다음, 기판 전면에 층간절연막으로서 산화막(26)을 형성하고, ARC막(24)의 표면이 노출되도록 CMP로 산화막(26)을 전면식각하여, 도 2b에 도시된 바와 같이, 기판 표면을 평탄화시킨다.Referring to FIG. 2A, a doped polysilicon film 21 and a metal silicide film 22 are laminated, and a hard mask 23 and an anti-reflective coating (ARC) film 24 of an insulating film are disposed thereon. The first nitride layer is deposited on the semiconductor substrate 20 on which the sequentially stacked word lines 200 are formed and blanket-etched to form spacers on sidewalls of the word line 200, the hard mask 23, and the ARC layer 24. 25). Then, an oxide film 26 is formed as an interlayer insulating film on the entire surface of the substrate, and the oxide film 26 is etched by CMP so that the surface of the ARC film 24 is exposed, thereby flattening the substrate surface as shown in FIG. 2B. Let's do it.

도 2c를 참조하면, ARC막(24) 상에 포토레지스트 패턴(27)을 형성하고, 포토레지스트 패턴(27)을 식각 마스크로하여 산화막(26)을 제거하여 스페이서(25) 사이의 기판을 노출시키는 자기정렬 콘택홀을 형성한다. 그리고 나서, 공지된 방법으로 포토레지스트 패턴을 제거한 후, 도 2d에 도시된 바와 같이, 상기 콘택홀에 매립되도록 기판 전면에 폴리실리콘막(28)을 증착한다. 그 후, ARC막(24)의 표면이 노출되도록 폴리실리콘막(28)을 CMP로 전면식각하여, 도 2e에 도시된 바와 같이, 폴리실리콘 플러그(28A)를 형성한다.Referring to FIG. 2C, the photoresist pattern 27 is formed on the ARC film 24, and the oxide film 26 is removed using the photoresist pattern 27 as an etching mask to expose the substrate between the spacers 25. Forming a self-aligning contact hole. Then, after removing the photoresist pattern by a known method, as shown in Fig. 2d, a polysilicon film 28 is deposited on the entire surface of the substrate to be filled in the contact hole. Thereafter, the polysilicon film 28 is etched with CMP so that the surface of the ARC film 24 is exposed, thereby forming a polysilicon plug 28A as shown in FIG. 2E.

상기 실시예에 의하면, 산화막(26) 및 폴리실리콘막(28)에 대한 CMP를 ARC막(24)을 식각정지층으로하여 진행하므로 CMP 제어가 용이해진다.According to the above embodiment, CMP for the oxide film 26 and the polysilicon film 28 proceeds with the ARC film 24 as the etch stop layer, thereby facilitating CMP control.

상기한 본 발명에 의하면, 산화막 및 폴리실리콘막에 대한 CMP를 소정의 식각정지층을 적용하여 진행함으로써 CMP 제어가 용이하여, 결국 소자의 신뢰성이 향상된다.According to the present invention described above, CMP control is facilitated by advancing CMP for the oxide film and the polysilicon film by applying a predetermined etch stop layer, thereby improving the reliability of the device.

또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

Claims (7)

상부에 하드 마스크 및 ARC이 순차적으로 적층된 워드라인이 형성된 반도체 기판을 제공하는 단계;Providing a semiconductor substrate having a word line on which a hard mask and ARC are sequentially stacked; 상기 워드라인, 하드 마스크 및 ARC막의 측벽에 절연막 스페이서를 형성하는 단계;Forming insulating film spacers on sidewalls of the word line, hard mask, and ARC film; 상기 기판 전면에 층간절연막을 형성하는 단계;Forming an interlayer insulating film on the entire surface of the substrate; 상기 하드 마스크의 표면이 노출되도록 상기 층간절연막을 전면식각하여 기판 표면을 평탄화시키는 단계;Planarizing the surface of the substrate by etching the entire surface of the interlayer insulating layer so that the surface of the hard mask is exposed; 상기 하드 마스크 상에 절연막 패턴을 형성하는 단계;Forming an insulating film pattern on the hard mask; 상기 제 2 절연막을 제거하여 상기 절연막 스페이서 사이의 기판을 노출시키는 자기정렬 콘택홀을 형성하는 단계;Removing the second insulating film to form a self-aligning contact hole exposing a substrate between the insulating film spacers; 상기 콘택홀에 매립되도록 상기 기판 전면에 폴리실리콘막을 형성하는 단계; 및Forming a polysilicon film on the entire surface of the substrate to be buried in the contact hole; And 상기 절연막 패턴의 표면이 노출되도록 상기 폴리실리콘막을 전면식각하여 폴리실리콘 플러그를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 폴리실리콘 플러그 형성방법.Forming a polysilicon plug by etching the entire polysilicon layer so that the surface of the insulating layer pattern is exposed. 제 1 항에 있어서, 상기 층간절연막 및 상기 폴리실리콘막의 전면식각은 화학적기계적연마로 진행하는 것을 특징으로 하는 반도체 소자의 폴리실리콘 플러그 형성방법.The method of claim 1, wherein the front surface etching of the interlayer insulating film and the polysilicon film is performed by chemical mechanical polishing. 제 1 항 또는 제 2 항에 있어서, 상기 절연막 스페이서 및 절연막 패턴은 질화막으로 형성하는 것을 특징으로 하는 반도체 소자의 폴리실리콘 플러그 형성방법.The method of claim 1 or 2, wherein the insulating film spacer and the insulating film pattern is formed of a nitride film. 제 1 항에 있어서, 상기 층간절연막은 산화막으로 형성하는 것을 특징으로 하는 반도체 소자의 폴리실리콘 플러그 형성방법.The method of claim 1, wherein the interlayer insulating film is formed of an oxide film. 상부에 하드 마스크 및 ARC이 순차적으로 적층된 워드라인이 형성된 반도체 기판을 제공하는 단계;Providing a semiconductor substrate having a word line on which a hard mask and ARC are sequentially stacked; 상기 워드라인, 하드 마스크 및 ARC막의 측벽에 절연막 스페이서를 형성하는 단계;Forming insulating film spacers on sidewalls of the word line, hard mask, and ARC film; 상기 기판 전면에 층간절연막을 형성하는 단계;Forming an interlayer insulating film on the entire surface of the substrate; 상기 ARC막의 표면이 노출되도록 상기 층간절연막을 전면식각하여 기판 표면을 평탄화시키는 단계;Planarizing the surface of the substrate by etching the interlayer dielectric layer so that the surface of the ARC layer is exposed; 상기 층간절연막을 제거하여 상기 절연막 스페이서 사이의 기판을 노출시키는 자기정렬 콘택홀을 형성하는 단계;Removing the interlayer insulating film to form a self-aligning contact hole exposing a substrate between the insulating film spacers; 상기 콘택홀에 매립되도록 기판 전면에 폴리실리콘막을 형성하는 단계; 및Forming a polysilicon film on the entire surface of the substrate to be filled in the contact hole; And 상기 ARC막의 표면이 노출되도록 상기 폴리실리콘막을 전면식각하여 폴리실리콘 플러그를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 폴리실리콘 플러그 형성방법.Forming a polysilicon plug by etching the polysilicon layer over the entire surface of the ARC layer to expose the surface of the ARC layer. 제 5 항에 있어서, 상기 층간절연막 및 상기 폴리실리콘막의 전면식각은 화학적기계적연마로 진행하는 것을 특징으로 하는 반도체 소자의 폴리실리콘 플러그 형성방법.6. The method of claim 5, wherein the front surface etching of the interlayer insulating film and the polysilicon film is performed by chemical mechanical polishing. 제 5 항에 있어서, 상기 절연막 스페이서는 질화막으로 형성하고 상기 층간절연막은 산화막으로 형성하는 것을 특징으로 하는 반도체 소자의 폴리실리콘 플러그 형성방법.6. The method of claim 5, wherein the insulating film spacer is formed of a nitride film and the interlayer insulating film is formed of an oxide film.
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KR100405933B1 (en) * 2001-03-20 2003-11-14 주식회사 하이닉스반도체 Method for forming capacitor of semiconductor device
KR100702837B1 (en) * 2001-06-01 2007-04-03 삼성전자주식회사 Method for fabricating semiconductor device
KR101663049B1 (en) * 2015-03-31 2016-10-06 주식회사 중앙정밀 An apparatus for assembling of a flat display

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JP3215320B2 (en) * 1996-03-22 2001-10-02 株式会社東芝 Method for manufacturing semiconductor device
JPH1126753A (en) * 1996-05-28 1999-01-29 Nippon Steel Corp Semiconductor device and its manufacture and information erasing method using the semiconductor device
JPH1126757A (en) * 1997-06-30 1999-01-29 Toshiba Corp Semiconductor device and manufacture thereof
KR100281692B1 (en) * 1998-10-17 2001-03-02 윤종용 Self-aligned contact pad of semiconductor device and method of forming the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100405933B1 (en) * 2001-03-20 2003-11-14 주식회사 하이닉스반도체 Method for forming capacitor of semiconductor device
KR100702837B1 (en) * 2001-06-01 2007-04-03 삼성전자주식회사 Method for fabricating semiconductor device
KR101663049B1 (en) * 2015-03-31 2016-10-06 주식회사 중앙정밀 An apparatus for assembling of a flat display

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