KR20050024977A - Semicondcutor device having self-alinged contact and method of the same - Google Patents

Abstract

PURPOSE: A semiconductor device with self-aligned contact hole and a method for forming the same are provided to restrain the lifting of a hard mask layer by preventing the short between a conductive line and a conductive material to be filled into a contact hole using a capping pattern with a wider linewidth in a hard mask pattern. CONSTITUTION: At least a pair of line patterns(126) is formed parallel to each other on a dielectric film(103,107) formed on a substrate(101), and comprise a conductive line(109a) and a hard mask pattern(125) that each is stacked sequentially. A dielectric spacer(119a) is formed on a part of each sidewall of at least the pair of line patterns. The top surface of a first interlayer dielectric(120') has the same height as the top surface of at least the pair of line patterns. A conductive material(130) is formed within a contact hole, a first capping pattern(110a) has the same linewidth as the conductive line, a second capping pattern(124a) has a wider linewidth compared with the conductive line.

Description

Semiconductor device having self-aligned contact hole and method for forming same {Semicondcutor device having self-alinged contact and method of the same}

The present invention relates to a semiconductor device and a method of forming the same, and more particularly, to a semiconductor device having a self-aligned contact hole and a method of forming the same.

Typically, contact holes in semiconductor devices belong to means for electrically connecting lower and upper conductors formed in the semiconductor substrate. That is, the contact hole is a passage passing through the insulating film formed between the lower and upper conductors, and a conductive material formed in the contact hole electrically connects the lower and upper conductors.

As the semiconductor device has a higher integration trend, the diameter of the contact hole is gradually decreasing, and the alignment margin between the contact hole and the lower conductor is also gradually decreasing. In addition, a contact hole having a smaller diameter than the minimum diameter that the photolithography process can define may be required. In order to solve these problems, self-aligned contact holes have been proposed.

In general, the method of forming the self-aligned contact hole will be briefly described. A conductive film and a hard mask film are successively formed on a substrate, and the patterns are patterned to form a conductor and a hard mask pattern sequentially stacked. Subsequently, an insulating spacer is formed on sidewalls of the conductor and the hard mask pattern, and an interlayer insulating film is formed on the entire substrate. In this case, the hard mask pattern and the insulating spacer have an etching selectivity with respect to the interlayer insulating layer. Subsequently, a self-aligned contact hole penetrates the interlayer insulating layer and has sidewalls aligned with the hard mask pattern and the insulating spacer.

In general, the interlayer insulating film is formed of an oxide film, and the hard mask film and the insulating spacer are formed of a nitride film. In this case, the nitride film may be formed by a high temperature chemical vapor deposition method to increase the etching selectivity with respect to the oxide film.

However, when the conductive film is formed of a metal film such as tungsten, the nitride film formed by the high temperature chemical vapor deposition method may be lifted from the conductive film. This is because the tungsten and the like are oxidized due to the high temperature of the nitride film forming process. In order to solve this problem, the nitride film may be formed by a low temperature chemical vapor deposition method.

1 is a cross-sectional view for describing a method of forming a semiconductor device having a conventional self-aligned contact hole.

Referring to FIG. 1, a lower interlayer insulating film 2 is formed on a semiconductor substrate 1, and the lower plug 3 penetrates through the lower interlayer insulating film 2 and contacts a predetermined region of the semiconductor substrate 1. To form.

Line patterns 6 are formed on the lower interlayer insulating layer 2 to be parallel to each other. The line patterns 6 are disposed on both upper sides of the lower plug 3, respectively. Each of the line patterns 6 includes a conductive line 4 and a hard mask pattern 5 that are sequentially stacked. In this case, the conductive line 4 is formed of tungsten, and the hard mask pattern 5 is formed of a nitride film using a low temperature chemical vapor deposition method. The low temperature chemical vapor deposition method refers to a chemical vapor deposition method that reduces a process temperature by additionally using a predetermined energy source capable of coping with thermal energy due to a process temperature. Typically, the predetermined energy source uses plasma energy. Insulating spacers 7 are formed on both sidewalls of the line pattern 6. The insulating spacer 7 is formed of the same material as the hard mask pattern 5, that is, a nitride film using a low temperature chemical vapor deposition method.

Subsequently, an upper interlayer insulating film 8 is formed on the entire surface of the semiconductor substrate 1. The upper interlayer insulating film 8 is formed of a silicon oxide film.

The upper interlayer insulating film 8 is patterned to form a contact hole 9 exposing an upper surface of the lower plug 3. In this case, the contact hole 9 exposes a portion of the hard mask pattern 5 and the insulating spacer 7 together with the upper surface of the lower plug 3. That is, the contact hole 9 is self-aligned with a portion of the hard mask pattern 5 and the insulating spacer 7.

In the above-described method for forming a semiconductor device, the hard mask pattern 5 and the insulating spacer 7 are formed of a nitride film (low temperature nitride film) using a low temperature chemical vapor deposition method. In general, the low temperature nitride film has a higher etching rate than that of a nitride film (high temperature nitride film) formed by a high temperature chemical vapor deposition method. In other words, the etching selectivity of the low temperature nitride film with respect to the oxide film is lower than the etching selectivity of the high temperature nitride film with respect to the oxide film. Accordingly, when the contact hole 9 is formed, the hard mask pattern 5 and the insulating spacer 7 may not sufficiently serve as an etch stop layer, and a part of the conductive line 4 may be exposed. In particular, the upper side wall of the conductive line 4 may be exposed. This means that a portion of the insulating spacer 7 formed on the upper sidewall of the conductive line 4 may be thinner than other portions of the insulating spacer 7 formed on the other portion of the conductive line 4. Because there is.

As a result, a conductive material (not shown) filling the contact hole 9 and the conductive line 4 may be electrically shorted due to the exposed portion of the conductive line 4.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned general problems, and includes a semiconductor device having a self-aligned contact hole capable of preventing a short between a conductive material filling a self-aligned contact hole and the conductive material and an adjacent conductive line, and forming the same. To provide a method.

Provided are a semiconductor device and a method of forming the same for solving the above technical problem. The semiconductor device according to the present invention is arranged side by side on the insulating film formed on the semiconductor substrate, each comprising at least a pair of line patterns consisting of a conductive line and a hard mask pattern stacked in sequence. An insulating spacer is disposed on a portion of the line pattern sidewalls. A first interlayer insulating layer may be disposed to cover the line patterns and the insulating spacers and have the same height as the top surfaces of the line patterns to expose the top surfaces of the line patterns. A conductive material is disposed in a contact hole that continuously passes through the first interlayer insulating film and the insulating film filled in the gap region between the line patterns and exposes a predetermined region of the semiconductor substrate. In this case, the hard mask patterns are sequentially stacked, and include a first capping pattern having the same line width as the conductive line and a second capping pattern having a larger line width than the conductive line.

In detail, the insulating spacer may be disposed on both sidewalls of the conductive line and the first capping pattern. A second interlayer insulating layer may be further disposed to cover the top surfaces of the first interlayer insulating layer and the exposed line patterns. In this case, the contact hole continuously penetrates the second and first interlayer insulating layers and the insulating layer to expose a predetermined region of the semiconductor substrate. The second capping pattern may be formed of an insulating layer having a lower etching rate than that of the first capping pattern. In this case, it is preferable that the first capping pattern is made of a low temperature nitride film, and the second capping pattern is made of a high temperature nitride film. The second capping pattern may have a larger line width than the sum of the line width of the conductive line and the thickness of the insulating spacer formed on both side walls of the conductive line.

A method of forming a semiconductor device according to the present invention includes forming an insulating film on a semiconductor substrate. Conductive lines, a first capping pattern, a first dummy pattern, and a second dummy pattern are sequentially formed on the insulating layer. Insulating spacers are formed on both side surfaces of the conductive line and the patterns, and a first interlayer insulating layer is formed on the entire surface of the substrate having the insulating spacers. The first interlayer insulating film is planarized until the top surface of the second dummy pattern is exposed. The exposed second dummy pattern, a portion of the insulating spacer, and the first dummy pattern are continuously removed to form a groove having a wider width than the width of the conductive line and exposing the first capping pattern. A second capping pattern is formed to fill the groove. The planarized first interlayer insulating layer and the insulating layer are successively patterned to form contact holes that are self-aligned to at least one side wall of the second capping pattern.

In detail, the first dummy pattern may be formed of the same material as the first interlayer insulating layer, and the second dummy pattern and the insulating spacer may be formed of an insulating layer having an etching selectivity with respect to the first dummy pattern. . The forming of the groove may include exposing the first dummy pattern, and forming a preliminary groove having a sidewall having the planarized first interlayer insulating layer, and exposing the first capping pattern, which is wider than the preliminary groove. It may comprise the step of forming the groove having a width. The preliminary groove may be formed by removing a portion of the insulating spacer formed on both sides of the exposed second dummy pattern and at least the second dummy pattern by first isotropic etching. The groove may be formed by removing the exposed first dummy pattern by a second isotropic etching. The groove may be formed larger than the sum of the width of the conductive line and the thickness of the insulating spacer formed on both side walls of the conductive line. The second capping pattern may be formed of an insulating layer having a slower etch rate than the first capping pattern. In this case, it is preferable that the first capping pattern is formed of a nitride film by a low temperature chemical vapor deposition method, and the second capping pattern is formed of a nitride film by a high temperature chemical vapor deposition method. The method may further include forming a second interlayer insulating layer covering the planarized first interlayer insulating layer and the second capping pattern before forming the contact hole. In this case, the contact hole is formed by successively patterning the second interlayer insulating film, the planarized first interlayer insulating film, and the insulating film. After forming the contact hole, the method may further include forming a conductive material filling the contact hole.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Portions denoted by like reference numerals denote like elements throughout the specification.

2 is a cross-sectional view illustrating a semiconductor device having a self-aligned contact hole according to a preferred embodiment of the present invention.

Referring to FIG. 2, a first plug 103 is disposed on the semiconductor substrate 101, and the lower plug 105 penetrates through the first insulating film 103 and contacts a predetermined region of the semiconductor substrate 101. Is placed. The second insulating layer 107 covering the lower plug 105 and the first insulating layer 103 is disposed. The first and second insulating layers 103 and 107 may be formed of a silicon oxide layer. The lower plug 105 may be formed of a conductive film, a doped polysilicon film, a metal film such as tungsten, or a conductive metal nitride film.

At least a pair of line patterns 126 are disposed in parallel with each other on the second insulating layer 107. The line patterns 126 are disposed on both sides of the lower plug 105, respectively. Each of the line patterns 126 includes a conductive line 109a and a hard mask pattern 125 that are sequentially stacked, and the hard mask pattern 125 is sequentially stacked with a first capping pattern 110a and a second capping. It consists of a pattern 124a. The first capping pattern 110a has the same first line width W1 as the conductive line 109a, and the second capping pattern 124a has a first line width W1 of the conductive line 109a. It has a wide 2nd line width W2. As illustrated in FIG. 2, the upper surface of the first capping pattern 110a may have a higher central portion than the edge thereof. Unlike this, although not shown, an upper surface of the first capping pattern 110a may be flat.

An insulating spacer 119 ′ is disposed on a portion of both sidewalls of the line pattern 126. The insulating spacer 119 ′ may be disposed on sidewalls of the conductive line 109a and the first capping pattern 110a. The second line width W2 of the second capping pattern 124a is compared with the sum of the thicknesses of the first line width W1 of the conductive line 109a and the thicknesses of the insulating spacers 110a of both side walls of the conductive line 109a. Can be large.

The first interlayer insulating layer 120 ′ is disposed to cover the second insulating layer 107, the line patterns 126, and the insulating spacer 119 ′, and to expose top surfaces of the line patterns 126. That is, the top surface of the first interlayer insulating layer 120 ′ has the same height as the top surfaces of the line patterns 126. A second interlayer insulating film 127 covering the first interlayer insulating film 120 ′ and the top surfaces of the line patterns 126 is disposed on the entire surface of the semiconductor substrate 101.

The conductive line 109a is preferably made of a conductive film, for example, a metal film such as tungsten. Of course, the conductive line 109a may be formed of a conductive film other than a metal film. The hard mask pattern 125 is formed of an insulating layer having an etch selectivity with respect to the first and second interlayer insulating layers 120 ′ and 127. In particular, the second capping pattern 124a may be formed of insulating layers having a lower etching rate than that of the first capping pattern 110a. The first and second interlayer insulating layers 120 ′ and 127 may be formed of silicon oxide layers. In this case, the first capping pattern 110a may be formed of a low temperature nitride film, and the second capping pattern 124a may be formed of a high temperature nitride film. The low temperature nitride film refers to a nitride film formed by a low temperature chemical vapor deposition method, and the high temperature nitride film refers to a nitride film formed by a high temperature chemical vapor deposition method. The high temperature nitride film has a lower etching rate than the low temperature nitride film. In addition, the high temperature nitride film and the low temperature nitride film have an etching selectivity with respect to the silicon oxide film. The insulating spacer 119 ′ may be formed of a low temperature nitride film or a high temperature nitride film.

An upper surface of the lower plug 105 may be formed through the second interlayer insulating layer 127, the first interlayer insulating layer 120 ′ and the second insulating layer 107 that fill the gap regions between the line patterns 126. A contact hole 129 exposing the contact hole 129 is disposed, and a conductive material 130 filling the contact hole 129 is disposed. In this case, the contact hole 129 exposes at least a portion of the hard mask pattern 125. In particular, the contact hole 129 exposes a portion of the second capping pattern 124a. That is, the contact hole 129 is self aligned by the second capping pattern 124a. In addition, the contact hole 129 may be self-aligned to a portion of the insulating spacer 119 ′.

In the above-described semiconductor device, the contact hole 129 is self-aligned in the hard mask pattern 125 with the second capping pattern 124a having a wider second line width W2 than the conductive line 109a. . Accordingly, when the contact hole 129 is formed, the second capping pattern 124a sufficiently protects the conductive line 109a to prevent the conventional conductive line from being exposed. In addition, the second capping pattern 124a is formed of an insulating layer having an etching rate lower than that of the first capping pattern 124a. That is, the first capping pattern 110a is made of a low temperature nitride film, and the second capping pattern 124a is made of a high temperature nitride film. As a result, the etch selectivity between the first interlayer insulating film 120 'and the hard mask pattern 125 is improved to further strengthen the insulation between the conductive material 130 and the conductive line 109a, and at the same time, It is possible to prevent the phenomenon of lifting the hard mask film.

3 to 7 are cross-sectional views illustrating a method of forming a semiconductor device having a self-aligned contact hole according to a preferred embodiment of the present invention.

Referring to FIG. 3, a lower plug 105 is formed on the semiconductor substrate 101 and penetrates through the first insulating film 103 to be connected to a predetermined region of the semiconductor substrate 101. To form. The first insulating layer 103 may be formed of a silicon oxide layer, and the lower plug 105 may be formed of a doped polysilicon layer, a metal layer, or a conductive metal nitride layer, which is a conductive layer.

A second insulating film 107 is formed on the entire surface of the semiconductor substrate 101 having the lower plug 105, and the conductive film 109, the first capping film 110, and the first insulating film 107 are formed on the second insulating film 107. The first dummy layer 111 and the second dummy layer 112 are sequentially formed. The first capping layer 110, the first dummy layer 111, and the second dummy layer 112 constitute a multiple layered layer 115. The conductive film 109 may be formed of a metal film such as tungsten. Of course, the conductive film 109 may be formed of a conductive film other than a metal film.

The second insulating layer 107 may be formed of a silicon oxide layer. The first capping layer 110 is formed of an insulating layer having an etch selectivity with respect to subsequent interlayer insulating layers. For example, the first capping film 110 may be formed of a low temperature nitride film by a low temperature chemical vapor deposition method. The low temperature chemical vapor deposition method is a chemical vapor deposition method in which a process temperature is lowered by additionally using energy (eg, plasma energy) other than thermal energy for energy required for deposition. Plasma Enhanced Chemical Vapor Deposition belongs to the low temperature chemical vapor deposition method. By forming the first capping layer 110 by the low temperature chemical vapor deposition method, a phenomenon in which a conventional hard mask pattern is lifted may be prevented.

The first dummy layer 111 is formed of an insulating layer having an etch selectivity with respect to the first capping layer. In addition, the first dummy layer 111 may be formed of the same material as the interlayer insulating layers formed subsequently. For example, the first dummy layer 111 may be formed of a silicon oxide film. The second dummy layer 112 is formed of an insulating layer having an etching selectivity with respect to the first dummy layer 111. For example, the second dummy layer 112 may be formed of the same material as the first capping layer 110. That is, the second dummy layer 112 may be formed of a low temperature nitride film.

Referring to FIG. 4, the multilayer film 115 and the conductive film 109 are successively patterned to form conductive lines 109a and a multilayer pattern 115a that are sequentially stacked. The multilayer pattern 115a includes a first capping pattern 110a, a first dummy pattern 111a, and a second dummy pattern 112a that are sequentially stacked.

At least one pair of the conductive lines 109a may be formed on the semiconductor substrate 101. The conductive lines 109a may be disposed on both sides of the lower plug 105. The second insulating layer 107 insulates the conductive lines 109a and the lower plug 105 from each other. That is, according to the tendency of high integration of the semiconductor device, even if a gap between the conductive lines 109a is reduced so that a portion of the conductive line 109a overlaps the lower plug 105, the second insulating layer 107 may be used. By doing so, the conductive line 109a and the lower plug 105 are insulated from each other.

Insulating spacers 119 are formed on both sides of the conductive line 109a and the multilayer pattern 115a. The insulating spacer 119 is formed of an insulating layer having an etching selectivity compared to subsequent interlayer insulating layers. For example, the insulating spacer 119 may be formed of a low temperature nitride film or a high temperature nitride film. The high temperature nitride film is a nitride film formed by the high temperature chemical vapor deposition method. The high temperature chemical vapor deposition method refers to a chemical vapor deposition method performed at a high process temperature compared to the low temperature chemical vapor deposition method described above. Although the conductive line 109a is formed of tungsten and the insulating spacer 119 is formed of a high temperature nitride film, the insulating spacer 119 is not lifted. This is because the area where the insulating spacer 119 contacts the conductive line 109a is significantly smaller than the area where the conventional hard mask film and the tungsten film contact.

The first interlayer insulating layer 120 is formed on the entire surface of the semiconductor substrate 101 having the insulating spacer 119. The first interlayer insulating film 120 may be formed of a silicon oxide film.

5 and 6, the first interlayer insulating layer 120 is planarized until an upper surface of the multilayer pattern 115a, that is, an upper surface of the second dummy pattern 112a is exposed. Accordingly, an upper surface of the planarized first interlayer insulating layer 120 ′ may have the same height as an upper surface of the second dummy pattern 112a.

The preliminary groove 121 may be formed by selectively etching the exposed second dummy pattern 112a and a portion of the insulating spacer 119 formed on at least two sidewalls of the second dummy pattern 112a. The preliminary groove 121 exposes the first dummy pattern 112a, and a sidewall thereof is formed of the planarized first interlayer insulating layer 120 ′. When the preliminary groove 121 is formed, a portion of the second dummy pattern 112a and the insulating spacer 119 may be removed by wet etching using isotropic etching, for example, a phosphoric acid solution.

The high temperature nitride film has a lower etching rate for the phosphoric acid solution than the low temperature nitride film. Accordingly, when the insulating spacer 119 is formed of a high temperature nitride film, an undercut region may be formed under the first dummy pattern 111a due to overetching during the wet etching. In other words, when overetching is performed after the first dummy pattern 111a is exposed, a portion of the insulating spacer 119 on both side walls of the first dummy pattern 11a may be further etched to form the first capping pattern ( 110a) is exposed. In this case, since the first capping pattern 110a is etched faster than the insulating spacer 119, the undercut region may occur. Alternatively, the isotropic etching may be stopped when the first capping pattern 110a and the planarized first interlayer insulating layer 120 'are exposed. In this case, an upper surface of the first capping pattern 110a may be flat.

After forming the preliminary groove 121, a recessed insulating spacer 119 ′ remains on sidewalls of the first capping pattern 110a and the conductive line 109a.

Subsequently, the first dummy pattern 111a exposed to the preliminary groove 121 is removed to form the groove 122 exposing the first capping pattern 110a. In this case, the first dummy pattern 111a may be removed by isotropic etching, for example, by wet etching including a hydrofluoric acid solution. Accordingly, the sidewall of the preliminary groove 121 is also recessed. That is, the width of the groove 122 is wider than the width of the preliminary groove 121.

A second capping layer 124 filling the groove 122 is formed on the entire surface of the semiconductor substrate 101. The second capping layer 124 is formed of an insulating layer having an etch selectivity with respect to the planarized first interlayer insulating layer 120 ′. In addition, the second capping layer 124 may be formed of an insulating layer having an etching rate lower than that of the first capping pattern 110a. For example, the second capping film 124 may be formed of a high temperature nitride film by a high temperature chemical vapor deposition method.

Referring to FIG. 7, the second capping layer 124 is planarized until the top surface of the planarized first interlayer insulating layer 120 ′ is exposed to form a second capping pattern 124a in the groove 122. do. The second capping pattern 124a has a wider line width than the conductive line 109a due to the groove 122. In addition, the second capping pattern 124a may have a width wider than the sum of the line width of the conductive line 109a and the thickness of the recessed insulating spacer 119 ′ of both sidewalls of the conductive line 109a. . The first and second capping patterns 110a and 124a constitute a hard mask pattern 125, and the hard mask pattern 125 and the conductive line 109a constitute a line pattern 126.

A second interlayer insulating film 127 is formed on the entire surface of the semiconductor substrate 101 having the hard mask pattern 125. The second interlayer insulating layer 127 may be formed of the same material as the planarized first interlayer insulating layer 120 ′. For example, the second interlayer insulating film 127 may be formed of a silicon oxide film. The second interlayer insulating film 127 is for easily forming a photoresist pattern (not shown) formed on an upper surface thereof. That is, the exposure process for forming the photoresist pattern may deteriorate due to diffuse reflection or the like when different materials coexist in the lower portion of the photoresist. Therefore, by forming the second interlayer insulating film 127 to form a material under the photosensitive film as one, it is possible to improve the performance of the exposure process.

The second interlayer insulating layer 127, the planarized first interlayer insulating layer 120 ′, and the second insulating layer 107 are successively patterned to form a contact hole 129 exposing an upper surface of the lower plug 105. do. Subsequently, the conductive material 130 of FIG. 2 is formed to fill the contact hole 129.

The contact hole 129 is self-aligned to the second capping pattern 124a having a wider width than at least the conductive line 109a. Accordingly, when the contact hole 129 is formed, the conductive line 109a is sufficiently protected. In addition, the second capping pattern 124a may also protect the recessed insulating spacer 119 ′. As a result, when the self-aligned contact hole is formed, a phenomenon in which a portion of the conventional conductive line is exposed may be prevented, and a short phenomenon of the conductive line 109a and the conductive material 130 of FIG.

In addition, the second capping pattern 124a is formed of an insulating layer having an etching rate lower than that of the first capping pattern 110a. That is, the second capping pattern 124a is formed of a high temperature nitride film, and the first capping pattern 110a is formed of a low temperature nitride film. As a result, an etch selectivity between the second capping pattern 124a and the interlayer insulating layers 120 ′ and 127 may be improved to protect the conductive line 109 a of the second capping pattern 124 a. It can be further improved. At the same time, due to the first capping pattern 110a, a phenomenon in which the conventional hard mask layer is lifted from the conductive layer can be prevented.

As described above, according to the present invention, the hard mask pattern formed on the conductive line is composed of a first capping pattern and a second capping pattern which are sequentially stacked. The first capping pattern has the same line width as the conductive line, and the second capping pattern has a wider line width than the conductive line. Accordingly, the contact holes are self-aligned mainly by the second capping pattern. In addition, the second capping pattern is an insulating film having a lower etching rate than the first capping pattern, for example, the first capping pattern is formed of a low temperature nitride film, and the second capping pattern is formed of a high temperature nitride film. As a result, when the contact hole is formed, the phenomenon in which the conductive line is exposed may be prevented to prevent a short phenomenon between the conventional conductive line and the conductive material filling the contact hole, and the phenomenon in which the conventional hard mask layer may be prevented from lifting. .

1 is a cross-sectional view for describing a method of forming a semiconductor device having a conventional self-aligned contact hole.

2 is a cross-sectional view illustrating a semiconductor device having a self-aligned contact hole according to a preferred embodiment of the present invention.

3 to 7 are cross-sectional views illustrating a method of forming a semiconductor device having a self-aligned contact hole according to a preferred embodiment of the present invention.

Claims (14)

At least one pair of line patterns arranged side by side on an insulating film formed on the semiconductor substrate, each of which comprises a conductive line and a hard mask pattern stacked in turn; An insulating spacer disposed on a portion of the line pattern sidewalls; A first interlayer insulating layer covering the line patterns and the insulating spacer and having the same height as the top surface of the line patterns to expose the top surfaces of the line patterns; And And a conductive material formed in a contact hole through the first interlayer insulating layer and the insulating layer filled in the gap region between the line patterns and exposing a predetermined region of the semiconductor substrate, wherein the hard mask patterns are sequentially stacked. And a first capping pattern having the same line width as the conductive line and a second capping pattern having a larger line width than the conductive line. The method of claim 1, The insulating spacer is disposed on both side walls of the conductive line and the first capping pattern. The method of claim 1, The semiconductor device may further include a second interlayer insulating layer covering the first interlayer insulating layer and the upper surfaces of the exposed line patterns, wherein the contact hole may continuously penetrate the second and first interlayer insulating layers and the insulating layer to form an insulating film. A semiconductor device characterized by exposing a predetermined region. The method of claim 1, And the second capping pattern is an insulating film having an etching rate lower than that of the first capping pattern. The method of claim 4, wherein The first capping pattern is made of a low temperature nitride film, the second capping pattern is a semiconductor device, characterized in that made of a high temperature nitride film. The method of claim 1, And the second capping pattern has a larger line width than a sum of a line width of the conductive line and a thickness of an insulating spacer formed on both sidewalls of the conductive line. Forming an insulating film on the semiconductor substrate; Forming a conductive line, a first capping pattern, a first dummy pattern, and a second dummy pattern sequentially stacked on the insulating layer; Forming insulating spacers on both sidewalls of the conductive lines and the patterns; Forming a first interlayer insulating film on an entire surface of the substrate having the insulating spacers; Planarizing the first interlayer insulating film until the top surface of the second dummy pattern is exposed; Continuously removing the exposed second dummy pattern, a part of the insulating spacer, and the first dummy pattern to form a groove having a wider width than the width of the conductive line and exposing the first capping pattern; Forming a second capping pattern to fill the groove; And And successively patterning the planarized first interlayer insulating film and the insulating film to form contact holes that are self-aligned to at least one side wall of the second capping pattern. The method of claim 7, wherein Wherein the first dummy pattern is formed of the same material as the first interlayer insulating layer, and the second dummy pattern and the insulating spacer are formed of an insulating layer having an etch selectivity with respect to the first dummy pattern. Method of formation. The method of claim 7, wherein Forming the grooves, A portion of the exposed second dummy pattern and at least a portion of the insulating spacer formed on both sidewalls of the second dummy pattern is removed by first isotropic etching to expose the first dummy pattern, and sidewalls of the first interlayer insulating film are formed. Forming a preliminary groove; And Removing the exposed first dummy pattern by a second isotropic etch to expose the first capping pattern, and forming a groove having a wider width than the preliminary groove. . The method of claim 7, wherein And the groove is larger than the sum of the width of the conductive line and the thickness of the insulating spacer formed on both side walls of the conductive line. The method of claim 7, wherein The second capping pattern is formed of an insulating film having a slower etch rate than the first capping pattern, wherein the first and second capping patterns constitute a hard mask pattern. The method of claim 11, The first capping pattern is formed of a nitride film by a low temperature chemical vapor deposition method, the second capping pattern is formed of a nitride film by a high temperature chemical vapor deposition method. The method of claim 7, wherein Before forming the contact hole, The method may further include forming a planarized first interlayer dielectric layer and a second interlayer dielectric layer covering the second capping pattern, wherein the contact hole is formed by continuously patterning the second interlayer dielectric layer, the planarized first interlayer dielectric layer, and the insulating layer. And forming the semiconductor device. The method of claim 7, wherein After the contact hole is formed, And forming a conductive material filling the contact hole.