KR100546152B1 - Contact Forming Method of Semiconductor Device - Google Patents
Contact Forming Method of Semiconductor Device Download PDFInfo
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- KR100546152B1 KR100546152B1 KR1019980059553A KR19980059553A KR100546152B1 KR 100546152 B1 KR100546152 B1 KR 100546152B1 KR 1019980059553 A KR1019980059553 A KR 1019980059553A KR 19980059553 A KR19980059553 A KR 19980059553A KR 100546152 B1 KR100546152 B1 KR 100546152B1
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Abstract
본 발명은 반도체소자의 콘택 형성방법에 관한 것으로, 0.15 ㎛ 이하의 소자에 필요한 수정된 플러그 색 ( modified plug SAC ( Self Aligned Contact) ) 방법에 있어서, 일반적으로, 수정된 플러그 SAC 공정에서 플러그 SAC 에치 ( etch ) 후 마스크 오픈 지역에서만 발생되는 국부적인 질화막 ( nitride ) 로 인해 플러그 폴리실리콘 화학기계연마 ( chemical mechanical polishing, 이하 CMP 라 함 ) 후 마스크 경계부에 잔류하는 폴리실리콘 스트링거 ( poly-silicon stringer ) 를 제거하고자 색 산화막 에치시 질화막 손상 ( nitride loss ) 을 최소화하기 위한 절연산화막을 형성하지 않고 플러그 SAC 마스크를 형성하고 감광막패턴을 이용하여 습식 산화막 에치 ( wet oxide etch ) 를 진행하여 식각장벽층 ( etch stopper ) 인 C-C 결합을 지닌 폴리머를 형성하고 SAC 산화막 건식방법으로 에치한 다음, 감광막을 제거 ( strip ) 하고 블랭킷 질화막 에치 ( blanket nitride etch ), 플러그 폴리실리콘 증착 및 플러그 폴리실리콘 CMP 공정을 진행하여 폴리실리콘 스트링거 ( poly-silicon stringer ) 로 인한 소자의 페일 ( fail ) 을 감소시킴으로써 반도체소자의 수율 및 생산성을 향상시킬 수 있는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact of a semiconductor device. In the modified plug SAC (self-aligned contact) method required for devices having a thickness of 0.15 μm or less, generally, a plug SAC etch in a modified plug SAC process After the etch, due to the local nitride film generated only in the mask open area, the polysilicon stringer remaining in the mask boundary after the plug polysilicon chemical mechanical polishing (CMP) To remove the etch stopper, a plug SAC mask is formed without forming an insulating oxide layer to minimize nitride loss, and a wet oxide etch is performed using a photoresist pattern to etch stopper. To form a polymer having a CC bond, and etch it by SAC oxide dry method. Stripping, blanket nitride etch, plug polysilicon deposition, and plug polysilicon CMP processes to reduce device fail due to polysilicon stringers. It is a technology that can improve the yield and productivity.
Description
본 발명은 반도체소자의 콘택 형성방법에 관한 것으로,The present invention relates to a method for forming a contact of a semiconductor device,
0.15 ㎛ 이하의 소자에 필요한 수정된 플러그 SAC ( modified plug SAC ( Self Aligned Contact) ) 방법에 있어서, 일반적으로, 수정된 플러그 SAC 공정에서 플러그 SAC 에치 ( etch ) 후 마스크 오픈 지역에서만 발생되는 국부적인 질화막 ( nitride ) 으로 인해 플러그 폴리실리콘의 화학기계연마 ( chemical mechanical polishing, 이하 CMP 라 함 ) 후 마스크 경계부에 잔류하는 폴리실리콘 스트링거 ( poly stringer ) 를 제거하여 폴리실리콘 스트링거로 인한 소자 페일을 감소시킬 수 있도록 하는 방법에 관한 것이다.In the modified plug SAC method, which is required for devices smaller than 0.15 μm, in general, localized nitride film generated only in the mask open area after plug SAC etch in the modified plug SAC process. Nitride eliminates polysilicon stringers remaining at the mask boundary after chemical mechanical polishing (CMP) of plug polysilicon to reduce device failure due to polysilicon stringers. It is about how to.
종래의 일반적인 수정된 플러그 SAC 형성 방법은 층간절연막 ( ILD, inter layer dielectric ) CMP후 콘택마스크를 이용한 사진식각공정으로 콘택홀을 형성한 다음, 산화막과 질화막 등의 식각 공정을 진행하여 콘택 면적을 확보하는 방법으로서 이는 0.15 - 0.25 ㎛ 급 소자에 적용 가능하였다.Conventional modified plug SAC formation method uses a photolithography process using a contact mask after an interlayer dielectric (ILD) CMP, and then forms a contact hole, and then performs an etching process such as an oxide film and a nitride film to secure a contact area. This method was applicable to 0.15-0.25 micrometer grade devices.
그러나 4G 디램급 이상의 소자를 형성하는데 있어 마스크 공정상의 중첩 마마진 측면에서 소자의 동작을 위해 필요한 적절한 콘택 면적 확보가 불가능하게 되었다.However, in forming 4G DRAM or higher devices, it is impossible to secure proper contact area required for device operation in terms of overlapping margin in the mask process.
도 1a 내지 도 1e 는 일반적인 수정된 플러그 SAC 공정을 적용한 반도체소자의 콘택 형성방법을 도시한 단면도 및 평면도로서, 도 1e 는 도 1d 의 평면도를 도시한다.1A to 1E are cross-sectional views and a plan view illustrating a method of forming a contact of a semiconductor device to which a general modified plug SAC process is applied, and FIG. 1E illustrates the top view of FIG. 1D.
도 1a를 참조하면, 실리콘기판(1) 상에 상측에 캐핑 질화막(미도시)이 구비되는 워드라인(2)을 형성한다.Referring to FIG. 1A, a word line 2 having a capping nitride layer (not shown) is formed on the silicon substrate 1.
그리고, 상기 워드라인(2) 측벽에 스페이서 질화막(3)을 형성하고, 전 표면에 장벽 질화막(4) 및 도핑방지막(5)을 증착한 다음, 그 상부에 층간절연막(6)을 증착한다.A spacer nitride film 3 is formed on the sidewalls of the word line 2, a barrier nitride film 4 and an anti-doping film 5 are deposited on the entire surface, and an interlayer insulating film 6 is deposited thereon.
도 1b를 참조하면, 상기 워드라인(2) 상부에 질화막(4)이 노출될 때까지 층간절연막(6)을 화학적 기계적 연마 ( CMP ) 공정으로 평탄화 식각한다.Referring to FIG. 1B, the interlayer insulating film 6 is planarized and etched by a chemical mechanical polishing (CMP) process until the nitride film 4 is exposed on the word line 2.
그리고, SAC 산화막 에치시 질화막 손상을 최소화하기 위한 산화막(8)을 증착하고 마스크 공정 마진을 증기시키기 위한 반사방지막(9)을 증착한 다음, 플러그 SAC 마스크 공정으로 감광막패턴(10)을 형성한다.Then, an oxide film 8 is deposited to minimize nitride film damage when the SAC oxide is etched, and an antireflection film 9 is deposited to vaporize the mask process margin, and then the photoresist pattern 10 is formed by a plug SAC mask process.
이때, 상기 플러그 SAC 마스크는 I, T 또는 Z-타입의 활성영역을 노출시키는 형태로 형성된 것이다.In this case, the plug SAC mask is formed to expose the active region of the I, T or Z-type.
도 1c를 참조하면, 상기 감광막패턴(10)을 마스크로 하여 플러그 SAC 에치를 진행하면 상기 활성영역과 이와 이웃하는 비활성영역의 경계부에 국부적인 질화막(4) 손상이 A 와 같이 발생한다.Referring to FIG. 1C, when the plug SAC is etched using the photoresist pattern 10 as a mask, damage to the localized nitride film 4 occurs at the boundary between the active region and the neighboring inactive region.
도 1d, 도 1e 및 도 1f 를 참조하면, 플러그 SAC 질화막 에치를 진행하여 상기 실리콘기판(1)의 활성영역을 노출시키는 콘택홀(13)을 형성하다. 이때, 상기 활성영역에서는 B 만큼의 질화막 손상이 발생한다.Referring to FIGS. 1D, 1E, and 1F, a contact hole 13 exposing the active region of the silicon substrate 1 is formed by performing plug SAC nitride film etch. In this case, as much as B nitride film damage occurs in the active region.
그 다음, 상기 감광막패턴(10)을 제거하고 전체표면상부에 플러그 폴리실리콘(14)을 증착한 다음, 상기 워드라인(2) 상측의 캐핑 질화막(11)이 노출될 때까지 상기 플러그 폴리실리콘(14)을 CMP 하여 콘택플러그(21)를 형성한다.Next, the photoresist layer pattern 10 is removed, and the plug polysilicon 14 is deposited on the entire surface, and the plug polysilicon (11) is exposed until the capping nitride layer 11 on the word line 2 is exposed. 14), the contact plug 21 is formed by CMP.
이때, 상기 활성영역은 콘택플러그(21)가 형성되지만, 활성영역과 비활성영역과의 경계부에는 폴리실리콘 스트링거 ( poly-silicon stringer )(16)가 발생하여 소자의 페일 ( fail ) ( poly-silicon stringer )을 유발한다.In this case, a contact plug 21 is formed in the active region, but a poly-silicon stringer 16 is generated at the boundary between the active region and the inactive region, thereby failing the device (poly-silicon stringer). Cause).
이상에서 설명한 바와 같이 종래기술에 따른 반도체소자의 콘택 형성방법은, 콘택플러그 형성공정시 플러그 물질인 폴리실리콘이 과도식각된 게이트전극의 상부에 남게 되어 상기 게이트전극과 콘택플러그가 접속되는 폴리실리콘 스트링거 ( poly-silicon stringer ) 를 유발함으로써 소자의 특성 및 신뢰성을 저하시키는 문제점이 있다.As described above, in the method of forming a contact of a semiconductor device according to the related art, a polysilicon stringer, in which a polysilicon as a plug material is left over an overetched gate electrode during a contact plug forming process, is connected to the gate electrode and the contact plug. By causing (poly-silicon stringer), there is a problem of degrading the characteristics and reliability of the device.
본 발명은 상기한 바와 같은 종래기술의 문제점을 해결하기 위하여,The present invention to solve the problems of the prior art as described above,
자기정렬적인 콘택공정으로 콘택플러그를 형성하되, 1단계의 CMP 공정을 이용하여 단차가 완화되고 폴리실리콘 스트링거 ( poly-silicon stringer )가 제거되도록 형성하므로써 반도체소자의 페일 ( fail ) 을 감소시켜 반도체소자의 수율 및 생산성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 콘택 형성방법을 제공하는데 그 목적이 있다.The contact plug is formed by a self-aligned contact process, but the step is reduced by using the one-step CMP process and the polysilicon stringer is removed to reduce the fail of the semiconductor device. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a contact for a semiconductor device, which improves the yield and productivity of the semiconductor device and thereby enables high integration of the semiconductor device.
상기 목적 달성을 위해 본 발명에 따른 반도체소자의 콘택 형성방법은,Contact formation method of a semiconductor device according to the present invention for achieving the above object,
실리콘기판 상부에 캐핑 질화막이 상측에 구비된 워드라인을 형성하고 그 측벽에 스페이서 질화막을 형성하는 공정과,Forming a word line having a capping nitride film on an upper side of the silicon substrate and forming a spacer nitride film on a sidewall thereof;
전표면에 장벽 질화막, 도핑 방지막을 형성하는 공정과,Forming a barrier nitride film and an anti-doping film on the entire surface;
상기 도핑 방지막 상부에 층간절연막을 증착하고 이를 열처리하는 공정과,Depositing an interlayer insulating film on the anti-doping film and heat-treating it;
상기 장벽 질화막이 노출될 때까지 상기 층간절연막과 도핑방지막을 CMP 하는 공정과,CMPing the interlayer insulating film and the anti-doping film until the barrier nitride film is exposed;
전체구조 상에 플러그 SAC 마스크 ( plug SAC mask ) 를 이용한 노광 및 현상공정으로 감광막패턴을 형성하는 공정과,Forming a photoresist pattern on the entire structure by exposure and development using a plug SAC mask;
상기 감광막패턴을 마스크로 하여 상기 층간절연막을 50 - 200 Å 두께 습식방법으로 에치하되, 상기 층간절연막 상부에 폴리머를 형성하는 공정과,Etching the interlayer insulating film by a 50-200 Å thickness wet method using the photosensitive film pattern as a mask, and forming a polymer on the interlayer insulating film;
상기 감광막패턴을 마스크로 하는 건식방법의 에치 공정으로 장벽 질화막을 노출시키고 상기 감광막패턴을 제거하는 공정과,Exposing the barrier nitride film and removing the photoresist pattern by an etch process of a dry method using the photoresist pattern as a mask;
상기 노출된 장벽 질화막을 블랭킷 ( blanket ) 에치 공정으로 식각하여 콘택홀을 형성하는 공정과,Etching the exposed barrier nitride layer by a blanket etch process to form a contact hole;
상기 콘택홀을 매립하는 플러그 폴리실리콘을 형성하고 이를 CMP 하여 콘택플러그를 형성하는 공정을 포함하는 것과,Forming a plug polysilicon filling the contact hole and CMP the contact hole to form a contact plug;
상기 장벽 질화막은 PECVD ( Plasma Enhanced Chemical mechanical polishing ) 또는 LPCVD ( Plasma Enhanced Chemical mechanical polishing ) 방법으로 50 - 400 Å 두께만큼 증착하는 것과,The barrier nitride film is deposited by 50-400 mm thick by PECVD (Plasma Enhanced Chemical mechanical polishing) or LPCVD (Plasma Enhanced Chemical mechanical polishing) method,
상기 도핑 방지막은 중온산화막 ( middle temperature oxide, 이하에서 MTO 라 함 ) 이나 고온산화막 (high temperature oxide, 이하에서 HTO 라 함 ) 을 50 - 400 Å 두께만큼 증착하여 형성하는 것과,The anti-doping film is formed by depositing a middle temperature oxide (hereinafter referred to as MTO) or a high temperature oxide (hereinafter referred to as HTO) by a thickness of 50 to 400 ,,
상기 습식 에치 공정시 상기 감광막패턴이 10 - 500 Å 식각되는 것과,In the wet etching process, the photoresist pattern is etched 10-500 Å,
상기 습식 에치 공정 후에 C-F 계 가스를 플로우시켜 상기 층간절연막 상부에 폴리머를 발생시키는 것을 특징으로 한다.The C-F-based gas is flowed after the wet etch process to generate a polymer on the interlayer insulating layer.
한편, 이상의 목적을 달성하기 위한 본 발명의 원리는,On the other hand, the principle of the present invention for achieving the above object,
감광막패턴을 마스크로 하는 습식 및 건식 식각공정으로 워드라인인 게이트 전극 상부에 폴리머를 형성하여 활성영역 상의 콘택홀 형성공정시 상기 게이트전극의 손상을 최소화시킬 수 있도록 하여 후속 플러그 폴리실리콘의 증착 및 평탄화 식각공정으로 폴리실리콘 스트링거 ( poly-silicon stringer ) 의 유발을 방지할 수 있도록 하는 것이다.Wet and dry etching processes using photoresist patterns as masks form polymers on the gate electrodes, which are word lines, to minimize damage to the gate electrodes during the process of forming contact holes on the active region, thereby depositing and planarizing the subsequent plug polysilicon. The etching process prevents the induction of poly-silicon stringers.
이때, 상기 질화막 상부에 충분한 양의 폴리머를 형성하고 건식방법으로 에치를 진행하면 질화막 손상을 크게 감소시킬 수 있다.In this case, if a sufficient amount of polymer is formed on the nitride film and etched by a dry method, damage to the nitride film can be greatly reduced.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f 는 본 발명의 실시예에 따른 반도체소자의 콘택 형성방법을 도시한 단면도 및 평면도로서, 상기 도 2f 는 도 2e 의 평면도를 도시한다.2A to 2F are cross-sectional views and a plan view illustrating a method for forming a contact of a semiconductor device according to an exemplary embodiment of the present invention, and FIG. 2F illustrates the top view of FIG. 2E.
도 2a 를 참조하면, 캐핑 질화막(11)이 상측에 형성된 워드라인(2)을 형성하고, 그 측벽에 스페이서 질화막(3)을 형성한다.Referring to FIG. 2A, a capping nitride film 11 forms a word line 2 formed on an upper side thereof, and a spacer nitride film 3 is formed on a sidewall thereof.
이때, 상기 스페이서 질화막(3)은 전체표면상부에 PECVD ( Plasma Enhanced Chemical mechanical polishing ) 또는 LPCVD ( Plasma Enhanced Chemical mechanical polishing ) 방법으로 질화막을 100 - 700 Å 두께만큼 증착하고 이를 이방성식각하여 형성한다.At this time, the spacer nitride film 3 is formed by depositing an anisotropically etched nitride film 100-700 Å thickness by PECVD (Plasma Enhanced Chemical mechanical polishing) or LPCVD (Plasma Enhanced Chemical mechanical polishing) method on the entire surface.
그 다음, 전체표면에 장벽 질화막(4)을 PECVD 또는 LPCVD 방법으로 50 - 400 Å 두께만큼 증착하고 그 상부에 도핑 방지막(5)인 증온산화막 ( middle temperature oxide, 이하에서 MTO 라 함 ) 나 고온산화막 ( high temperature oxide, 이하에서 HTO 라 함 ) 을 50 - 400 Å 만큼 증착한다.Then, the barrier nitride film 4 is deposited on the entire surface by PECVD or LPCVD with a thickness of 50 to 400 Å, and on top of it, a middle temperature oxide (hereinafter referred to as MTO) or a high temperature oxide film. (high temperature oxide, hereinafter HTO) is deposited by 50-400 Hz.
이때, 상기 장벽 질화막(4)은 후속 공정으로 실시되는 CMP 공정시 하부구조물의 손상을 방지하기 위한 박막으로서, 장벽층으로 사용되기 위한 최소 두께 범위로 형성한 것이다.In this case, the barrier nitride film 4 is a thin film for preventing damage to the lower structure during the CMP process performed in a subsequent process, and is formed in a minimum thickness range for use as a barrier layer.
상기 도핑 방지막(5)은 후속 공정으로 형성되는 층간절연막(6)에 함유된 불순물이 반도체기판(1)으로 확산되는 현상을 방지함으로써 층간절연막(6)의 특성 변화를 방지하고 반도체기판(1)이 도핑되는 현상을 방지하는 박막으로서, 도핑 방지막의 역할을 수행할 수 있는 최소 두께 범위를 형성한 것이다.The anti-doping film 5 prevents a phenomenon in which impurities contained in the interlayer insulating film 6 formed in a subsequent process is diffused into the semiconductor substrate 1, thereby preventing the characteristic change of the interlayer insulating film 6 and preventing the semiconductor substrate 1. As a thin film for preventing the doping phenomenon, a minimum thickness range that can serve as an anti-doping film is formed.
그리고, 비.피.에스.지. ( boro phospho silicate glass, 이하에서 BPSG 라 함 ), 피.에스.지. ( phospho silicate glass, 이하에서 PSG 라 함 ), 에프.에스.지. ( fluorine silicate glass, 이하에서 FSG 라 함 ), 에이.엘.피. ( APL ) 산화막, 오존-테오스 ( ozone-tetraethylorthosilicate, 이하에서 O3-TEOS 라 함 ) 또는 고밀도 플라즈마 산화막 ( high density plasma oxide, 이하에서 HDP 라 함 ) 을 이용하여 4000 - 10000 Å 두께의 층간절연막(6)을 증착한다.And B.P.S. (boro phospho silicate glass, hereinafter referred to as BPSG). (phospho silicate glass, hereinafter referred to as PSG), F.G. (fluorine silicate glass, hereinafter referred to as FSG), A.L.P. (APL) An interlayer insulating film of 4000-10000 Å thickness using an oxide film, ozone-tetraethylorthosilicate (hereinafter referred to as O 3 -TEOS) or a high density plasma oxide (hereinafter referred to as HDP). (6) is deposited.
그리고, 300 - 1000 ℃ 의 온도에서 열처리하여 산화막용 슬러리로 상기 워드라인 상부의 질화막(4)이 드러날 때까지 CMP 한다.Then, heat treatment is performed at a temperature of 300 to 1000 ° C. until the nitride film 4 on the word line is exposed to the slurry for oxide film.
도 2b 를 참조하면, I, T 또는 Z-타입의 활성영역 마스크를 이용한 플러그 SAC 마스크 공정으로 감광막패턴(10)을 형성한다.Referring to FIG. 2B, the photosensitive film pattern 10 is formed by a plug SAC mask process using an I, T or Z-type active region mask.
그리고, 상기 장벽 질화막(4) 상부에 C-C 결합을 지닌 감광막 잔류물인 폴리머(20)를 유발시키기 위하여, 상기 감광막패턴(10)을 마스크로 한 습식방법으로 에치한다. 이때, 상기 습식방법의 에치 공정은 상기 감광막패턴(10)의 표면만을 에치할 수 있도록 산화막 계열인 층간절연막(6)을 50 - 200 Å 만큼 에치하여, 후속 공정에서 상기 감광막패턴(10)이 마스크 역할을 할 수 있도록 최소 두께 범위만을 에치한 것이다.Then, in order to induce the polymer 20 which is a photoresist residue having a C-C bond on the barrier nitride layer 4, the photoresist pattern 10 is etched by a wet method using a mask. At this time, the etch process of the wet method etches the interlayer insulating film 6, which is an oxide film series, by 50 to 200 Å so that only the surface of the photosensitive film pattern 10 can be etched, and the photosensitive film pattern 10 is masked in a subsequent process. Only the minimum thickness range is etched to play a role.
여기서, 상기 감광막패턴(10)에 도시된 점선은 감광막이 일정부분 에치되어 형성된 프로파일을 도시한다.Here, the dotted line illustrated in the photoresist pattern 10 illustrates a profile formed by etching the photoresist part.
도 2c 를 참조하면, 산화막층인 층간절연막(6)을 제거하되, C2F4, C3F6 및 C4F8 와 같은 C-F 계 가스를 플로우시켜 장벽 질화막(4) 상부에 식각장벽층인 C-C 결합 폴리머 또는 C-F 결합 폴리머를 다량 형성하고, 상기 감광막패턴(10)을 마스크로 하여 상기 층간절연막(6)을 건식방법으로 에칭함으로써 마스크 오픈 지역내의 산화막을 모두 제거한다. 이때, 활성영역과 비활성영역 간의 경계부에서 종래보다 작은 "C" 만큼의 국부적인 장벽 질화막(4) 손상이 유발된다.Referring to FIG. 2C, an oxide-layered interlayer insulating film 6 is removed and a CF-based gas such as C2F4, C3F6 and C4F8 is flowed to form a CC-bonded polymer or CF-bonded polymer as an etch barrier layer on the barrier nitride film 4. A large amount is formed, and the interlayer insulating film 6 is etched by a dry method using the photosensitive film pattern 10 as a mask to remove all the oxide film in the mask open area. At this time, local barrier nitride film 4 damage as small as "C" is caused at the boundary between the active and inactive regions.
그리고, 상기 감광막패턴(10)을 제거한다.Then, the photoresist pattern 10 is removed.
도 2d 를 참조하면, 마스크 공정 없이 실시하는 블랭킷 ( blanket ) 에치공정으로 활성영역 상부의 장벽 질화막(4)을 에치하여 상기 실리콘 기판(1)의 활성영역을 노출시키는 콘택홀(13)을 자기정렬적으로 형성한다.Referring to FIG. 2D, a self-aligned contact hole 13 exposing the active region of the silicon substrate 1 by etching the barrier nitride film 4 over the active region by a blanket etch process without a mask process. Form the enemy.
그 다음에, 상기 콘택홀(13)을 매립하는 플러그 폴리실리콘(14)을 전체표면상부에 500 - 4000 Å 두께로 형성한다.Next, a plug polysilicon 14 filling the contact hole 13 is formed on the entire surface to a thickness of 500 to 4000 mm 3.
도 2e 및 도 2f 를 참조하면, 상기 플러그 폴리실리콘(14)을 폴리용 슬러리를 이용하여 CMP 함으로써 수정된 플러그 SAC 공정의 최종 목적인 워드라인(2)을 이용한 콘택 분리 ( isolation ) 가 이루어지고 그에 따른 콘택플러그(21)가 형성된다.Referring to FIGS. 2E and 2F, contact isolation using the word line 2, which is the final purpose of the modified plug SAC process, is achieved by CMPing the plug polysilicon 14 using a slurry for poly and accordingly The contact plug 21 is formed.
따라서 소자 페일 ( fail ) 을 근본적으로 제거할 수 있다. (도 2e, 도 2f)Thus, device fail can be fundamentally eliminated. (FIG. 2E, FIG. 2F)
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 콘택 형성방법은, 한 단계의 플러그 폴리실리콘 CMP 공정으로 콘택플러그를 형성하되, 폴리실리콘 스트링거 ( poly-silicon stringer ) 가 없고 단차가 완화된 형태로 형성하여 반도체소자의 소자 페일 ( fail ) 을 방지할 수 있고, CMP 공정의 단축으로 공정단가를 감소시킬 수 있어 그에 따른 반도체소자의 수율 및 생산성을 향상시키고 반도체소자의 고집적화를 가능하게 하는 기술이다.As described above, in the method for forming a contact of a semiconductor device according to the present invention, the contact plug is formed by a plug polysilicon CMP process in one step, but the polysilicon stringer is formed without a step difference. Therefore, the device fail of the semiconductor device can be prevented, and the process cost can be reduced by shortening the CMP process, thereby improving the yield and productivity of the semiconductor device and enabling high integration of the semiconductor device.
도 1a 내지 도 1f 는 종래기술에 따른 반도체소자의 콘택 형성방법을 도시한 단면도 및 평면도.1A to 1F are cross-sectional views and plan views illustrating a method for forming a contact of a semiconductor device according to the prior art.
도 2a 내지 도 2f 는 본 발명의 실시예에 따른 반도체소자의 콘택 형성방법을 도시한 단면도 및 평면도.2A to 2F are cross-sectional views and plan views illustrating a method for forming a contact in a semiconductor device according to an embodiment of the present invention.
〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
1 : 실리콘기판 2 : 워드라인1: silicon substrate 2: word line
3 : 스페이서 질화막 4 : 장벽 질화막3: spacer nitride film 4: barrier nitride film
5 : 도핑방지막 6 : 층간절연막5: anti-doping film 6: interlayer insulating film
8 : 질화막 손상 억제용 산화막 9 : 반사방지막8: oxide film for inhibiting nitride film damage 9: antireflection film
10 : 감광막패턴10: photosensitive film pattern
13 : 콘택홀 14 : 플러그 폴리실리콘13 contact hole 14 plug polysilicon
16 : 폴리실리콘 스트링거 ( poly-silicon stringer )16: poly-silicon stringer
20 : 폴리머 21 : 콘택플러그20 polymer 21 contact plug
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980059553A KR100546152B1 (en) | 1998-12-28 | 1998-12-28 | Contact Forming Method of Semiconductor Device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980059553A KR100546152B1 (en) | 1998-12-28 | 1998-12-28 | Contact Forming Method of Semiconductor Device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000043203A KR20000043203A (en) | 2000-07-15 |
| KR100546152B1 true KR100546152B1 (en) | 2006-04-14 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980059553A KR100546152B1 (en) | 1998-12-28 | 1998-12-28 | Contact Forming Method of Semiconductor Device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100546152B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9972696B2 (en) | 2015-09-21 | 2018-05-15 | Samsung Electronics Co., Ltd. | Etching method and method of fabricating a semiconductor device using the same |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100480233B1 (en) * | 2000-12-29 | 2005-04-06 | 주식회사 하이닉스반도체 | Method for forming the contact hole of semiconductor device |
| KR100410980B1 (en) * | 2001-04-24 | 2003-12-18 | 삼성전자주식회사 | Method for Forming SAC Contact pad in Semiconductor Device |
| KR100702837B1 (en) * | 2001-06-01 | 2007-04-03 | 삼성전자주식회사 | Method for fabricating semiconductor device |
| KR100732308B1 (en) * | 2001-06-22 | 2007-06-25 | 주식회사 하이닉스반도체 | Method for chemical mechanical polishing of semiconductor device |
| KR100732309B1 (en) * | 2001-06-22 | 2007-06-25 | 주식회사 하이닉스반도체 | Manufacturing method for semiconductor device |
-
1998
- 1998-12-28 KR KR1019980059553A patent/KR100546152B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9972696B2 (en) | 2015-09-21 | 2018-05-15 | Samsung Electronics Co., Ltd. | Etching method and method of fabricating a semiconductor device using the same |
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| Publication number | Publication date |
|---|---|
| KR20000043203A (en) | 2000-07-15 |
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