KR100327663B1 - Forming method for inter layer oxide of semiconductor device - Google Patents
Forming method for inter layer oxide of semiconductor device Download PDFInfo
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- KR100327663B1 KR100327663B1 KR1019990025386A KR19990025386A KR100327663B1 KR 100327663 B1 KR100327663 B1 KR 100327663B1 KR 1019990025386 A KR1019990025386 A KR 1019990025386A KR 19990025386 A KR19990025386 A KR 19990025386A KR 100327663 B1 KR100327663 B1 KR 100327663B1
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- insulating film
- interlayer insulating
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- oxide film
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- 239000011229 interlayer Substances 0.000 title claims abstract description 74
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000010438 heat treatment Methods 0.000 claims abstract description 10
- 125000006850 spacer group Chemical group 0.000 claims abstract description 9
- 239000011810 insulating material Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 238000007517 polishing process Methods 0.000 claims description 3
- UPSOBXZLFLJAKK-UHFFFAOYSA-N ozone;tetraethyl silicate Chemical compound [O-][O+]=O.CCO[Si](OCC)(OCC)OCC UPSOBXZLFLJAKK-UHFFFAOYSA-N 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 9
- 239000004020 conductor Substances 0.000 description 8
- 238000005530 etching Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- -1 boro phophos Chemical compound 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체소자의 층간절연막 형성방법에 관한 것으로,The present invention relates to a method for forming an interlayer insulating film of a semiconductor device,
패터닝된 게이트전극과 마스크산화막 적층구조가 구비된 반도체기판에 스페이서용 절연막을 형성하고 제1층간절연막을 형성한 다음, 상기 제1층간절연막을 열처리하고 화학기계연마하여 평탄화시키되, 상기 마스크산화막 상측으로 얇은 두께의 제1층간절연막을 남긴 다음, 상기 제1층간절연막을 통하여 상기 반도체기판에 접속되는 콘택플러그를 형성하고 전체표면상부에 제2층간절연막인 언도프드 산화막을 형성한 다음, 상기 제2층간절연막을 통하여 상기 콘택플러그를 콘택되는 비트라인을 형성함으로써 후속열처리공정시 상기 비트라인이 변형되거나 움직이는 현상을 억제하여 반도체소자의 수율을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.A spacer insulating film is formed on a semiconductor substrate having a patterned gate electrode and a mask oxide film stack structure, a first interlayer insulating film is formed, and then the first interlayer insulating film is heat-treated and chemically polished to planarize, and then the upper side of the mask oxide film is planarized. After leaving a thin first interlayer insulating film, a contact plug connected to the semiconductor substrate is formed through the first interlayer insulating film, and an undoped oxide film, which is a second interlayer insulating film, is formed on the entire surface of the second interlayer insulating film. By forming a bit line contacting the contact plug through an insulating film, the bit line is deformed or moved in a subsequent heat treatment process, thereby improving the yield of the semiconductor device and thereby increasing the integration of the semiconductor device.
Description
본 발명은 반도체소자의 층간절연막 형성방법에 관한 것으로, 특히 반도체소자의 제조공정시 게이트전극을 형성하고 유동성이 우수한 산화계 물질로 갭필 ( gap fill ) 및 평탄화를 진행할때 후속 열공정 등에 의한 제2차 유동을 방지하여 그 상부에 형성되는 도전층의 변형 및 움직임을 차단하여 안정된 구조의 반도체소자를 형성하는 기술에 관한 것이다.The present invention relates to a method for forming an interlayer insulating film of a semiconductor device, and more particularly, to form a gate electrode during a manufacturing process of a semiconductor device, and to perform a gap fill and planarization with an oxidizing material having excellent fluidity. The present invention relates to a technology for forming a semiconductor device having a stable structure by preventing flow and blocking deformation and movement of a conductive layer formed thereon.
반도체 제품의 집적도가 높아지고패턴의 미세화가 진행됨에 따라 층간절연막의 갭필 효과와 평탄화 효과의 증대가 요구되고 있다.As the degree of integration of semiconductor products increases and the pattern becomes smaller, it is required to increase the gap fill effect and the planarization effect of the interlayer insulating film.
따라서, 우수한 갭필 특성과 평탄화특성을 동시에 만족시키다 보면 유동성이 높은 산화막계 물질을 매우 두껍게 쓸수 밖에 없다.Therefore, when satisfying the excellent gap fill characteristics and planarization characteristics at the same time, there is no choice but to use very thick oxide film material having high fluidity.
또한, 소자의 안정된 특성을 고려하다 보면 이러한 유동성이 높은 산화막을 열적으로 충분히 안정화시킬 수 없게 된다.In addition, considering the stable characteristics of the device, it is not possible to sufficiently stabilize such a high-flowing oxide film.
따라서, 이 위에 형성되는 비트라인과 같은 도전체 라인은 후속의 열공정에 의한 변형 및 움직임이 발생되어 원치않는 도전체 간의 쇼트 ( short ) 를 유발하여 전기적으로 페일 ( fail ) 이 발생된다.Accordingly, conductor lines such as bit lines formed thereon are deformed and moved by subsequent thermal processes, causing shorts between unwanted conductors, resulting in an electrical fail.
이는 이 도전체 아래의 유동성이 높은 산화막이 후속 열공정에 의하여 2차 유동 ( reflow ) 을 일으켜 직접적으로 도전체를 움직이게 하거나, 간접적으로 스트레스를 가하여 변형을 일으키기 때문이다.This is because an oxide film having high fluidity under the conductor causes secondary flow by subsequent thermal processes to directly move the conductor, or indirectly stresses it to cause deformation.
도 1 은 종래기술에 따른 반도체소자의 층간절연막 형성방법을 도시한 단면도이다.1 is a cross-sectional view showing a method for forming an interlayer insulating film of a semiconductor device according to the prior art.
먼저, 반도체기판(100) 상부에 트렌치형 소자분리막(1)을 형성한다.First, a trench type isolation layer 1 is formed on the semiconductor substrate 100.
그리고, 상기 반도체기판(100) 표면에 게이트전극(3)과 마스크 산화막(4)의 적층구조를 형성한다.A stack structure of the gate electrode 3 and the mask oxide film 4 is formed on the surface of the semiconductor substrate 100.
이때, 상기 적층구조는 전체표면상부에 게이트전극용 도전체와 마스크 산화막을 적층하고 그 상부에 게이트전극 마스크를 이용한 노광 및 현상공정으로 감광막패턴(도시안됨)을 형성하고 이를 마스크로하여 식각함으로써 형성한다.At this time, the laminated structure is formed by stacking a gate electrode conductor and a mask oxide film on the entire surface, and forming a photoresist pattern (not shown) by etching and developing using a gate electrode mask on the top thereof and etching the same as a mask. do.
그 다음, 전체표면상부에 스페이서 절연막(5)을 일정두께 형성한다.Then, the spacer insulating film 5 is formed on the entire surface at a constant thickness.
그리고, 전체표면상부에 제1층간절연막(6)을 형성한다.Then, the first interlayer insulating film 6 is formed over the entire surface.
이때, 상기 제1층간절연막(6)은 비.피.에스.지. ( boro phophos silicate glass, 이하에서 BPSG 라 함 ) 등과 같이 유동성이 우수한 산화계 절연물질로 5000 ∼ 20000 Å 정도의 두께로 형성하고 이를 열처리 및 화학기계연마 공정으로 평탄화시킨다.At this time, the first interlayer insulating film 6 is made of B.S.G. Oxide-based insulating material, such as boro phophos silicate glass, hereinafter referred to as BPSG, is formed to a thickness of 5000 to 20000 Å and is flattened by heat treatment and chemical mechanical polishing processes.
그 다음, 상기 반도체기판 상의 비트라인영역과 저장전극영역을 노출시키는 콘택홀을 형성하고 이를 매립하는 콘택플러그(10)를 형성한다.Next, a contact hole 10 exposing the bit line region and the storage electrode region on the semiconductor substrate is formed and a contact plug 10 is formed.
그리고, 전체표면상부에 제2층간절연막(7)인 제1언도프드 산화막을 형성한다.Then, a first undoped oxide film, which is the second interlayer insulating film 7, is formed over the entire surface.
그리고, 상기 비트라인 영역에 형성된 콘택플러그(10)를 노출시키는 비트라인 콘택홀(9)을 형성하고 상기 콘택플러그(10)에 접속되는 비트라인(8)을 형성한다. (도 1)A bit line contact hole 9 exposing the contact plug 10 formed in the bit line region is formed and a bit line 8 connected to the contact plug 10 is formed. (Figure 1)
상기한 바와같이 종래기술에 따른 반도체소자의 층간절연막 형성방법은, 게이트전극 상부의 층간절연막 두께가 두꺼워 후속열공정시 층간절연막의 유동성으로 인하여 그 상부에 형성된 도전층이 변형될 수 있어 반도체소자의 수율을 저하시키고 그에 따른 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.As described above, in the method for forming an interlayer insulating film of a semiconductor device according to the prior art, the thickness of the interlayer insulating film on the gate electrode is thick, so that the conductive layer formed thereon may be deformed due to the fluidity of the interlayer insulating film in a subsequent thermal process. There is a problem in that it is difficult to reduce the resulting high integration of the semiconductor device.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 게이트전극 상부의 층간절연막 두께를 일정두께 이하로 형성하여 후속 열공정으로 인한 상부 도전체의 변형이나 움직임을 방지할 수 있도록 하는 반도체소자의 층간절연막 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the interlayer insulating film may be formed to have a thickness below the predetermined thickness of the gate electrode to prevent deformation or movement of the upper conductor due to subsequent thermal processes. It is an object of the present invention to provide a method for forming an insulating film.
도 1 은 종래기술에 따른 반도체소자의 층간절연막 형성방법을 도시한 단면도.1 is a cross-sectional view showing a method for forming an interlayer insulating film of a semiconductor device according to the prior art.
도 2a 내지 도 2c 는 본 발명의 제1실시예에 따른 반도체소자의 층간절연막 형성방법을 도시한 단면도.2A to 2C are cross-sectional views showing a method for forming an interlayer insulating film of a semiconductor device according to the first embodiment of the present invention.
도 3 은 본 발명의 제2실시에에 따른 반도체소자의 층간절연막 형성방법을 도시한 단면도.3 is a cross-sectional view showing a method for forming an interlayer insulating film of a semiconductor device according to the second embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
1 : 소자분리막 2 : 소오스/드레인 접합영역1: device isolation layer 2: source / drain junction region
3 : 게이트전극 4 : 마스크산화막3: gate electrode 4: mask oxide film
5 : 스페이서 절연막 6 : 제1층간절연막5: spacer insulating film 6: first interlayer insulating film
7 : 제1언도프드 산화막 8 : 비트라인7: first undoped oxide film 8: bit line
9 : 비트라인 제2콘택홀 10 : 콘택플러그9: bit line 2nd contact hole 10: contact plug
11 ; 제2언도프드 산화막 100 : 반도체기판11; Second undoped oxide film 100: semiconductor substrate
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 층간절연막 형성방법은,In order to achieve the above object, an interlayer insulating film forming method of a semiconductor device according to the present invention,
패터닝된 게이트전극과 마스크산화막 적층구조가 구비된 반도체기판에 스페이서용 절연막을 형성하는 공정과,Forming an insulating film for a spacer on a semiconductor substrate having a patterned gate electrode and a mask oxide film stack structure;
전체표면상부에 제1층간절연막을 형성하는 공정과,Forming a first interlayer insulating film over the entire surface;
상기 제1층간절연막을 열처리하고 화학기계연마하여 평탄화시키되, 상기 마스크산화막 상부로 10 ∼ 1000 Å 두께의 제1층간절연막만을 남겨 후속 열처리공정으로 인한 상기 제1층간절연막의 리플로우를 방지하는 공정과,Heat treating and planarizing the first interlayer insulating film, leaving only the first interlayer insulating film 10-1000 Å thick over the mask oxide film to prevent reflow of the first interlayer insulating film due to a subsequent heat treatment process; ,
상기 제1층간절연막을 통하여 상기 반도체기판에 접속되는 콘택플러그를 형성하는 공정과,Forming a contact plug connected to the semiconductor substrate through the first interlayer insulating film;
전체표면상부에 제2층간절연막인 언도프드 산화막을 형성하는 공정과,Forming an undoped oxide film as a second interlayer insulating film over the entire surface;
상기 제2층간절연막을 통하여 상기 콘택플러그를 콘택되는 비트라인을 형성하는 공정을 포함하는 것을 제1특징으로한다.A first feature is that the step of forming a bit line for contacting the contact plug through the second interlayer insulating film.
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 층간절연막 형성방법은,In order to achieve the above object, an interlayer insulating film forming method of a semiconductor device according to the present invention,
패터닝된 게이트전극과 마스크산화막 적층구조가 구비된 반도체기판에 스페이서용 절연막을 형성하는 공정과,Forming an insulating film for a spacer on a semiconductor substrate having a patterned gate electrode and a mask oxide film stack structure;
전체표면상부에 제1층간절연막을 형성하는 공정과,Forming a first interlayer insulating film over the entire surface;
상기 제1층간절연막을 열처리하고 상기 마스크산화막을 노출시때까지 화학기계연마공정을 실시하여 후속 열처리공정으로 인한 상기 제1층간절연막의 리플로우를 방지하는 공정과,Heat treating the first interlayer insulating film and performing a chemical mechanical polishing process until the mask oxide film is exposed, thereby preventing reflow of the first interlayer insulating film due to a subsequent heat treatment process;
전체표면상부에 제2층간절연막인 언도프드 산화막을 형성하는 공정과,Forming an undoped oxide film as a second interlayer insulating film over the entire surface;
상기 언도프드 산화막 및 제1층간절연막을 통하여 상기 반도체기판에 접속되는 콘택플러그를 형성하는 공정과,Forming a contact plug connected to the semiconductor substrate through the undoped oxide film and the first interlayer insulating film;
전체표면상부에 제3층간절연막인 다른 언도프드 산화막을 형성하는 공정과,Forming another undoped oxide film on the entire surface as a third interlayer insulating film;
상기 제3층간절연막을 통하여 상기 콘택플러그를 콘택되는 비트라인을 형성하는 공정을 포함하는 것을 제2특징으로한다.A second feature is the step of forming a bit line for contacting the contact plug through the third interlayer insulating film.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c 는 본 발명의 실시예에 따른 반도체소자의 층간절연막 형성방법을 도시한 단면도이다.2A to 2C are cross-sectional views illustrating a method for forming an interlayer insulating film of a semiconductor device according to an embodiment of the present invention.
먼저, 반도체기판(100) 상부에 트렌치형 소자분리막(1)을 형성한다.First, a trench type isolation layer 1 is formed on the semiconductor substrate 100.
그리고, 상기 반도체기판(100) 표면에 게이트전극(3)과 마스크 산화막(4)의 적층구조를 형성한다.A stack structure of the gate electrode 3 and the mask oxide film 4 is formed on the surface of the semiconductor substrate 100.
이때, 상기 적층구조는 전체표면상부에 게이트전극용 도전체와 마스크 산화막을 적층하고 그 상부에 게이트전극 마스크를 이용한 노광 및 현상공정으로 감광막패턴(도시안됨)을 형성하고 이를 마스크로하여 식각함으로써 형성한다.At this time, the laminated structure is formed by stacking a gate electrode conductor and a mask oxide film on the entire surface, and forming a photoresist pattern (not shown) by etching and developing using a gate electrode mask on the top thereof and etching the same as a mask. do.
그리고, 상기 마스크산화막(4)은 플라즈마증착 산화막, O3-TEOS ( ozone - Tetra ethyl ortho silicate ), 질화막, 산화질화막, LP-TEOS ( low pressure - Tetra ethyl ortho silicate ), HTO ( high temperature oxide ) 또는 MTO ( middle temperature oxide ) 등과 같은 물질로 500 ∼ 2000 Å 두께 형성한다.The mask oxide film 4 may include a plasma deposition oxide film, an O 3 -TEOS (ozone-tetra ethyl ortho silicate), a nitride film, an oxynitride film, LP-TEOS (low pressure-Tetra ethyl ortho silicate), HTO (high temperature oxide) Or 500 to 2000 mm thick with a material such as MTO (middle temperature oxide).
그 다음, 전체표면상부에 스페이서 절연막(5)을 일정두께 형성한다.Then, the spacer insulating film 5 is formed on the entire surface at a constant thickness.
그리고, 전체표면상부에 제1층간절연막(6)을 형성한다. 이때, 상기 제1층간절연막(6)은 BPSG 등과 같이 유동성이 우수한 산화계 절연물질로 5000 ∼ 20000 Å 정도의 두께로 형성한다.Then, the first interlayer insulating film 6 is formed over the entire surface. At this time, the first interlayer insulating film 6 is formed of an oxide-based insulating material having excellent fluidity such as BPSG and the like to have a thickness of about 5000 to 20,000 kPa.
그리고, 상기 제1층간절연막(6)을 실온 ∼ 840 ℃ 온도에서 열처리하여 플로우시켜 평탄화시킨다.Then, the first interlayer insulating film 6 is heated by heat treatment at room temperature to 840 ° C. to be flattened.
그 다음, 상기 게이트전극(3) 상측의 제1층간절연막(6)이 10 ∼ 1000 Å 두께 남도록 화학기계연마 ( chemical mechenical polishing, 이하에서 CMP 라 함 ) 하여 평탄화시킨다. 이때, 상기 CMP 공정은 에치백공정으로 대신할 수도 있다. (도 2a, 도 2b)Next, the first interlayer insulating film 6 on the upper side of the gate electrode 3 is planarized by chemical mechanical polishing (hereinafter referred to as CMP) so that the thickness of the first interlayer insulating film 6 remains 10 to 1000 Å. In this case, the CMP process may be replaced by an etch back process. (FIG. 2A, FIG. 2B)
그 다음, 상기 반도체기판 상의 비트라인영역과 저장전극영역을 노출시키는 콘택홀을 형성하고 이를 매립하는 콘택플러그(10)를 형성한다.Next, a contact hole 10 exposing the bit line region and the storage electrode region on the semiconductor substrate is formed and a contact plug 10 is formed.
그리고, 전체표면상부에 제2층간절연막(7)인 제1언도프드 산화막을 형성한다.Then, a first undoped oxide film, which is the second interlayer insulating film 7, is formed over the entire surface.
이때, 상기 언도프드 산화막은 LP-TEOS ( low pressure - Tetra ethyl ortho silicate ), LTO ( low temperature oxide ) 또는 MTO ( middle temperature oxide ), PE-TEOS ( plasma enhanced - Tetra ethyl ortho silicate ), O3-TEOS ( ozone - Tetra ethyl ortho silicate ) 또는 SOG ( spin on glass ) 등과 같은 물질로 형성한다.In this case, the undoped oxide film is LP-TEOS (low pressure-Tetra ethyl ortho silicate), LTO (low temperature oxide) or MTO (middle temperature oxide), PE-TEOS (plasma enhanced-Tetra ethyl ortho silicate), O 3- It is formed from materials such as ozone-tetra ethyl ortho silicate (TEOS) or spin on glass (SOG).
그리고, 상기 비트라인 영역에 형성된 콘택플러그(10)를 노출시키는 비트라인 콘택홀(9)을 형성하고 상기 콘택플러그(10)에 접속되는 비트라인(8)을 형성한다. (도 2c)A bit line contact hole 9 exposing the contact plug 10 formed in the bit line region is formed and a bit line 8 connected to the contact plug 10 is formed. (FIG. 2C)
도 3 은 본 발명의 제2실시예에 따른 반도체소자의 층간절연막 형성방법을 도시한 단면도이다.3 is a cross-sectional view illustrating a method for forming an interlayer insulating film of a semiconductor device according to a second embodiment of the present invention.
먼저, 반도체기판(100) 상부에 트렌치형 소자분리막(1)을 형성한다.First, a trench type isolation layer 1 is formed on the semiconductor substrate 100.
그리고, 상기 반도체기판(100) 표면에 게이트전극(3)과 마스크 산화막(4)의 적층구조를 형성한다.A stack structure of the gate electrode 3 and the mask oxide film 4 is formed on the surface of the semiconductor substrate 100.
이때, 상기 적층구조는 전체표면상부에 게이트전극용 도전체와 마스크 산화막을 적층하고 그 상부에 게이트전극 마스크를 이용한 노광 및 현상공정으로 감광막패턴(도시안됨)을 형성하고 이를 마스크로하여 식각함으로써 형성한다.At this time, the laminated structure is formed by stacking a gate electrode conductor and a mask oxide film on the entire surface, and forming a photoresist pattern (not shown) by etching and developing using a gate electrode mask on the top thereof and etching the same as a mask. do.
그리고, 상기 마스크산화막(4)은 플라즈마증착 산화막, O3-TEOS, 질화막, 산화질화막, LP-TEOS, HTO 또는 MTO 등과 같은 물질로 500 ∼ 2000 Å 두께 형성한다.The mask oxide film 4 is formed to have a thickness of 500 to 2000 mm 3 using a material such as a plasma deposition oxide film, an O 3 -TEOS, a nitride film, an oxynitride film, LP-TEOS, HTO, or MTO.
그 다음, 전체표면상부에 스페이서 절연막(5)을 일정두께 형성한다.Then, the spacer insulating film 5 is formed on the entire surface at a constant thickness.
그리고, 전체표면상부에 제1층간절연막(6)을 형성한다. 이때, 상기 제1층간절연막(6)은 BPSG 등과 같이 유동성이 우수한 산화계 절연물질로 5000 ∼ 20000 Å 정도의 두께로 형성한다.Then, the first interlayer insulating film 6 is formed over the entire surface. At this time, the first interlayer insulating film 6 is formed of an oxide-based insulating material having excellent fluidity such as BPSG and the like to have a thickness of about 5000 to 20,000 kPa.
그리고, 상기 제1층간절연막(6)을 실온 ∼ 840 ℃ 온도에서 열처리하여 플로우시켜 평탄화시킨다.Then, the first interlayer insulating film 6 is heated by heat treatment at room temperature to 840 ° C. to be flattened.
그 다음, 상기 게이트전극(3) 상측의 마스크산화막(4) 상측으로 상기 제1층간절연막(6)을 10 ∼ 1000 Å 두께 남기는 CMP 공정으로 평탄화시켜 상기 게이트전극(3)과 마스크산화막(4) 적층구조 사이를 매립하는 제1층간절연막(6)을 형성한다. 이때, 상기 CMP 공정은 에치백공정으로 대신할 수도 있다.Then, the gate electrode 3 and the mask oxide film 4 are planarized by a CMP process leaving the first interlayer insulating film 6 10 to 1000 Å thick above the mask oxide film 4 above the gate electrode 3. A first interlayer insulating film 6 is formed which fills between the stacked structures. In this case, the CMP process may be replaced by an etch back process.
그리고, 전체표면상부에 제2층간절연막(7)인 제1언도프드 산화막을 형성한다.Then, a first undoped oxide film, which is the second interlayer insulating film 7, is formed over the entire surface.
그 다음, 상기 반도체기판 상의 비트라인영역과 저장전극영역을 노출시키는 콘택홀을 형성하고 이를 매립하는 콘택플러그(10)를 형성한다.Next, a contact hole 10 exposing the bit line region and the storage electrode region on the semiconductor substrate is formed and a contact plug 10 is formed.
그리고, 전체표면상부에 제3층간절연막(11)인 제2언도프드 산화막을 형성한다.A second undoped oxide film, which is the third interlayer insulating film 11, is formed over the entire surface.
그리고, 상기 비트라인 영역에 형성된 콘택플러그(10)를 노출시키는 비트라인 콘택홀(9)을 형성하고 상기 콘택플러그(10)에 접속되는 비트라인(8)을 형성한다. (도 3)A bit line contact hole 9 exposing the contact plug 10 formed in the bit line region is formed and a bit line 8 connected to the contact plug 10 is formed. (Figure 3)
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 층간절연막 형성방법은, 유동성이 우수한 절연물질을 게이트전극 사이에 매립하고 게이트전극 상측에 얇게 형성하여 후속열공정으로 인한 유동성으로 상부 도전층이 변형되거나 움직이는 경우를 억제하거나, 유동성이 우수한 절연물질로 게이트전극 사이만을 매립하고 게이트전극 상측은 언도프드 산화막을 형성하여 후속열처리공정시 유동성이 우수한 절연물질의 리플로우 현상을 방지하여 그 상측에 구비되는 상부 도전층의 변형이나 움직임을 억제함으로써 반도체소자의 수율을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 효과를 제공한다.As described above, in the method of forming the interlayer insulating film of the semiconductor device according to the present invention, an insulating material having excellent fluidity is buried between the gate electrodes and thinly formed on the upper side of the gate electrode, so that the upper conductive layer is deformed due to fluidity due to subsequent thermal processes. The upper portion of the upper portion provided to prevent the reflow phenomenon of the insulating material having excellent fluidity during the subsequent heat treatment process by suppressing the case of movement or filling only the gate electrode with an insulating material having excellent fluidity and forming an undoped oxide layer on the upper side of the gate electrode. By suppressing deformation or movement of the conductive layer, it is possible to improve the yield of the semiconductor device and thereby to provide high integration of the semiconductor device.
Claims (7)
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