KR19980060885A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR19980060885A KR19980060885A KR1019960080252A KR19960080252A KR19980060885A KR 19980060885 A KR19980060885 A KR 19980060885A KR 1019960080252 A KR1019960080252 A KR 1019960080252A KR 19960080252 A KR19960080252 A KR 19960080252A KR 19980060885 A KR19980060885 A KR 19980060885A
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- insulating film
- forming
- semiconductor substrate
- semiconductor device
- interlayer insulating
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 40
- 239000011229 interlayer Substances 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000010410 layer Substances 0.000 claims abstract description 12
- 238000002955 isolation Methods 0.000 claims abstract description 3
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 13
- 238000005498 polishing Methods 0.000 claims description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims 2
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 claims 2
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 claims 2
- 239000000377 silicon dioxide Substances 0.000 claims 2
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 238000003860 storage Methods 0.000 abstract description 11
- 230000010354 integration Effects 0.000 abstract description 6
- 238000005516 engineering process Methods 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
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Abstract
본 발명은 반도체 소자의 제조방법에 관한 것으로, 반도체 기판에 소자분리절연막 및 워드라인을 형성하고 상기 반도체 기판의 전체 표면 상부에 제 1 절연막을 형성한 다음, 상기 제 1 절연막 상부에 제 1 층간절연막을 형성하여 평탄화시키고 상기 제 1 층간절연막을 CMP 하되, 상기 제 1 절연막이 노출될 때까지 실시한 다음, 상기 제 1 절연막 상부에 제 2 절연막을 형성하고 상기 반도체 기판에 접속되는 비트라인을 형성한 다음, 상기 반도체 기판의 전체 표면 상부에 제 3 절연막을 일정 두께 형성하고 상기 반도체 기판 상부에 제 2 층간절연막을 형성하여 평탄화 시킨 다음, 상기 제 2 층간절연막을 CMP 하되, 상기 제 3 절연막이 노출될 때까지 실시하고 상기 반도체 기판 상부에 제 4 절연막을 형성하는 공정으로 워드라인과 비트라인, 비트라인과 저장전극 사이의 절연층 두께를 얇게 하여 후속공정을 용이하게 함으로써 반도체 소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체 소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for manufacturing a semiconductor device, comprising: forming a device isolation insulating film and a word line on a semiconductor substrate, forming a first insulating film over the entire surface of the semiconductor substrate, and then forming a first interlayer insulating film over the first insulating film. And planarize to form the first interlayer insulating film CMP until the first insulating film is exposed, and then form a second insulating film on the first insulating film and a bit line connected to the semiconductor substrate. When the third insulating film is formed on the entire surface of the semiconductor substrate by a predetermined thickness and the second interlayer insulating film is formed on the semiconductor substrate to be planarized, the second interlayer insulating film is CMP, but when the third insulating film is exposed. Word line, bit line, bit line and before storage An improved follow-up characteristic of the semiconductor device easier by having a step and reliability by a thin insulation layer thickness between and technology that enables high integration of the semiconductor device thereof.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 반도체 소자의 층간 절연막을 형성하는 방법에 있어서, 금속배선 형성전 도전배선간의 층간절연막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming an interlayer insulating film of a semiconductor device, the method for forming an interlayer insulating film between conductive wirings before forming metal wirings.
반도체 소자의 고집적화에 따라 소자 표면의 요철은 더욱 심화되어 고단차의 표면을 절연막으로 채우는 평탄화 기술은 반도체 소자 제조에 있어 중요한 기술중 하나로 대두되고 있다.As the integration of semiconductor devices increases, the unevenness of the surface of the device is further intensified, and the planarization technology for filling the surface of the high step with an insulating film is one of the important technologies in the manufacture of semiconductor devices.
일반적으로, 금속배선 이전의 도전배선간 절연막으로서 또한 기 형성된 도전배선으로부터 기인된 표면을 평탄화하기 위해서는, 고농도의 붕소(B) 및 인(P)을 첨가한 비.피.에스.지. (Boro Phospho Silicate Glass, 이하에서 BPSG라 함) 산화막을 도전배선 상부에 증착하여 고온에서 리플로우(reflow) 하여 평탄화하는 방법을 이용한다.Generally, in order to planarize the surface resulting from the previously formed conductive wiring as the insulating film between the conductive wirings before the metal wiring, B.P.S.G. is added with high concentrations of boron (B) and phosphorus (P). (Boro Phospho Silicate Glass, hereinafter referred to as BPSG) An oxide film is deposited on the conductive wiring and reflowed at a high temperature to planarize it.
그런데 소자의 집적도 증가에 따라 도전배선 즉 예를 들어 워드라인(word line) 또는 비트라인(bit line)을 다결정 실리콘과 텅스텐실리사이드의 적층구조인 폴리사이드 구조를 채용함에 따라 이들 도전배선 형성 후 표면단차를 완화하기 위하여 증착되는 BPSG 산화막의 두께로 증착시켜야만 한다. 이와 더불어 비트라인 콘택이나 전하저장 전극 콘택의 크기도 소자 집적도가 증가함에 따라 감소하므로, 콘택의 에스펙트비(aspect ratio)가 증가하는 결과를 가져온다.However, as the degree of integration of the device increases, the surface difference after forming the conductive wiring, for example, the word line or the bit line, is adopted as a polyside structure, which is a laminated structure of polycrystalline silicon and tungsten silicide. In order to mitigate, the thickness of the deposited BPSG oxide must be deposited. In addition, the size of the bit line contact or the charge storage electrode contact also decreases as the device density increases, resulting in an increase in the aspect ratio of the contact.
그리고, 상기 에스펙트비가 증가하면 건식 식각 공정에서 콘택홀이 완전히 식각되지 않거나, 식각후 콘택홀 하부에 존재하는 반응 잔류물 세정이 완벽히 이루어지지 않으므로 반도체 소자의 제작이 불가능하거나, 소자 작동에 중대한 결함을 초래할 수 있다는 단점이 있다.In addition, if the aspect ratio is increased, the contact hole may not be fully etched in the dry etching process, or the reaction residues existing under the contact hole may not be completely cleaned. It has the disadvantage that it can cause.
도 1은 종래 기술에 따른 반도체 소자의 제조방법을 도시한 단면도로서, BPSG 산화막을 이용한 층간절연막 평탄화 방법에 의해 형성된 소자를 도시한다.1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the prior art, showing a device formed by the method of planarizing an interlayer insulating film using a BPSG oxide film.
먼저, 반도체 기판(100) 상부에 필드산화막(1)을 형성하여 소자를 분리하고 그 후 게이트 산화막(3)을 형성하고 제 1 도전층으로 다결정 실리콘층 패턴을 형성하여 일련의 워드라인(4)을 형성한다.First, the field oxide film 1 is formed on the semiconductor substrate 100, and the device is separated. Then, the gate oxide film 3 is formed and a polycrystalline silicon layer pattern is formed as the first conductive layer. To form.
그리고, 상기 워드라인(4) 양측의 반도체 기판에 엘.디.디. (lightly doped drain, 이하에서 LDD라 함) 구조의 소오스/드레인 전극(2)을 형성한다. 후속공정으로 워드라인(4) 측벽에 산화막 스페이서를 형성하여 통상의 모스전계 효과 트랜지스터를 구성한다.In addition, the D.D.D. semiconductor substrates on both sides of the word line 4 are formed. A source / drain electrode 2 having a lightly doped drain (hereinafter referred to as LDD) structure is formed. In a subsequent step, an oxide spacer is formed on the sidewall of the word line 4 to form a conventional MOS field effect transistor.
이후 상기 구조 전표면에 제 1 층간절연막(도시안됨)으로 사용될 BPSG 산화막을 증착하기에 앞서 불순물로 사용된 B, P 등이 워드라인으로의 확산을 방지하기 위한 제 1 산화막(5)을 증착한다.Thereafter, before depositing the BPSG oxide film to be used as the first interlayer insulating film (not shown) on the entire surface of the structure, the first oxide film 5 is deposited to prevent diffusion of B, P and the like into the word line. .
그리고, 제 1 층간절연막(6)을 BPSG 산화막으로 형성하고, 고온 열처리 공정으로 리플로우시켜 평탄화한다.Then, the first interlayer insulating film 6 is formed of a BPSG oxide film, and reflowed by a high temperature heat treatment process to planarize it.
그 다음에, 상기 BPSG 산화막(6) 상부에 다시 제 2 산화막(7)을 증착한다. 계속하여, 비트라인 콘택홀(20)을 건식 식각방법으로 형성하고 제 2 도전배선인 다결정 실리콘으로 된 비트라인(8)을 형성한다.Then, the second oxide film 7 is deposited again on the BPSG oxide film 6. Subsequently, the bit line contact hole 20 is formed by a dry etching method, and a bit line 8 made of polycrystalline silicon, which is a second conductive wiring, is formed.
그리고, 상기 비트라인(8) 상부에 B, P의 확산을 방지하기 위한 제 3 산화막(9), 제 2 층간절연막(10)인 BPSG 산화막의 증착하고 이를 고온에서 리플로우시킨 다음, 제 4 산화막(11)을 증착한다.Then, a BPSG oxide film, which is a third oxide film 9 and a second interlayer insulating film 10, is deposited on the bit line 8 to prevent diffusion of B and P, and reflowed at a high temperature. (11) is deposited.
그 다음에, 저장전극 콘택홀(40)을 형성하고 이를 통하여 상기 소오스/드레인 전극(2)과 접촉되는 제 3 도전배선인 저장전극(12)을 형성한다.Next, a storage electrode contact hole 40 is formed and a storage electrode 12, which is a third conductive wiring in contact with the source / drain electrode 2, is formed through the storage electrode contact hole 40.
이와 같은 종래 기술에 따른 반도체 소자의 제조방법은, 소자 집적도가 증가함에 따른 높은 에스펙트비로 인하여 콘택 식각공정시 어려우며, 식각공정후 콘택홀의 기저부에 존재하는 반응 잔유물들이 후속 세정공정으로 용이하게 제거할 수 없어 소자의 특성 및 신뢰성을 저하시키고 그에 따른 반도체 소자의 고집적화를 어렵게 하는 문제점이 있다.Such a method of manufacturing a semiconductor device according to the prior art is difficult in the contact etching process due to the high aspect ratio as the device density increases, and the reaction residues present at the base of the contact hole after the etching process can be easily removed by a subsequent cleaning process. There is a problem in that it is difficult to reduce the characteristics and reliability of the device and thereby high integration of the semiconductor device.
따라서, 본 발명은 상기한 종래 기술의 문제점을 해결하기 위하여, 워드라인이나 비트라인 상부에 형성된 절연막 간의 연마속도 차이를 이용하여 단차를 완화시킴으로써 후속공정을 용이하게 하여 반도체 소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체 소자의 고집적화를 가능하게 하는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above-mentioned problems of the prior art, the step is alleviated by using the difference in polishing speed between the insulating films formed on the word line or the bit line, thereby facilitating subsequent processes, thereby improving the characteristics and reliability of the semiconductor device. It is an object of the present invention to provide a method for manufacturing a semiconductor device that enables high integration of the semiconductor device.
도 1은 종래 기술에 따른 반도체 소자의 제조방법을 도시한 단면도.1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the prior art.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 도시한 단면도.2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 : 반도체기판2 : 소오스/드레인 전극1: semiconductor substrate 2: source / drain electrodes
3 : 게이트산화막4 : 워드라인3: gate oxide film 4: word line
5 : 제 1 산화막6 : 제 1 층간절연막5: first oxide film 6: first interlayer insulating film
7 : 제 2 산화막8 : 비트라인7: second oxide film 8: bit line
9 : 제 3 산화막10 : 제 2 층간절연막9: third oxide film 10 second interlayer insulating film
11 : 제 4 산화막12 : 저장전극11: fourth oxide film 12: storage electrode
20, 60 : 비트라인 콘택홀40 : 저장전극 콘택홀20, 60: bit line contact hole 40: storage electrode contact hole
이상의 목적을 달성하기 위해 본 발명에 따른 반도체 소자의 제조방법은, 반도체 기판에 소자분리절연막 및 워드라인을 형성하는 공정과, 상기 반도체 기판의 전체 표면 상부에 제 1 절연막을 형성하는 공정과, 상기 제 1 절연막 상부에 제 1 층간절연막을 형성하여 평탄화시키는 공정과, 상기 제 1 층간절연막을 CMP 하되, 상기 제 1 절연막이 노출될 때까지 실시하는 공정과, 상기 제 1 절연막 상부에 제 2 절연막을 형성하는 공정과, 상기 반도체 기판에 접속되는 비트라인을 형성하는 공정과, 상기 반도체 기판의 전체 표면 상부에 제 3 절연막을 일정 두께 형성하는 공정과, 상기 반도체 기판 상부에 제 2 층간절연막을 형성하여 평탄화 시키는 공정과, 상기 제 2 층간절연막을 CMP 하되, 상기 제 3 절연막이 노출될 때까지 실시하는 공정과, 상기 반도체 기판 상부에 제 4 절연막을 형성하는 공정을 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes forming a device isolation insulating film and a word line on a semiconductor substrate, forming a first insulating film over the entire surface of the semiconductor substrate, and Forming and planarizing a first interlayer insulating film over the first insulating film; and performing a CMP of the first interlayer insulating film until the first insulating film is exposed; and a second insulating film over the first insulating film. Forming a bit line connected to the semiconductor substrate; forming a third thickness of the third insulating film over the entire surface of the semiconductor substrate; and forming a second interlayer insulating film over the semiconductor substrate. Planarizing, performing a CMP of the second interlayer insulating film until the third insulating film is exposed, and the semiconductor substrate It characterized in that it comprises a step of forming a fourth insulating film in the portion.
한편, 이상의 목적을 달성하기 위한 본 발명의 원리는, 도전층 간의 절연을 목적으로 형성하는 층간절연막과 같은 다수의 절연층 간의 연마속도 차이를 이용하여 상부구조물과 하부구조물과의 단차를 감소시킴으로써 전체적인 소자의 두께를 감소시켜 후속공정을 용이하게 할 수 있도록 에스펙트비를 감소시키는 것이다.On the other hand, the principle of the present invention for achieving the above object is to reduce the step between the upper structure and the lower structure by using the difference in polishing rate between a plurality of insulating layers, such as an interlayer insulating film formed for the purpose of insulating between conductive layers. It is to reduce the aspect ratio to reduce the thickness of the device to facilitate the subsequent process.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 도시한 단면도이다.2A through 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
먼저, 반도체 기판(100) 상부에 필드산화막(1)을 이용하여 소자를 분리하고 게이트 산화막(3)을 형성하고 다결정 실리콘층 또는 다결정 실리콘과 텅스텐 실리사이드의 적층구조로 형성된 워드라인(4)을 형성한 후, 워드라인(4) 양측의 반도체 기판(100)에 LDD 구조의 소오스/드레인 전극(2)을 형성하고, 워드라인(4) 측벽에 산화막 스페이서(도시안됨)를 형성하여 통상의 모스전계효과 트랜지스터를 구성한다.First, the device is separated using the field oxide film 1 on the semiconductor substrate 100 to form a gate oxide film 3, and a word line 4 formed of a polycrystalline silicon layer or a laminated structure of polycrystalline silicon and tungsten silicide is formed. After that, a source / drain electrode 2 having an LDD structure is formed on the semiconductor substrate 100 at both sides of the word line 4, and an oxide spacer (not shown) is formed on the sidewall of the word line 4 to form a normal MOS field. Configure the effect transistor.
그리고, 상기 구조 전표면에 B, P의 확산방지용인 제 1 산화막(5)을 증착하고 제 1 층간절연막(6)을 BPSG 산화막으로 형성하고 고온 열처리 공정으로 리플로우시켜 평탄화시킨다.Then, the first oxide film 5 for preventing diffusion of B and P is deposited on the entire surface of the structure, and the first interlayer insulating film 6 is formed of a BPSG oxide film and reflowed by a high temperature heat treatment process to planarize it.
여기서, 상기 제 1 산화막(5)은 SiH4와 NO2를 이용하여 700 ~ 800 ℃에서 증착시키거나, TEOS와 O2를 반응가스로 이용하여 600 ~ 750 ℃에서 증착시키며, 두께는 500 ~ 2000 Å 정도로 한다. (도 2a)Here, the first oxide film 5 is deposited at 700 ~ 800 ℃ using SiH 4 and NO 2 , or deposited at 600 ~ 750 ℃ using TEOS and O 2 as a reaction gas, the thickness is 500 ~ 2000 Do it enough. (FIG. 2A)
그 다음에, 상기 CMP 공정으로 상기 제 1 층간절연막(6)를 상기 제 1 산화막(5)이 노출될 때까지 연마한다. 이때, 상기의 제 1 산화막(5)은 BPSG에 비하여 CMP 연마속도가 2 / 1 ~ 3 / 1 정도 느리므로 연마정지층 역할을 한다. (도 2b)Then, the first interlayer insulating film 6 is polished by the CMP process until the first oxide film 5 is exposed. At this time, since the CMP polishing rate is about 2/1 to 3/1 slower than the BPSG, the first oxide film 5 serves as the polishing stop layer. (FIG. 2B)
그리고, 상기 제 1 층간절연막(6) 상부에 제 2 산화막(7)을 증착한 후 비트라인 콘택홀(60)과 비트라인(8)을 형성한다.After the second oxide layer 7 is deposited on the first interlayer insulating layer 6, the bit line contact hole 60 and the bit line 8 are formed.
그 다음에, 전체 표면 상부에 제 3 산화막(9)을 형성하고 그 상부에 제 2 층간절연막(10)인 BPSG 산화막을 형성한다.Next, a third oxide film 9 is formed over the entire surface, and a BPSG oxide film, which is the second interlayer insulating film 10, is formed thereon.
그리고, 상기 제 2 층간절연막(10)을 고온에서 리플로우시켜 평탄화시킨다.The second interlayer insulating film 10 is reflowed at a high temperature to be flattened.
그리고, 상기 제 2 층간절연막(10)을 CMP 공정으로 연마하되, 상기 제 3 산화막(9)이 노출될 때까지 실시한다.The second interlayer insulating film 10 is polished by a CMP process until the third oxide film 9 is exposed.
그 다음에, 그 상부에 제 4 산화막(11)을 증착한다.Then, a fourth oxide film 11 is deposited on it.
후속공정으로 전하저장 전극용 콘택홀을 형성하고 전하저장전극을 형성한다.In a subsequent process, a contact hole for a charge storage electrode is formed and a charge storage electrode is formed.
이상에서 설명한 바와 같이 본 발명에 따른 반도체 소자의 제조방법은, 전하저장 전극의 콘택 식각시 기존 방법에 비하여 CMP로 연마된 BPSG 산화막 두께만큼 콘택 깊이가 감소하는 효과가 있으므로 에스펙트비를 감소시켜 콘택식각공정을 용이하게 할 수 있다. 또한, 셀부와 주변회로부 간의 단차가 감소되어 후속공정에서의 노광공정시 공정마진을 증가시킬 수 있다. 이로 인하여, 반도체 소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체 소자의 고집적화를 가능하게 하는 효과가 있다.As described above, the method of fabricating a semiconductor device according to the present invention has the effect of reducing the contact depth by the thickness of the BPSG oxide film polished with CMP, compared to the conventional method, when the contact storage of the charge storage electrode is performed. Etching process can be facilitated. In addition, the step difference between the cell portion and the peripheral circuit portion is reduced to increase the process margin during the exposure process in the subsequent process. Therefore, there is an effect of improving the characteristics and reliability of the semiconductor device and thereby enabling high integration of the semiconductor device.
Claims (14)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100680938B1 (en) * | 2000-05-31 | 2007-02-08 | 주식회사 하이닉스반도체 | Method of making metal word line and bit line in semiconductor device |
| KR100680937B1 (en) * | 2000-05-31 | 2007-02-08 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100680938B1 (en) * | 2000-05-31 | 2007-02-08 | 주식회사 하이닉스반도체 | Method of making metal word line and bit line in semiconductor device |
| KR100680937B1 (en) * | 2000-05-31 | 2007-02-08 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
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