KR100223323B1 - The manufacturing method of semiconductor device - Google Patents
The manufacturing method of semiconductor device Download PDFInfo
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- KR100223323B1 KR100223323B1 KR1019950048045A KR19950048045A KR100223323B1 KR 100223323 B1 KR100223323 B1 KR 100223323B1 KR 1019950048045 A KR1019950048045 A KR 1019950048045A KR 19950048045 A KR19950048045 A KR 19950048045A KR 100223323 B1 KR100223323 B1 KR 100223323B1
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- metal wiring
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- forming
- interlayer insulating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Microelectronics & Electronic Packaging (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로서, 금속배선의 일부 두께를 그 하부의 층간절연막에 묻히도록 하여 상기 층간절연막의 평면 위초 돌출된 제1금속배선의 높이로 감소시켰으므로, 금속배선에 의한 단차가 감소되므로 평탄도가 향상되어 후속 포토 리소그래피 공정시 단차에 의한 나칭 발생이 감소되고, 제1금속배선과 제2금속 배선 사이의 단락이 방지하고, 배선의 단선도 방지되며, 상기의 방법을 제2금속배선 증착과 보호막(passivation)공정에도 적용하여 보호막의 보이드 발생을 억제하고 평탄화를 향상시켜(package) 공정진행시 보호막의 균열 발생을 억제할 수 있어 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein the thickness of a metal wiring is buried in a lower interlayer insulating film to reduce the height of the first metal wiring protruding above the plane of the interlayer insulating film. The flatness is improved because the step is reduced, thus reducing the occurrence of nagging due to the step in the subsequent photolithography process, preventing short circuit between the first metal wiring and the second metal wiring, and preventing the disconnection of the wiring. It is also applied to the second metal wiring deposition and passivation process to suppress void generation of the passivation layer and to improve planarization to suppress cracking of the passivation layer during the process, thereby improving process yield and device operation reliability. Can be.
Description
제 1a도 내지 제 1e도는 본발명에 따른 반도체소자의 제조 공정도.1A to 1E are manufacturing process diagrams of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 제1층간절연막 2 : 다결정실리콘층1: first interlayer insulating film 2: polycrystalline silicon layer
3 : 제2층간절연막 4 : 감광막패턴3: second interlayer insulating film 4: photosensitive film pattern
5 : 홈 6 : 콘택홀5: home 6: contact hole
7 : 제1금속막 8 : 제3층간절연막7: first metal film 8: third interlayer insulating film
8A : 장벽절연막 8B : 평탄화막8A: barrier insulation film 8B: planarization film
9 : 제2금속막9: second metal film
본 발명은 반도체소자의 제조방법에 관한 것으로서 특히 메모리 소자의 금속배선을 그 하부에 층간절연막에 형성된 홈에 일부 두꼐를 묻어 단차를 감소시켜 평탄화가 용이하고 나칭에 의한 불량 발생을 방지하며, 보호막의 평탄도를 향상시켜 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, the metal wiring of the memory device is partially buried in the grooves formed in the interlayer insulating film, thereby reducing the step difference, thereby making it easier to planarize and preventing the occurrence of defects due to nagging. The present invention relates to a method for manufacturing a semiconductor device capable of improving flatness to improve process yield and device operation reliability.
집적도가 낮은 반도체소자는 단차가 작아 각 도전층들의 패턴닝이나 평탄화에 별다른 문제점이 없었으나, 소자가 고집적화되어 각층들간의 단차 및 적층되는 막의 수가 증가되면 소자의 제조 공정에서 나칭이나 단선등의 불량들이 발생하게 되며, 이를 방지하기 위하여 적층막들의 상부를 평탄화하는 평탄화공정이 공정수율 및 소자의 신뢰성에 중요한 영향을 미치게 된다.The low integration semiconductor device has no problem in patterning or planarization of each conductive layer due to the small step. However, when the device is highly integrated and the number of steps and stacked films between the layers increases, defects such as unsymmetry or disconnection occur in the manufacturing process of the device. In order to prevent this, the planarization process of planarizing the top of the stacked layers has an important effect on the process yield and the reliability of the device.
현재 1M DRAM 이상의 소자에서는 다량의 불순물을 함유하여 유동성이 우수하고 화학기상증착(chemical vapor dopodition; 이하 CVD라 칭함) 방법으로 형성되고 유동성이 우수하여 단차피복성이 향상되는 비.피.에스.지(Boro Phospho Silicate Glass; 이하 BPSG라 칭함)나 테오스(Tetra etchyl orthor silicate; 이하 TEOS라 칭함) 산화막등을 평탄화막으로 널리 사용하고 있다. 그러나 상기의 평탄화막들은 우수한 유동성에도 불구하고 평탄화의 정도에 한계가 있으며, 불순물이 다량으로 포함되어있어 또 다른 문제점을 갖고 있다.Currently, devices containing 1M DRAM or more contain a large amount of impurities, which are excellent in fluidity, formed by chemical vapor deposition (CVD), and excellent in fluidity to improve step coverage. (Boro Phospho Silicate Glass; hereinafter referred to as BPSG) and Teos (Tetra etchyl orthor silicate; hereinafter called TEOS) oxide films are widely used as planarization films. However, the above planarization films have a limit in the degree of planarization in spite of their excellent fluidity.
또한 256M DRAM 이상의 초고집적 소자에서는 평탄화막의 표면을 연마제를 사용하여 기계적으로 갈아내는 씨.엠.피(chemical mechanical polishing; 이하 CMP라 칭함) 방법이 견구되고 있다.In addition, in the ultra-high density device of 256M DRAM or more, a method of chemical mechanical polishing (hereinafter referred to as CMP) which mechanically grinds the surface of the planarization film using an abrasive has been found.
그러나 상기와 같은 CMP 공정은 기계적인 한께 때문에 평탄화의 균일성이 떨어지는 문제점이 있다.However, the CMP process as described above has a problem in that the uniformity of the planarization is poor due to the mechanical thickness.
도시되어있지는 않으나, 종래 기술에 따른 반도체소자의 금속배선간 절연막에 관하여 살펴보면 다음과 같다.Although not shown, the insulating film between metal wirings of the semiconductor device according to the prior art will be described as follows.
먼저, 반도체기판상에 소정의 하부 구조, 예를 들어 소자분리를 위한 소자분리 산화막과 게이트전극 및 소오스/드레인전극을 구비하는 모스 전계효과 트랜지스터와 비트선 및 캐패시터등이 순차적으로 형성되어있고, 상기 구조의 전표면에 제1층간 절연막이 형성되어 있다.First, a MOS field effect transistor having a predetermined substructure, for example, a device isolation oxide film for device isolation, a gate electrode, and a source / drain electrode, a bit line, a capacitor, and the like are sequentially formed on a semiconductor substrate. The first interlayer insulating film is formed on the entire surface of the structure.
또한 상기 제 1층간 절연막상에는 상기 제 1 층간 절연막상에는 A1패턴으로된 제1금속배선이 형성되어있으며, 상기 구조의 전표면에 평탄화막이 오존-TEOS나 에스.오.지(Spin On Glass; 이하 SOG라 칭함)등과 같은 산화막 재질로 형성되어 있고, 상기 평탄화막상에 제2금속배선이 형성되어 있다.In addition, a first metal wiring having an A1 pattern is formed on the first interlayer insulating film, and a planarization film is formed on the entire surface of the structure by using ozone-TEOS or spin on glass (SOG). And the like, and a second metal wiring is formed on the planarization film.
상기와 같은 종래 기술에 따른 반도체소자의 금속배선간 절연막 제조방법은 제1금속배선인 A1 패턴상에 평탄화막을 형성하여 절연 및 평탄화하는 방법으로서 자체 평타노하 특성이 우수한 오존-TEOS 산화막을 10000Å 이상으로 두껍게 전면 식각을 하거나, 오존-TEOS 산화막을 6000Å 정도 증착 후 부족한 평탄도를 보완하기 위하여 오존-TEOS 산화막상에 에,오,지(spin on glass ; 이하 SOG라 칭함)등과 같이 평탄화가 우수하고 단차피복성이 우수한 재료를 도포하고, 전면 식각을 실시하여 금속배선간 콘택 부분에는 SOG가 노출되지 않게 하며 평탄화하고 있다.The method of manufacturing an insulating film between metal wirings of a semiconductor device according to the prior art as described above is a method of forming and insulating and planarizing a planarization film on the A1 pattern, which is the first metal wiring. In order to compensate for the lack of flatness after the entire surface is etched or the ozone-TEOS oxide film is deposited by 6000Å, the flatness is excellent and the level difference such as spin on glass (hereinafter referred to as SOG) on the ozone-TEOS oxide film. A material having excellent coating properties is applied, and the entire surface is etched to prevent SOG from being exposed to the contact portions between the metal wirings and to be flattened.
그러나 상기와 같은 반도체소자의 평탄화 방법은 공정이 복잡하여 제조단가가 상승하고, 공정중에 층간 절연막이 균열되어 도전배선간에 단락등이 발생되거나, 평탄도가 떨어져 후속 금속배선 공정이 어려우 공정수율 및 소자 동작의 신뢰성이 떨어지는 문제점이 있다.However, in the planarization method of the semiconductor device as described above, the manufacturing cost is increased due to the complicated process, the interlayer insulating film is cracked during the process, short circuit occurs between the conductive wirings, or the subsequent flatness is difficult due to poor flatness. There is a problem that the operation reliability is low.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서 본 발명의 목적은 제1금속배선을 증착하기에 앞서 제1금속배선 밑의 층간절연막에서 A1 배선이 올라갈 부분에 오목한 홈을 형성하여 금속배선의 일부가층간절연막 사이에 심어지는 형태로 형성하여 평탄화막의 형성 공정이 용이하고, 평탄도가 향상되어 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법을 제공함에 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to form a concave groove in a portion where an A1 wiring is to be raised in an interlayer insulating film under the first metal wiring before depositing the first metal wiring, thereby forming a part of the metal wiring. The present invention provides a method of manufacturing a semiconductor device, which is formed in a form interposed between the interlayer insulating films to facilitate the process of forming the planarization film, and the flatness is improved to improve the process yield and the reliability of device operation.
상기와 같은 목적을 달성하기 위한 본발명에 따른 반도체소자의 제조방법의 특징은 소정의 하부구조물들이 형성되어있는 반도체기판상에 층간절연막을 형성하는 공정과, 상기 층간절연막에서 금속배선이 올라갈 부분 상측에 일정 깊이의홈을 형성하는 공정과, 상기 홈에 일정 부분이 묻혀있는 제1금속배선을 형성하는 공정과, 상기 구조의 전표면에 평탄화막을 형성하는 공정과, 상기 평탄화막상에 제2금속배선을 형성하는 공정을 구비함에 있다.In order to achieve the above object, there is provided a method of manufacturing a semiconductor device according to the present invention, which includes forming an interlayer insulating film on a semiconductor substrate on which predetermined lower structures are formed, and an upper portion of the interlayer insulating film on which a metal wiring is to be raised. Forming a groove having a predetermined depth in the groove, forming a first metal wiring having a predetermined portion buried in the groove, forming a flattening film on the entire surface of the structure, and forming a second metal wiring on the flattening film. It has in the process of forming a.
본발명에 따른 반도체소자의 제종방법의 다른 특징은, 소정 구조의 반도체기판상에 제1금속배선을 형성하고, 상기 구조의 전표면에 층간절연막을 형성하는 공정과, 상기 층간절연막에서 제2금속배선이 올라가기로예정된 부분상에 소정 깊이의 홈을 형성하는 공정과, 상기 제1금속배선에서 비하 콘택으로 예정되있는 부분상측의 층간절연막을 제거하여 비아 콘택홀을 형성하는 공정과, 상기 홈을 메우고 비아콘택홀을 통하여 제1금속배선과 연결되는 제2금속배선을 형성하는 공정과 ,상기 구조의 전표면에 보호막을 형성하는 공정을 구비함에 있다.Another characteristic of the method for fabricating a semiconductor device according to the present invention is the step of forming a first metal wiring on a semiconductor substrate having a predetermined structure, forming an interlayer insulating film on the entire surface of the structure, and a second metal in the interlayer insulating film. Forming a groove having a predetermined depth on a portion where the wiring is supposed to go up; forming a via contact hole by removing an interlayer insulating film on an upper portion of the first metal wiring, which is supposed to be a non-contact contact; Forming a second metal wiring connected to the first metal wiring through the via contact hole and forming a protective film on the entire surface of the structure.
이하, 본발명에 따른 반도체소자의 제조방법에 관하여 첨부도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
제 1a도 내지 제 1e도는 본발명에 따른 반도체소자의 제조공정도로서, 제1금속배선이 하부의 다결정실리콘층 패턴과 연결되어 있는 부분을 도시한 예이다.1A to 1E are diagrams illustrating a manufacturing process of a semiconductor device according to the present invention, and show an example in which a first metal wiring is connected to a lower polysilicon layer pattern.
먼저, 소정의 하부 구조, 예를들어 소자분리를 위한 소자분리 산화막과 게이트전극 및 엘.디.디(lightly doped drain; 이하 LDD라 칭함) 구조의 소오스/드레인전극을 구비하는 모스 전계효과 트랜지스터와 비트선 및 캐패시터등이 순차적으로 형성되어있는 분도체기판상에의 전표면에 제1층간 절연막(1)을 산화막 재질, 예를들어 비.피.에스.지(Boro Phospho Silicate Glass; 이하 BPSG라 칭함), 테오스(Tetra etchyl orthor silicate; 이하 TEOS라 칭함),피,에스.지(Phospho Silicate Glass; 이하 PSG라 칭함)등과 같이 단차피복성이 우수한 재질로 형성하고, 사이 제1 층간절연막(1)상에 플레이트 전극이 되는 다결정실리콘층(2) 패턴을 형성한다. (제 1a도 참조).First, a MOS field effect transistor having a predetermined substructure, for example, a device isolation oxide layer and a gate electrode for device isolation, and a source / drain electrode having a lightly doped drain (LDD) structure; The first interlayer insulating film 1 is formed on an entire surface of a semiconductor substrate on which bit lines and capacitors are sequentially formed. ), Teos (tetra etchyl orthor silicate) (hereinafter referred to as TEOS), P, S. (Phospho Silicate Glass (hereinafter referred to as PSG)) and the like formed of a material having excellent step coverage, the first interlayer insulating film (1 The polysilicon layer 2 pattern which becomes a plate electrode is formed on (). (See also Figure 1a).
그다음 상기 구조의 전표면에 제2층간절연막(3)을 형성하고, 상기 제2층간절연막(3)상에 감광막패턴(4)을 형성하되, 상기 감광막패턴(4)에 의해 노출되는 부분이 제1금속배선으로 에정되어있는 부분이 되도록 한다. 이때 상기 다결정실리콘층(2) 패턴과 제1금속배선 사이의 제2층간절연막(3)을 현재의 두께보다 1000~2000Å 정도 두꺼운 4500~5000Å 정도 두껍게 증착하여 평탄도를 더욱 향상시킬 수도 있다.Next, a second interlayer insulating film 3 is formed on the entire surface of the structure, and a photosensitive film pattern 4 is formed on the second interlayer insulating film 3, and the portion exposed by the photosensitive film pattern 4 is formed. 1 Make the part defined by metal wiring. In this case, the second interlayer insulating film 3 between the polysilicon layer 2 pattern and the first metal interconnection may be deposited to a thickness of about 4500 to 5000 m thick, which is 1000 to 2000 m thick thicker than the current thickness, to further improve flatness.
또한 상기 감광막패턴(4) 형성시에는 금속배선 패턴닝시의 노광마스크를 사용하되, 감광막의 반대의 것을 사용할 수도 있다. 즉 제1금속배선 패턴닝시의 감광막을 포지티브 형을 사용하면, 상기의 감광막패턴(4)은 네가티브를 사용한다. (제 1b도 참조).When the photoresist pattern 4 is formed, an exposure mask during metallization patterning may be used, but the opposite of the photoresist may be used. That is, when the photosensitive film at the time of patterning the first metal wiring uses a positive type, the photosensitive film pattern 4 uses negative. (See also Figure 1b).
그후, 상기 감광막패턴(4)에 의해 노출되어있는 제2층간절연막(3)을 소정 깊이로 습식식각하여 홈(5)을 형성하고, 상기 감광막패턴(4)을 제거한다. 이때 상기 홈(5)의 깊이는 형성하고자하는 제 1 금속배선 두깨의 일부 두께, 예를 들어 금속배선 두께의 1/3 정도인 1000~4000Å 정도가되도록 하고, 식각 공정은 습식식각방법을 사용한다. (제 1c도 참조).Thereafter, the second interlayer insulating film 3 exposed by the photosensitive film pattern 4 is wet-etched to a predetermined depth to form a groove 5, and the photosensitive film pattern 4 is removed. In this case, the depth of the groove 5 is about 1000 to 4000 mm, which is about 1/3 of the thickness of the first metal wire to be formed, for example, about 1/3 of the metal wire thickness, and the etching process uses a wet etching method. . (See also Figure 1c).
그다음 상기 다결정실리콘층(2)에서 금속배선 콘택으로 에정되어있는 부분상측의 제 2 층간절연막(3)을 건식식각방법으로 제거하여 콘택홀(6)을 형성한다. (제 1d도 참조).Then, the second interlayer insulating film 3 overlying the portion of the polysilicon layer 2 etched as the metal wiring contact is removed by dry etching to form the contact hole 6. (See also Figure 1d).
그후, 상기 홈(5)을 메우고 콘택홀(6)을 통하여 상기 다결정실리콘층(2) 패턴과 연결되는 제1금속배선이 되는 제1금속막(7)을 6000~8000Å 정도 두께로 Al 합금계열, W 등의 금속으로 형성한다. 이때 상기 제 1 금속막(7)은 1000~4000Å 정도는 상기 홈(5)에 묻혀 있으며, 2000~7000Å 정도는 제2층간절연막(3) 위에 위치하게 된다. (제 1e도 참조).Subsequently, an Al alloy series having a thickness of about 6000 to 8000 Å is formed on the first metal film 7 which fills the groove 5 and becomes the first metal wiring connected to the polysilicon layer 2 pattern through the contact hole 6. And metal such as W. At this time, the first metal film 7 is buried in the groove 5 at about 1000 to 4000 kPa, and is positioned on the second interlayer insulating film 3 at about 2000 to 7000 kPa. (See also section 1e).
그후, 상기 제 1 금속막(7)을 패턴닝하여 제1금속막(7) 패턴으로된 제1 금속배선을 형성하고, (제 1f도 참조), 상기 구조의 전표면에 제3층간절연막(8)을 형성하되, 상기 제 3 층간절연막(8)은 제1금속막(7) 패턴의 산화나 수분 침투 등을 방지하기위하여 500~15000Å 정도 두께로 굴절율이 1.48 이상인 Si 리치(rich) 산화막이나 SiH4-N2O 계 플라즈마를 이용하여 형성되는 굴절율 1.64의 실리콘 산화질화막으로된 장벽절연막(8A)과 그상측에 평탄성이 우수한 산화막 재질, 예를 들어 오존 -TEOS 산화막이나 BPSG, PSG등으로된 6000-10000Å 정도 두께의 평탄화막(8B)을 순차적으로 증착하여 제1금속배선과 제2금속배선 사이를 절연 및 평탄화 시킨다. 여기서 상기 평탄화막(8B)이 오전-TEOS 산화막인 경우 오존-TEOS 산화막의 형성조건은 오존/TEOS 몰(mole) 비를 10 이상이 되도록하고, 증착온도는 300~500, 증착율은 400~600Å/min. 정도의 조건으로 증착한다. (제 1f도 참조).Thereafter, the first metal film 7 is patterned to form a first metal wiring having a pattern of the first metal film 7 (see also FIG. 1F), and a third interlayer insulating film is formed on all surfaces of the structure. 8) wherein the third interlayer insulating film 8 is formed of a Si rich oxide film having a refractive index of 1.48 or more and having a thickness of about 500 to 15000 위 to prevent oxidation or moisture penetration of the first metal film 7 pattern. A barrier insulating film 8A made of a silicon oxynitride film having a refractive index of 1.64 formed using a SiH 4 -N 2 O-based plasma and an oxide film material having excellent flatness on the upper side thereof, for example, an ozone-TEOS oxide film, BPSG, PSG, or the like. The planarization film 8B having a thickness of about 6000-10000 kV is sequentially deposited to insulate and planarize between the first metal wiring and the second metal wiring. Where the planarization film 8B is an AM-TEOS oxide film, the ozone-TEOS oxide film is formed under an ozone / TEOS mole ratio of 10 or more, the deposition temperature is 300 to 500, and the deposition rate is 400 to 600 mW /. min. Deposition under conditions of degree. (See also 1f).
그다음 후속 금속배선간 콘택 식각을 진행한 후에 상기 제3층간절연막(8) 상에 제2금속막(9) 패턴으로된 제2금속배선을 형성한다. 이때 상기 제2금속배선은 30℃ 고온 스퍼터링(sputtering)을 통하여 증착하므로 전체 단차피복성을 향상시켜 제2금속배선(9) 패턴닝시 패턴이 단락되는 브릿지 발생을 방지할 수 있다. (제 1g도 참조).Subsequently, after the subsequent contact etching between the metal lines is performed, a second metal wire having a second metal film 9 pattern is formed on the third interlayer insulating film 8. In this case, since the second metal wiring is deposited through high-temperature sputtering at 30 ° C., the overall step coverage can be improved to prevent the occurrence of a short-circuit bridge when patterning the second metal wiring 9. (See also 1g).
본발명의 다른 실시예로서, 제2 금속배선 형성 전에 상기 제1금속배선의 상측을 덮는 층간절연막 상부에서 제2금속배선으로 에정되어있는 부분에 홈을 형성하여 제2금속배선의 일부 두께가 홈 내부에 묻히도록 형성하면, 후속 보호막(passivation) 형성 공정시 보호막내의 보이드 생성이 방지되고 평탄도가 향상되어 패키지(package) 공정시 보호막의 균열이 방지된다.According to another embodiment of the present invention, before forming the second metal wiring, a groove is formed in a portion defined by the second metal wiring on the upper part of the interlayer insulating film covering the upper side of the first metal wiring, so that a part of the thickness of the second metal wiring is grooved. When formed to be buried therein, void formation in the protective film is prevented during the subsequent passivation forming process and flatness is improved to prevent cracking of the protective film during the package process.
이상에서 설명한 바와 같이, 본발명에 따른 반도체소자의 제조방법은 금속배선의 일부 두께를 그 하부의 층간절연막에 묻히도록하여 상기 층간절연막의 평면위로 돌출된 제1금속배선의 높이를 감소시켰으므로, 금속배선에 의한 단차가 감소되므로 평탄도가 향상되어 후속 포토 리소그래피 공정시 단차에 의한 나칭 발생이 감소되고, 제1금속 배선과 제2금속 배선 사이의 단락이 방지되고, 배선의 단선도 방지되며, 상기의 방법을 제2금속배선 증착과 보호막 공정에도 적용하여 보호막의 보이드 발생을 억제하고 평탄화를 향상시켜 패키지 공정진행시 보호막의 균열 발생을 억제할 수 있어 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, the thickness of the first metal wiring protruding onto the plane of the interlayer insulating film is reduced by embedding a part of the thickness of the metal wiring in the interlayer insulating film below. Flatness is improved because the level difference due to the metal wiring is reduced, thus reducing the occurrence of naching due to the level difference in the subsequent photolithography process, preventing short circuit between the first metal wiring and the second metal wiring, and preventing disconnection of the wiring. By applying the above method to the second metal wiring deposition and the protective film process, it is possible to suppress the void generation of the protective film and to improve the planarization to suppress the cracking of the protective film during the package process, thereby improving the process yield and the reliability of device operation. There is an advantage to that.
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