KR100200747B1 - Device isolation method in silicon processing - Google Patents

Abstract

(LOCOS) by a selective oxidation method and a device isolation method using a shallow trench are disclosed. For this purpose, the present invention provides a method of manufacturing a semiconductor device, comprising: a first step of forming a field oxide film on a semiconductor substrate by a device isolation method using selective oxidation (LOCOS); a step of forming a gate oxide film on the resultant product and depositing a gate polysilicon film A third step of forming first and second insulating films on the polysilicon film for gate, a third step of etching the gate polysilicon film and the first and second insulating films to form a gate electrode, A fourth step of forming gate spacers on both side walls, a fifth step of depositing a conductive layer for forming a contact on the entire surface of the resultant, a sixth step of forming a third insulating film on the conductive layer, A step of patterning a landing pad by conducting a photolithography / etching process on the conductive layer and the third insulating layer; etching the silicon of the field oxide layer and the substrate using the landing pad as a mask; And a tenth step of forming a trench, and a ninth step of depositing an interlayer insulating film on the entire surface of the resultant to fill the trench, thereby completing a device isolation process. . Therefore, it is possible to realize a device isolation method of a semiconductor device which can solve the problems in the device isolation method using a conventional trench.

Description

Device isolation method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device, and more particularly, to a device isolation method of a semiconductor device combining a device isolation method (LOCOS) by selective oxidation and a device isolation method using a trench.

BACKGROUND ART [0002] LOCal Oxidation of Silicon (LOCOS) method widely used as a device isolation method in the manufacture of semiconductor devices has been widely used for a variety of applications such as a Bird's beak phenomenon caused by lateral oxidation, There is a problem in improving the electrical characteristics of the semiconductor device due to problems such as crystal defects in the silicon substrate and redistribution of impurities implanted for channel blocking. In addition, in the highly integrated device, since the width of element isolation is reduced, the conventional LOCOS method has reached its limit due to punch-through due to Bird's beak and reduction in thickness of the element isolation film.

Trench isolation has been proposed as one of the methods for solving the problems of the LOCOS method. In this trench isolation method, a semiconductor substrate is etched to form a trench, an insulating material is buried in the trench, and then a chemical-mechanical polishing (CMP) is performed to form a device isolation film. Since this trench isolation method is not dependent on the thermal oxidation process as in the LOCOS method in the formation of the device isolation film, the disadvantages of the LOCOS process caused by the thermal oxidation process can be reduced to some extent and the device isolation film suitable for high integration can be formed .

Here, a method of isolating a semiconductor device using a conventional trench and its problems will be described in detail.

1 to 6 are cross-sectional views for explaining a device isolation method of a conventional semiconductor device using a transistor.

Referring to FIG. 1, a pad oxide film 3 and a nitride film 5 are formed on a semiconductor substrate 1, followed by patterning by a general photo / etching method. The silicon of the semiconductor substrate 1 is etched by a predetermined amount using the pattern as a mask to form a trench 7.

2, a thermal oxide film 9 is grown on the side surface of the trench 7, and boron ions are implanted into the thermal oxide film 9 for channel stop purposes.

Referring to FIG. 3, an oxide film 11 is deposited on the entire surface of the resultant by a chemical vapor deposition (CVD) method. In general, the oxide film formed by the CVD method is wet-etched faster than the thermal oxide film. Therefore, the oxide film 11 produced by the CVD method is subjected to a high-temperature heat treatment. Subsequently, the nitride film (5) is used as a polishing stopper layer, and CMP is performed to achieve overall planarization.

Referring to FIG. 4, a spacer 13 (spacer) made of an oxide film is formed to remove the nitride film 5 on the substrate and to smooth the step formed on the interface between the active region and the inactive region.

Referring to FIG. 5, the pad oxide film 3 on the top of the substrate is removed.

Referring to FIG. 6, a gate oxide film 15 is grown on a front surface of a substrate, and a gate polysilicon film 17 doped with impurities is deposited on the gate oxide film 15 to complete the process.

However, the above-described conventional device isolation method using a trench has the following problems.

First, the high temperature heat treatment process performed to improve the characteristics of the oxide film 11 generated by the CVD method filling the trenches 7 so that the wet etching progresses too quickly causes heat stress to the inside of the device, .

Second, there is a problem that a void is generated in the process of filling the trench 7 with the oxide film 11 formed by the CVD method, thereby causing a bridge in the gate polysilicon film.

Thirdly, in the CMP process for planarization, when the photo / etching process is added to prevent the dishing (dipping (surface of the layer to be polished in the CMP process) There is a problem that it becomes long and complicated.

Fourth, it is difficult to stop the etching in the pad oxide film 3 when forming the spacers 13 to alleviate the level difference between the active region and the inactive region. When the etching proceeds to the substrate 1, the characteristics of the gate oxide film 15 There is a problem of deterioration.

Fifth, in the case where a spacer is not formed in order to prevent the gate oxide film 15 from deteriorating, an electric field is concentrated in a region where a step is formed due to a step difference between the active region and the inactive region, ) And the inverse narrow width effect in which the gate width is reduced is intensified, resulting in serious consequences.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a device isolation method for a semiconductor device capable of solving the problems in a device isolation method using a conventional trench.

1 to 6 are cross-sectional views for explaining a device isolation method of a conventional semiconductor device using a transistor.

7 to 16 are views for explaining a device isolation method of a semiconductor device according to the first embodiment of the present invention.

17 is a cross-sectional view for explaining a device isolation method of a semiconductor device according to a second embodiment of the present invention.

DESCRIPTION OF THE RELATED ART [0002]

100: semiconductor substrate, 106: field oxide film,

108: conductive layer, 110: third insulating film,

112: fourth insulating film, 114: landing pad,

116: trench, 118: interlayer insulating film,

120: gate oxide film, 122: polysilicon film for gates electrode,

124: first insulating film, 126: second insulating film,

128: gate spacer.

According to an aspect of the present invention, there is provided a method of isolating elements in a semiconductor device, comprising: a first step of forming a field oxide film on a semiconductor substrate by a device isolation method using selective oxidation (LOCOS) A second step of forming a gate oxide film on the gate polysilicon film and laminating a polysilicon film for gate, a third step of forming a first insulator film on the gate polysilicon film, A fourth step of forming a gate electrode by etching to form gate spacers on both side walls of the gate electrode, a fifth step of depositing a conductive layer for forming a contact on the entire surface of the resultant, A sixth step of forming an insulating film, a seventh step of patterning a landing pad by conducting a photo / etching process on the conductive layer and the third insulating film, Forming a trench by etching the field oxide film and the silicon on the substrate using the trench landing pad as a mask and depositing an interlayer insulating film on the entire surface of the resultant to fill the trench to complete the device isolation process The device isolation method of the semiconductor device.

After the sixth step of forming the third insulating film, a step of forming a fourth insulating film on the third insulating film may also be performed to realize the device separating method according to the present invention.

After the third step of forming the first insulating film, a step of forming a second insulating film on the first insulating film may be added to realize the device separating method according to the present invention.

The seventh step of patterning the landing pad by conducting a photolithography / etching process on the conductive layer and the third insulating layer may include patterning the third insulating layer and the conductive layer using the fourth insulating layer, Is preferably etched.

According to a preferred embodiment of the present invention, it is preferable to use any one material selected from the group consisting of a nitride film (SiN), aluminum oxide (AL ₂ O ₃ ), and polysilicon.

It is preferable that the fourth insulating film is formed with a different thickness of the fourth insulating film according to the etch selectivity of the material to be used and the material to be etched.

According to a preferred embodiment of the present invention, it is preferable that the first insulating film and the gate spacer use one of an oxide film or a nitride film (SiN) formed by a chemical vapor deposition method.

In accordance with a preferred embodiment of the invention, the second insulating film, a nitride film can be prevented from etching the first insulating film at the time of etching of the field oxide film and the substrate for the trench formation (SiN) or aluminum oxide (AL ₂ O ₃₎ It is appropriate to use one of them.

The third insulating film is preferably thicker than the field oxide film.

The interlayer insulating film for embedding the trench in the ninth step is preferably an oxide film formed by a chemical vapor deposition method.

The conductive layer is preferably polysilicon doped with phosphorus (P).

It is preferable that the trench of the eighth step is located in the field oxide region generated by the element isolation method using selective oxidation (LOCOS).

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First Embodiment

FIGS. 7 to 16 are diagrams for explaining the manufacturing method, which is one embodiment of the present invention applied to a device isolation process of a semiconductor device. FIG.

FIG. 7 is a plan view of a semiconductor device in which a field oxide film according to the present invention is formed, and FIGS. 8 to 12 are cross-sectional views taken along the line X - X - X ' And FIGS. 13 to 15 show cross-sectional views when the process is performed in a state where FIG. 7 is cross-sectioned in Y (Y-Y 'direction) axis. 16 is a cross-sectional view illustrating a mechanism for embedding a trench according to the present invention.

Referring to FIG. 7, an active region 102, which is an area where an element is formed on a semiconductor substrate 100 (not shown), and an inactive region 104, which is an area isolating elements from each other, are formed.

FIG. 8 is a cross-sectional view taken along the X-axis direction of FIG. 7. FIG. First, a field oxide film 106 is formed on a semiconductor substrate 100 using a general isolation oxidation (LOCOS) method to complete device isolation in an initial stage (first stage). The LOCOS device isolation method can be any conventional LOCOS device isolation technology. The sequential steps to the above process are the steps of forming gate electrodes and gate spacers for the transistor formation (second to fourth steps), but this is not shown in the sectional view for the sake of easy explanation. The above-described second to fourth steps will be described in detail by cross-sectional views illustrating the Y-axis, which will be described later.

Referring to FIG. 9, a conductive layer 108, for example, polysilicon doped with phosphorus is deposited on the entire surface of the result of the above-mentioned step 5 by CVD (fifth step). The conductive layer 108 may be a buried contact (BC) and a direct contact (DC) after the gate formation, i.e., a capacitor and a bit line, and a landing pad for BC and DC contact of the memory cell. . Next, the third insulating film 110 and the fourth insulating film 112 are deposited on the conductive layer 108 (step 6). The third and fourth insulating films 110 and 112 may be formed of one layer, that is, a third insulating film, to realize the device isolation method of the present invention, which will be described in detail in a second embodiment to be described later. When the trench is formed by etching the field oxide film 106 and the substrate 100 in a subsequent process, the third insulating film 112 and the landing pad including the third insulating film 110 and the conductive layer 108 are etched, (SiN), aluminum oxide (AL ₂ O ₃ ) _, polysilicon, or an oxide film formed by the CVD method, which are different from each other in the etching selectivity of the substrate 100 _, ≪ / RTI > The thickness of the fourth insulating film 112 should be different depending on the etch selectivity of the material used.

10, a photo / etching process is performed on the third and fourth insulating layers 110 and 112 and the conductive layer 108 using a fourth insulating layer 112 as an etching mask to complete a pattern of a landing pad exposing the field oxide layer (Step 7). Here, the landing pad 114 always self-aligns over the field oxide film 106, so that the field oxide film 106 serves as an etch stop layer when the landing pad 114 is etched.

11, a trench 116 is formed by etching the lower field oxide 106 and the silicon of the substrate 100 using the third and fourth insulating films 110 and 112 as a mask (Step 8) do. Since the landing pad 114 is used as a mask when the trench 116 is formed by etching the lower field oxide film 106 and the silicon of the substrate 100, the trench 116 is always subjected to selective oxidation (LOCOS) And is formed only in the region of the field oxide film 106 generated by the field oxide film 106. That is, the structure in which the trench is always formed in the field oxide film has a problem that the hump, the inverse narrow width effect and the gate oxide film of the transistor, which conventionally cause the edge of the trench to meet with the active region, Thereby forming one of the key ideas of the present invention which can improve the problem.

Referring to FIG. 12, an interlayer insulating layer 118 is deposited on the entire surface of the resultant structure to fill the trench 116 formed in the eighth step, thereby achieving overall planarization. In the present invention, the entire planarization can be achieved by using the interlayer insulating film 118 without achieving the entire planarization by CMP. Therefore, in order to prevent dishing and dishing caused in the planarization process using CMP in the prior art The problem of lengthening the process due to the addition of the photo / etching process can be solved. Also, since the heat treatment process involved in the photo / etching process for preventing the dishing is eliminated, it is possible to prevent defects caused by the stress occurring at this time.

FIG. 13 is a cross-sectional view taken along the Y-axis in the plan view of FIG. 2. FIG. In detail, a gate oxide film 120 is grown and formed on a substrate 100 having a structure of a lower transistor, and a polysilicon film 122 for a gate electrode is stacked on the gate oxide film 120 (second step). The first insulating film 124 and the second insulating film 126 are deposited on the polysilicon film 122 for the gate electrode 122 in the third step and the photolithography process is performed to form the lower second insulating film 126, The first insulating film 124 and the gate electrode polysilicon 122 are etched to form gate electrodes and gate spacers 128 are formed on both sidewalls thereof (fourth step). The gate spacer 128 is a material that can prevent the bottom portion of the polysilicon for the gate electrode from being etched in the etching process for forming the trench, and it is possible to use one of the oxide film or the nitride film (SiN) . The first insulating layer 124 formed on the gate electrode polysilicon layer 122 prevents the first insulating layer from being etched when the landing pad 114, the field oxide layer 106, and the trench 116 are etched. It is preferable to use one of an oxide film or a nitride film (SiN) produced by the CVD method. The second insulating layer 126 is formed by using one of a nitride layer (SiN) and aluminum oxide (AL ₂ O ₃ ) as a material for preventing the underlying first insulating layer 124 from being etched in an etching process for forming a trench. do. At this time, the first and second insulating films may be formed of one layer, that is, a first insulating film, to achieve the object of the present invention. Next, a polysilicon doped with a conductive layer 108, for example, phosphorus is deposited on the entire surface of the resultant structure by a CVD method (fifth step) as described in the sectional view along the X-axis, 3, and 4 insulating films (sixth step) are formed.

Referring to FIG. 14, a landing pad 114 is formed by performing a photolithography / etching process. Then, the landing pad and the gate electrode on the field oxide film 106 and the gate spacer 128 are used as an etching mask, ) Of silicon is etched to complete the trench 116. At this time, the landing pad 114 is self-aligned and positioned between adjacent gate electrodes.

Referring to FIG. 15, an interlayer insulating layer 118 is deposited on the entire surface of the resultant structure as an oxide layer formed by CVD, which is a material having a function of buffer layer for relieving stress caused by heat during a subsequent process. At this time, even if a seam or void occurs due to poor step coverage characteristics, the interlayer insulating film 118 is filled with the filling material at the top of the interlayer insulating film, so that the characteristics of the device are not affected in the subsequent process.

Referring to FIG. 16, in the process of depositing the interlayer insulating film 118 described in FIG. 15, the oxide film generated by the CVD method is shimmed in a certain region 134 of the trench during the process of filling the lower trench 116 Seam) and voids. Reference numeral 132 denotes an area where an element pattern including the landing pad of FIG. 15 is formed, though it is not shown in detail in order to facilitate explanation.

Second Embodiment

FIG. 17 is a cross-sectional view illustrating the second embodiment of the present invention, which is different from FIG. 9 as described above. The third embodiment differs from the first embodiment in that the third and fourth insulating films are formed on the conductive layer in the sixth step of the first embodiment. In this embodiment, one insulating film, for example, Only the third insulating film 136 is used.

7, a field oxide film 106 is formed on a semiconductor substrate 100 by a device isolation method using a general selective oxidation (LOCOS) process (first step After the device structure including the gate electrode is completed (steps 2, 3 and 4, not shown in the figure), a conductive layer 108 for a contact is stacked on the entire surface of the resultant (step 5) A third insulating film 136 is formed only on the conductive layer in consideration of the etching selectivity of the two insulating films instead of the third and fourth insulating films. When the oxide film formed by the CVD method is used, the third insulating film 136 is also etched together with the field oxide film 106 in the photo / etching process for forming the trench 114 The thickness of the layer must be thick and remain at the time of etching the silicon of the lower substrate 100. According to an embodiment of the present invention, when the thickness of the field oxide layer 106 is 2000 angstroms, the thickness of the third insulating layer 136 is preferably 3000 to 5000 angstroms.

It will be apparent to those skilled in the art that the present invention is not limited to the above-described embodiment, and many modifications may be made by those skilled in the art without departing from the spirit and scope of the present invention.

Therefore, according to the present invention described above, it is possible to provide a method of manufacturing a semiconductor device, which has a problem in a conventional device isolation process using a shallow transistor, that is, a defect caused by a stress generated in a heat treatment process, a dishing in a planarization process, It is possible to realize a device isolation method of a semiconductor device in which a hump phenomenon of a transistor is improved.

Claims (12)

A first step of forming a field oxide film on a semiconductor substrate by a device isolation method (LOCOS) using selective oxidation; A second step of forming a gate oxide film on the resultant product and laminating a gate polysilicon film; A third step of forming a first insulating film on the gate polysilicon film; A fourth step of forming a gate electrode by etching the gate polysilicon film and the first insulating film and forming gate spacers on both side walls of the gate electrode; A fifth step of depositing a conductive layer on the entire surface of the resultant to form a contact; A sixth step of forming a third insulating film on the conductive layer; A seventh step of patterning a landing pad by conducting a photo / etching process on the conductive layer and the third insulating layer; An eighth step of forming a trench by etching the field oxide film and the silicon of the substrate using the landing pad as a mask; And And a ninth step of depositing an interlayer insulating film on the entire surface of the resultant to fill the trench portion to complete a device isolation process. The method according to claim 1, wherein the sixth step includes the step of forming a fourth insulating film on the third insulating film. The method according to claim 1, wherein the third step further comprises forming a second insulating film on the first insulating film. 3. The method according to claim 2, wherein the seventh step uses the fourth insulating film as an etching mask to etch the underlying third insulating film and the conductive layer. The method according to claim 2, wherein the fourth insulating film is formed of any one selected from a nitride film (SiN), aluminum oxide (AL ₂ O ₃ ), and polysilicon. The device isolation method according to claim 1 or 2, wherein the first insulating film uses one of an oxide film or a nitride film (SiN) formed by chemical vapor deposition. The device isolation method of claim 1 or 2, wherein the gate spacer uses one of an oxide film or a nitride film (SiN) formed by chemical vapor deposition. The method according to claim 1 or 3, wherein the second insulating film is formed of a nitride film (SiN) or aluminum oxide (AL ₂ O ₃ ) that can prevent the first insulating film from being etched when etching the field oxide film and the substrate, Is used as the element isolation method. The device isolation method according to claim 1 or 2, wherein the thickness of the third insulating film is thicker than that of the field oxide film. 3. The semiconductor device according to claim 1 or 2, wherein the interlayer insulating film for embedding the trench in the ninth step uses an oxide film produced by chemical vapor deposition, which is a material having a poor step coverage characteristic. Way. The device isolation method of claim 1 or 2, wherein the conductive layer in the fifth step is polysilicon doped with phosphorus (P). The method of claim 1 or 2, wherein the trench of the eighth step is located in a field oxide film.