KR20030050668A - Method for forming isolation layer - Google Patents
Method for forming isolation layer Download PDFInfo
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- KR20030050668A KR20030050668A KR1020010081171A KR20010081171A KR20030050668A KR 20030050668 A KR20030050668 A KR 20030050668A KR 1020010081171 A KR1020010081171 A KR 1020010081171A KR 20010081171 A KR20010081171 A KR 20010081171A KR 20030050668 A KR20030050668 A KR 20030050668A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 소자분리막의 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a device isolation film.
일반적으로 반도체 장치의 소자분리(Isolation; ISO)는 LOCOS(Local Oxidation of Silicon) 또는 PGI(Profiled Grove Isolation) 등과 같은 통상적인 소자 분리 방법을 이용하여 반도체기판의 소정 부분에 필드절연막을 형성하여 활성영역을 한정하는 필드영역을 형성한다.In general, device isolation (ISO) of a semiconductor device is an active region by forming a field insulating film on a predetermined portion of a semiconductor substrate by using a conventional device isolation method such as LOCOS (Local Oxidation of Silicon) or PGI (Profiled Grove Isolation). A field area defining the area is formed.
소자 분리 방법 중에서 LOCOS 방법은 활성영역을 한정하는 산화 마스크인 질화막(Nitride)을 반도체기판상에 형성하고, 포토리소그래피(Photolithograpy) 방법으로 패터닝하여 반도체기판의 소정 부분을 노출시킨 후, 노출된 반도체기판을 산화시켜 소자 분리 영역으로 이용되는 필드산화막(Field Oxide)을 형성한다.Among the device isolation methods, the LOCOS method forms a nitride film, which is an oxidation mask defining an active region, on a semiconductor substrate, is patterned by a photolithography method to expose a predetermined portion of the semiconductor substrate, and then the exposed semiconductor substrate. Is oxidized to form a field oxide film used as an isolation region.
LOCOS 방법은 공정이 단순하고, 넓은 부위와 좁은 부위를 동시에 분리할 수 있다는 장점을 갖고 있지만, 측면산화에 의한 새부리(Bird's beak)가 형성되어 소자 분리 영역의 폭이 넓어져서 소오스/드레인 영역의 유효 면적을 감소시킨다. 또한, 필드산화막 형성시 산화막의 가장자리에 열 팽창계수의 차이에 따른 응력이 집중됨으로써, 실리콘 기판에 결정 결함이 발생하여 누설전류가 많은 단점이 있다.The LOCOS method has the advantage of simple process and the separation of wide and narrow areas at the same time. However, Bird's beak is formed by lateral oxidation, so the width of device isolation area is widened, so that the effective source / drain area is effective. Reduce the area. In addition, when the field oxide film is formed, stress is concentrated on the edges of the oxide film due to the difference in thermal expansion coefficient, so that a crystal defect occurs in the silicon substrate and thus a leakage current is increased.
최근에 반도체소자의 집적도가 증가함에 따라 디자인 룰이 감소하고, 따라서 반도체소자와 반도체소자를 분리하는 소자분리막의 크기도 같은 스케일(scale)만큼 축소되어 통상의 LOCOS, PBL 등과 같은 소자 분리 방법은 그 적용이 한계에 이르게되었다.In recent years, as the integration degree of semiconductor devices increases, the design rule decreases. Accordingly, the size of the device isolation layer separating the semiconductor devices from the semiconductor devices is also reduced by the same scale, so that a conventional device separation method such as LOCOS, PBL, etc. Application has reached its limit.
이를 해결하기 위해 적용된 STI 방법은 반도체기판상에 반도체기판과 식각선택비가 양호한 질화막을 형성하고, 질화막을 하드마스크(Hardmask)로 사용하기 위해 질화막을 포토리소그래피 방법으로 패터닝하여 질화막 패턴을 형성하고, 질화막 패턴을 하드 마스크로 사용하여 반도체기판을 소정 깊이로 건식 식각 방법으로 패터닝하여 트렌치를 형성한 후, 트렌치에 절연막을 매립시킨 후 화학적기계적연마(Chemical Mechanical Polishing; CMP)하여 트렌치에 매립되는 필드절연막을 형성한다.The STI method applied to solve this problem is to form a nitride film having a good etching selectivity with a semiconductor substrate on the semiconductor substrate, and to form a nitride film pattern by patterning the nitride film by photolithography to use the nitride film as a hard mask. Using the pattern as a hard mask, the semiconductor substrate is patterned by dry etching to a predetermined depth to form a trench, an insulating film is embedded in the trench, and chemical mechanical polishing (CMP) is used to fill a field insulating film embedded in the trench. Form.
최근에는 대부분의 메모리 장치에서 소자간 분리를 위해 트렌치에 매립되는 물질로 고밀도 플라즈마 산화막(High Density Plasma Oxide) 예컨대 USG(Undoped Silicate Glass)을 이용하고 있다.Recently, high-density plasma oxide (USG), such as USG (Undoped Silicate Glass), is used as a material embedded in a trench for isolation between devices in most memory devices.
도 1은 종래기술에 따른 반도체소자의 평면도이다.1 is a plan view of a semiconductor device according to the prior art.
도 1을 참조하면, 반도체기판(substrate)(11)에 섬(island) 형태의 활성영역(active region; ACT)을 정의하는 소자분리영역(isolation; ISO)이 형성되고, 활성영역(ACT)을 가로지르는 방향으로 반도체기판(11)상에 다수의 게이트(G)가 형성된다.Referring to FIG. 1, an isolation region (ISO) defining an island-type active region (ACT) is formed in a semiconductor substrate 11, and the active region ACT is formed. A plurality of gates G are formed on the semiconductor substrate 11 in the crossing direction.
도 1의 'A'은 활성영역(ACT)과 소자분리영역(ISO)의 경계 부분을 도시한 상세도로서, 활성영역(ACT)의 끝단이 게이트(G)에 걸치고 있다.'A' of FIG. 1 is a detailed view showing a boundary portion between the active region ACT and the device isolation region ISO. The end of the active region ACT extends over the gate G. As shown in FIG.
도 2a 내지 도 2c는 도 1의 x-x'선에 따른 소자분리막의 형성 방법 도시한 공정 단면도이다.2A to 2C are cross-sectional views illustrating a method of forming a device isolation film along the line x-x 'of FIG. 1.
도 2a에 도시된 바와 같이, 반도체기판(11)상에 패드산화막(12)과 패드질화막(13)을 증착한다. 이때, 패드질화막(13)은 후속 화학적기계적연마(CMP) 공정에서 스톱층(Stop layer)으로 활용한다.As shown in FIG. 2A, a pad oxide film 12 and a pad nitride film 13 are deposited on the semiconductor substrate 11. In this case, the pad nitride layer 13 is used as a stop layer in a subsequent chemical mechanical polishing (CMP) process.
다음으로, 패드질화막(13)상에 감광막을 도포한 후 노광 및 현상으로 패터닝하여 트렌치를 형성하기 위한 소자분리마스크(iso mask, 도시 생략)를 형성한 다음, 소자분리마스크를 식각마스크로 이용하여 패드질화막(13)과 패드산화막(12)을 산화막식각장치에서 식각한다.Next, after forming a photoresist film on the pad nitride film 13 and patterned by exposure and development to form an isolation mask (iso mask, not shown) to form a trench, using an isolation mask as an etching mask The pad nitride film 13 and the pad oxide film 12 are etched by the oxide film etching apparatus.
계속해서, 소자분리마스크를 제거한 후, 패드질화막(13)을 식각마스크로 하여 패드산화막(12) 식각후 노출된 반도체기판(11)을 실리콘식각장치에서 소정 깊이로 식각하여 소자분리영역이 될 트렌치(14)를 형성한다.Subsequently, after the device isolation mask is removed, the semiconductor substrate 11 is etched to a predetermined depth in the silicon etching apparatus after the pad oxide film 12 is etched using the pad nitride film 13 as an etching mask to form a device isolation region. (14) is formed.
도 2b에 도시된 바와 같이, 전면에 갭필(gapfill) 특성이 우수한 고밀도플라즈마산화막(high density plasma oxide; HDP)(15)을 증착하고, 패드질화막(13)이 노출될때까지 고밀도플라즈마산화막(15)을 화학적기계적연마하여 평탄화한다.As shown in FIG. 2B, a high density plasma oxide (HDP) film 15 having excellent gapfill characteristics is deposited on the entire surface, and the high density plasma oxide film 15 is exposed until the pad nitride film 13 is exposed. Chemical mechanical polishing to planarize.
이때, 패드질화막(13)이 소정 두께 더 연마되어 패드질화막(13)의 두께가 감소한다.At this time, the pad nitride film 13 is further polished by a predetermined thickness so that the thickness of the pad nitride film 13 is reduced.
계속해서, 패드질화막(13)을 제거한다. 이는 도 2c에 도시되어 있다.Subsequently, the pad nitride film 13 is removed. This is shown in Figure 2c.
도 2c에 도시된 바와 같이, 패드질화막(13) 제거후 고밀도플라즈마산화막(15)과 패드산화막(12)간, 고밀도플라즈마산화막(15)과 활성영역(ACT)간 단차가 발생된다.As shown in FIG. 2C, after the pad nitride layer 13 is removed, a step is generated between the high density plasma oxide layer 15 and the pad oxide layer 12 and the high density plasma oxide layer 15 and the active region ACT.
도 2d에 도시된 바와 같이, 고밀도플라즈마산화막(15)과 활성영역간 단차를완화시키기 위해 패드산화막(12)이 제거될때까지 화학적기계적연마에 의해 평탄화된 고밀도플라즈마산화막(15)을 습식식각으로 등방성식각하여 고밀도플라즈마산화막(15)으로 이루어진 트렌치구조의 소자분리막(16)을 형성한다.As shown in FIG. 2D, the planarized high density plasma oxide film 15 is isotropically etched by wet etching until the pad oxide film 12 is removed to alleviate the step difference between the high density plasma oxide film 15 and the active region. As a result, a trench isolation device isolation layer 16 including a high density plasma oxide layer 15 is formed.
이때, 패드질화막(13) 제거후 고밀도플라즈마산화막(15)과 패드산화막(12)간에 단차가 발생됨에 따라 고밀도플라즈마산화막(15)의 등방성 습식식각시 활성영역(ACT)과의 경계 부분에서 소자분리막(16)이 활성영역(ACT)보다 낮아지는 모우트 부분(M)이 발생된다.In this case, as the step is generated between the high density plasma oxide layer 15 and the pad oxide layer 12 after the pad nitride layer 13 is removed, the device isolation layer at the boundary between the high density plasma oxide layer 15 and the active region ACT during isotropic wet etching. The moat part M in which 16 is lower than the active area ACT is generated.
도 2e에 도시된 바와 같이, 모우트 부분(M)이 형성된 반도체기판(11) 전면에 게이트산화막(도시 생략)을 형성한 후, 게이트산화막상에 활성영역(ACT)과 소자분리막(16)의 경계부분에 걸치는 게이트전극(17)을 형성한다.As shown in FIG. 2E, after the gate oxide film (not shown) is formed on the entire surface of the semiconductor substrate 11 on which the moat portion M is formed, the active region ACT and the device isolation film 16 may be formed on the gate oxide film. A gate electrode 17 covering the boundary portion is formed.
만약, 활성영역(ACT)과 게이트전극(17)의 겹치는 면적이 늘어나면 다른 셀과의 간섭이 심해져 리프레쉬 특성이 나쁘게 된다. 반대로, 활성영역(ACT)과 게이트전극(17)이 겹치지 않으면 활성영역(ACT)의 면적이 감소하여 셀저항(캐패시터에서 활성영역에 이르는 직렬저항)이 너무 높아지는 문제가 있다.If the overlapping area of the active region ACT and the gate electrode 17 is increased, interference with other cells is increased, resulting in poor refresh characteristics. On the contrary, if the active region ACT and the gate electrode 17 do not overlap, the area of the active region ACT decreases and the cell resistance (series resistance from the capacitor to the active region) becomes too high.
따라서, 활성영역(ACT)을 게이트전극(17)과 겹치는 범위내에서 최대한 줄이면 DRAM의 리프레쉬 특성을 개선시킬 수 있다.Therefore, if the active region ACT is reduced as much as possible within the range overlapping with the gate electrode 17, the refresh characteristics of the DRAM can be improved.
그러나, 상술한 종래기술은 도 3에 도시된 것처럼, 활성영역(ACT)의 끝단이 게이트전극(17)에 걸치면서 활성영역(ACT)과 소자분리막(16)의 경계 부분인 모우트 부분(M)에 게이트 패터닝후 미처 식각되지 않은 잔유물(R)이 남아 이러한 잔유물(R)로 인해 활성영역(ACT)에 연결되는 후속 캐패시터의 콘택플러그와 게이트전극간 브릿지(bridge)가 발생되는 문제점이 있다.However, in the above-described conventional technique, as shown in FIG. 3, the moat portion M, which is a boundary between the active region ACT and the device isolation layer 16, with the end of the active region ACT across the gate electrode 17. After the gate patterning, the residue (R), which is not etched, remains, resulting in a bridge between the contact plug and the gate electrode of a subsequent capacitor connected to the active region ACT due to the residue R.
특히, 게이트전극이 활성영역에 걸쳐 형성되는 경우에 그 문제점은 더욱 심각하다.In particular, the problem is more serious when the gate electrode is formed over the active region.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 활성영역보다 낮아지는 모우트 부분이 형성됨에 따른 리프레쉬 특성 저하를 방지하는데 적합한 소자분리막의 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the prior art, and an object of the present invention is to provide a method for forming a device isolation film suitable for preventing a decrease in refresh characteristics due to the formation of a moat portion lower than the active region.
도 1은 종래기술에 따른 반도체소자의 평면도,1 is a plan view of a semiconductor device according to the prior art,
도 2a 내지 도 2e는 도 1의 x-x'선에 따른 공정 단면도,2A to 2E are cross-sectional views of a process taken along line x-x 'of FIG.
도 3은 도 1의 y-y'선에 따른 문제점을 도시한 도면,3 is a view showing a problem along the line y-y 'of FIG.
도 4a 내지 도 4c는 본 발명의 제1실시예에 따른 소자분리막의 형성 방법을 도시한 공정 단면도,4A to 4C are cross-sectional views illustrating a method of forming a device isolation film according to a first embodiment of the present invention;
도 5a 내지 도 5c는 본 발명의 제2실시예에 따른 소자분리막의 형성 방법을 도시한 공정 단면도.5A to 5C are cross-sectional views illustrating a method of forming an isolation layer in accordance with a second embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체기판 22 : 제1패드산화막21 semiconductor substrate 22 first pad oxide film
23 : 제2패드산화막 24 : 트렌치23: second pad oxide film 24: trench
25 : 고밀도플라즈마산화막 26 : 소자분리막25: high density plasma oxide film 26: device isolation film
27 : 게이트전극27: gate electrode
상기의 목적을 달성하기 위한 본 발명의 소자분리막의 형성 방법은 반도체기판상에 제1패드산화막, 제2패드산화막의 적층막을 형성하는 단계, 상기 적층막을 식각마스크로 상기 반도체기판을 소정 깊이로 식각하여 트렌치를 형성하는 단계;In order to achieve the above object, a method of forming a device isolation film according to the present invention includes forming a stacked film of a first pad oxide film and a second pad oxide film on a semiconductor substrate, and etching the semiconductor substrate to a predetermined depth using the laminated film as an etch mask. To form a trench;
상기 트렌치를 채울때까지 상기 적층막상에 절연막을 형성하는 단계, 상기 제2패드산화막의 표면이 노출될때까지 상기 절연막을 화학적기계적연마하여 평탄화하는 단계, 및 상기 제1,2패드산화막이 제거될때까지 상기 절연막을 습식식각하여 상기 트렌치에 매립되는 소자분리막을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.Forming an insulating film on the laminated film until the trench is filled, and chemically polishing and insulating the insulating film until the surface of the second pad oxide film is exposed, and then removing the first and second pad oxide films. And wet etching the insulating film to form an isolation layer buried in the trench.
또한, 본 발명의 소자분리막의 형성 방법은 반도체기판상에 패드산화막을 형성하는 단계, 상기 패드산화막을 식각마스크로 상기 반도체기판을 소정 깊이로 식각하여 트렌치를 형성하는 단계, 상기 트렌치를 채울때까지 상기 패드산화막상에 절연막을 형성하는 단계, 상기 패드산화막의 표면이 노출될때까지 상기 절연막을 화학적기계적연마하여 평탄화하는 단계, 및 상기 패드산화막이 제거될때까지 상기 절연막을 습식식각하여 상기 트렌치에 매립되는 소자분리막을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.In addition, the method of forming a device isolation film of the present invention comprises the steps of: forming a pad oxide film on a semiconductor substrate, etching the semiconductor substrate to a predetermined depth with the pad oxide film as an etch mask to form a trench, until the trench is filled; Forming an insulating film on the pad oxide film, planarizing the insulating film by chemical mechanical polishing until the surface of the pad oxide film is exposed, and wet etching the insulating film until the pad oxide film is removed to fill the trench. It characterized by comprising a step of forming a device isolation film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 4a 내지 도 4c는 본 발명의 제1실시예에 따른 소자분리막의 형성 방법을 도시한 공정 단면도이다.4A to 4C are cross-sectional views illustrating a method of forming a device isolation film according to a first embodiment of the present invention.
도 4a에 도시된 바와 같이, 반도체기판(21)상에 제1패드산화막(22)과 제2패드산화막(23)을 증착한다. 이때, 제2패드산화막(23)은 후속 화학적기계적연마(CMP) 공정에서 스톱층으로 활용하고, 제1패드산화막(22)은 후속 반도체기판(21) 식각시 식각패드로 이용한다.As shown in FIG. 4A, the first pad oxide film 22 and the second pad oxide film 23 are deposited on the semiconductor substrate 21. In this case, the second pad oxide layer 23 is used as a stop layer in a subsequent chemical mechanical polishing (CMP) process, and the first pad oxide layer 22 is used as an etch pad when the subsequent semiconductor substrate 21 is etched.
이때, 제1패드산화막(22)은 50Å∼100Å의 두께로 형성되고, 제2패드산화막(23)은 종래 패드질화막의 두께와 동일한 1500Å∼2000Å의 두께로 형성되며, 이들 패드산화막들은 반도체기판상에 증착 및 성장시킬 수 있다.In this case, the first pad oxide film 22 is formed to have a thickness of 50 kPa to 100 kPa, and the second pad oxide film 23 is formed to have a thickness of 1500 kPa to 2000 kPa which is the same as that of a conventional pad nitride film. Can be deposited and grown.
다음으로, 제2패드산화막(23)상에 감광막을 도포한 후 노광 및 현상으로 패터닝하여 트렌치를 형성하기 위한 소자분리마스크(iso mask, 도시 생략)를 형성한다음, 소자분리마스크를 식각마스크로 이용하여 제2패드산화막(23)과 제1패드산화막(22)을 동시에 식각하거나, 제1패드산화막(22)에서 식각이 멈출때까지 제2패드산화막(23)을 먼저 식각한 후 얇은 두께의 제1패드산화막(22)을 연속해서 식각하므로써 반도체기판(21)의 식각 손실을 줄일 수 있다.Next, after forming a photoresist film on the second pad oxide film 23 and patterning it by exposure and development to form an isolation mask (iso mask, not shown) to form a trench, the device isolation mask as an etching mask The second pad oxide layer 23 and the first pad oxide layer 22 are simultaneously etched or the second pad oxide layer 23 is first etched until the etching stops at the first pad oxide layer 22, and then a thin thickness is obtained. The etching loss of the semiconductor substrate 21 can be reduced by continuously etching the first pad oxide film 22.
계속해서, 소자분리마스크를 제거한 후, 제2패드산화막(23)을 식각마스크로 하여 제1패드산화막(22) 식각후 노출된 반도체기판(21)을 소정 깊이로 식각하여 소자분리영역이 될 트렌치(24)를 형성한다.Subsequently, after removing the device isolation mask, the trench to be a device isolation region by etching the exposed semiconductor substrate 21 to a predetermined depth after etching the first pad oxide film 22 using the second pad oxide film 23 as an etching mask. To form (24).
도 4b에 도시된 바와 같이, 전면에 갭필 특성이 우수한 고밀도플라즈마산화막(HDP oxide)(25)을 증착하고, 제2패드산화막(23)이 노출될때까지 고밀도플라즈마산화막(25)을 화학적기계적연마하여 평탄화한다.As shown in FIG. 4B, a high density plasma oxide film (HDP oxide) 25 having excellent gap fill characteristics is deposited on the entire surface, and the high density plasma oxide film 25 is chemically mechanically polished until the second pad oxide film 23 is exposed. Flatten.
이때, 제2패드산화막(23)이 소정 두께 더 연마되어 제2패드산화막(23)의 두께가 감소한다.At this time, the second pad oxide film 23 is further polished by a predetermined thickness, thereby reducing the thickness of the second pad oxide film 23.
도 4c에 도시된 바와 같이, 제1 및 제2패드산화막(22,23)을 제거하여 활성영역을 노출시키기 위해 제1,2 패드산화막(22,23)이 제거될때까지 고밀도플라즈마산화막(25)을 습식식각으로 등방성식각하여 고밀도플라즈마산화막(25)으로 이루어진 트렌치구조의 소자분리막(26)을 형성한다.As shown in FIG. 4C, the high density plasma oxide layer 25 is removed until the first and second pad oxide layers 22 and 23 are removed to remove the first and second pad oxide layers 22 and 23 to expose the active region. Isotropically etched by wet etching to form a device isolation film 26 having a trench structure formed of a high-density plasma oxide film 25.
종래에는 패드질화막을 제거하는 과정을 거치고, 이에 따라 고밀도플라즈마산화막이 활성영역보다 위로 돌출되어 있는 형태를 가져 단차가 발생되었으나, 본 발명은 패드질화막을 이용하지 않으므로, 패드질화막 제거공정없이 바로 단차가 없는 상태에서 제1,2패드산화막(22,23)을 제거하므로써 전체적으로 소자분리막(26)인고밀도플라즈마산화막(25)의 두께만 낮추고 모우트 발생을 방지한다.Conventionally, a step of removing the pad nitride film is performed, and accordingly, a step is generated because the high density plasma oxide film protrudes above the active region. However, the present invention does not use the pad nitride film. By removing the first and second pad oxide films 22 and 23 in a non-existent state, the thickness of the high-density plasma oxide film 25, which is the device isolation film 26, is reduced as a whole, and the occurrence of moats is prevented.
더욱이, 습식 등방성 식각시, 고밀도플라즈마산화막(25)과 제2패드산화막 (23) 및 제1패드산화막(21)은 동일한 식각특성을 갖는 산화막계열이므로 식각률 차이가 발생되지 않아 모우트 부분이 발생되지 않는다.In addition, during wet isotropic etching, since the high density plasma oxide layer 25, the second pad oxide layer 23, and the first pad oxide layer 21 are oxide series having the same etching characteristics, no etch rate difference is generated so that no moat portion is generated. Do not.
후속 공정으로, 반도체기판(11) 전면에 게이트산화막(도시 생략)을 형성한 후, 게이트산화막상에 활성영역(ACT)과 소자분리막(26)의 경계부분에 걸치는 게이트전극(27)을 형성한다.In a subsequent process, a gate oxide film (not shown) is formed on the entire surface of the semiconductor substrate 11, and then a gate electrode 27 is formed on the gate oxide film, which covers the boundary between the active region ACT and the device isolation layer 26. .
도 5a 내지 도 5c는 본 발명의 제2실시예에 따른 소자분리막의 형성 방법을 도시한 공정 단면도이다.5A to 5C are cross-sectional views illustrating a method of forming a device isolation film according to a second embodiment of the present invention.
도 5a에 도시된 바와 같이, 반도체기판(31)상에 두꺼운 패드산화막(32)을 증착한다. 이때, 패드산화막(32)은 후속 화학적기계적연마(CMP) 공정에서 스톱층으로 활용되며 반도체기판(31) 식각시 패드 역할로도 활용된다.As shown in FIG. 5A, a thick pad oxide film 32 is deposited on the semiconductor substrate 31. In this case, the pad oxide layer 32 is used as a stop layer in a subsequent chemical mechanical polishing (CMP) process and also serves as a pad when etching the semiconductor substrate 31.
이때, 패드산화막(32)은 1500Å∼2000Å의 두께로 형성되며, 반도체기판(31)상에 증착 및 성장시킬 수 있다.In this case, the pad oxide film 32 is formed to a thickness of 1500 to 2000 Å, and can be deposited and grown on the semiconductor substrate 31.
다음으로, 패드산화막(32)상에 감광막을 도포한 후 노광 및 현상으로 패터닝하여 트렌치를 형성하기 위한 소자분리마스크(iso mask, 도시 생략)를 형성한 다음, 소자분리마스크를 식각마스크로 이용하여 패드산화막(32)을 식각한다.Next, after forming a photoresist film on the pad oxide film 32 and patterning by exposure and development to form a device isolation mask (iso mask, not shown) to form a trench, using the device isolation mask as an etching mask The pad oxide film 32 is etched.
계속해서, 소자분리마스크를 제거한 후, 패드산화막(32)을 식각마스크로 하여 패드산화막(32) 식각후 노출된 반도체기판(31)을 소정 깊이로 식각하여 소자분리영역이 될 트렌치(33)를 형성한다.Subsequently, after the device isolation mask is removed, the trench 33 to be a device isolation region is etched by etching the exposed semiconductor substrate 31 to a predetermined depth using the pad oxide film 32 as an etch mask. Form.
도 5b에 도시된 바와 같이, 전면에 갭필 특성이 우수한 고밀도플라즈마산화막(HDP oxide)(34)을 증착한다. 이때, 제1실시예 및 종래와 다르게 고밀도플라즈마산화막(34)의 증착 두께를 감소시킬 수 있다. 즉, 제1패드산화막과 패드질화막을 증착하지 않으므로 고밀도플라즈마산화막(34)이 증착될 두께를 감소시킨다.As shown in FIG. 5B, a high density plasma oxide film (HDP oxide) 34 having excellent gap fill characteristics is deposited on the entire surface. In this case, unlike the first embodiment and the prior art, the deposition thickness of the high density plasma oxide layer 34 may be reduced. That is, since the first pad oxide film and the pad nitride film are not deposited, the thickness at which the high density plasma oxide film 34 is to be deposited is reduced.
다음으로, 패드산화막(32)이 소정 두께가 남을때까지 고밀도플라즈마산화막(34)을 화학적기계적연마하여 평탄화한다. 이때, 패드산화막(32)이 소정 두께 남도록 하는 이유는 패드산화막(32)이 모두 제거되어 반도체기판(31)이 드러나는 경우 활성영역(ACT)이 손상받는 것을 방지하기 위함이다.Next, the high density plasma oxide film 34 is chemically mechanically polished and planarized until the pad oxide film 32 has a predetermined thickness. In this case, the reason why the pad oxide layer 32 remains a predetermined thickness is to prevent the active region ACT from being damaged when all of the pad oxide layer 32 is removed to expose the semiconductor substrate 31.
한편, 화학적기계적연마시 제1실시예의 제1패드산화막 두께까지 진행하는 경우, 후속 패드산화막을 제거하기 위한 습식세정시 부담을 감소시킬 수 있고, 패드산화막(32)을 두껍게 증착하여 화학적기계적연마시 반도체기판(31)의 활성영역(ACT)이 손상되는 것을 방지한다.On the other hand, when the chemical mechanical polishing proceeds to the thickness of the first pad oxide film of the first embodiment, the burden during wet cleaning to remove the subsequent pad oxide film can be reduced, and the chemical vapor deposition by thickly depositing the pad oxide film 32 The active area ACT of the semiconductor substrate 31 is prevented from being damaged.
도 5c에 도시된 바와 같이, 패드산화막(32)을 제거하여 활성영역을 노출시키기 위해 패드산화막(32이 제거될때까지 고밀도플라즈마산화막(34)을 습식식각으로 등방성식각하여 고밀도플라즈마산화막(34)으로 이루어진 트렌치구조의 소자분리막(35)을 형성한다.As shown in FIG. 5C, to remove the pad oxide layer 32 to expose the active region, the high density plasma oxide layer 34 isotropically etched by wet etching until the pad oxide layer 32 is removed to the high density plasma oxide layer 34. A device isolation film 35 having a formed trench structure is formed.
이때, 습식 등방성 식각시, 고밀도플라즈마산화막(34)과 패드산화막(32)은 동일한 식각특성을 갖는 산화막계열이므로 식각률 차이가 발생되지 않아 모우트 부분이 발생되지 않는다.At this time, when the wet isotropic etching, the high-density plasma oxide film 34 and the pad oxide film 32 is an oxide film series having the same etching characteristics, so there is no difference in etch rate and no moat portion is generated.
더욱이, 종래에 실시했던 패드질화막 제거공정없이 바로 습식식각을 실시하므로 전체적으로 두께만 낮아지고 모우트 부분은 발생하지 않는다.Furthermore, since wet etching is performed immediately without the conventional pad nitride film removing process, only the thickness is lowered as a whole and no moat portion is generated.
후속 공정으로, 반도체기판(31) 전면에 게이트산화막(도시 생략)을 형성한 후, 게이트산화막상에 활성영역(ACT)과 소자분리막(35)의 경계부분에 걸치는 게이트전극(36)을 형성한다.In a subsequent process, a gate oxide film (not shown) is formed on the entire surface of the semiconductor substrate 31, and then a gate electrode 36 is formed on the gate oxide film, which extends over the boundary between the active region ACT and the device isolation layer 35. .
상술한 것처럼, 본 발명은 소자분리막의 모우트 부분의 발생을 억제하므로 후속 게이트패터닝후 잔유물이 남지 않아 게이트전극과 후속 캐패시터의 콘택플러그간 브릿지를 방지한다.As described above, the present invention suppresses the generation of the moat portion of the device isolation film, and thus no residue remains after the subsequent gate patterning, thereby preventing the bridge between the contact plug of the gate electrode and the subsequent capacitor.
한편, 본 발명에서는 패드질화막을 이용하지 않는데, 패드산화막과 패드질화막을 이용할 경우에는 패드질화막과 패드산화막은 산화막식각장치에서 식각하고 반도체기판은 실리콘식각장치에서 식각하는 복잡한 공정이나, 제1,2패드산화막(22,23)만을 사용하는 본 발명은 실리콘식각장치에서 제1,2패드산화막과 반도체기판을 동시에 식각할 수도 있고, 패드질화막 제거공정이 생략되므로 공정이 단순하다.In the present invention, the pad nitride film and the pad nitride film are not used. However, when the pad oxide film and the pad nitride film are used, the pad nitride film and the pad oxide film are etched by the oxide etching device and the semiconductor substrate is etched by the silicon etching device. In the present invention using only the pad oxide films 22 and 23, the first and second pad oxide films and the semiconductor substrate may be simultaneously etched in the silicon etching apparatus, and the process of removing the pad nitride film is omitted.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명은 소자분리막과 활성영역의 경계 부분에 모우트가 발생되는 것을 억제하므로써 리프레쉬 특성을 개선시킬 수 있는 효과가 있다.The present invention described above has the effect of improving the refresh characteristics by suppressing the occurrence of the moat at the boundary between the device isolation layer and the active region.
또한, 패드질화막 증착 및 제거 공정을 생략하므로써 공정을 단순화시키며, 이로써 수율 및 신뢰성을 향상시킬 수 있는 효과가 있다.In addition, the process of simplifying the process by omitting the pad nitride film deposition and removal process has the effect of improving the yield and reliability.
Claims (5)
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| KR1020010081171A KR20030050668A (en) | 2001-12-19 | 2001-12-19 | Method for forming isolation layer |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100881414B1 (en) * | 2002-10-24 | 2009-02-05 | 매그나칩 반도체 유한회사 | Method for forming isolation layer of semiconductor device |
| KR100881413B1 (en) * | 2002-10-24 | 2009-02-05 | 매그나칩 반도체 유한회사 | Method for forming isolation layer of semiconductor device |
| CN102543776A (en) * | 2010-12-17 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Method for forming redistribution of welding pad |
-
2001
- 2001-12-19 KR KR1020010081171A patent/KR20030050668A/en not_active Application Discontinuation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100881414B1 (en) * | 2002-10-24 | 2009-02-05 | 매그나칩 반도체 유한회사 | Method for forming isolation layer of semiconductor device |
| KR100881413B1 (en) * | 2002-10-24 | 2009-02-05 | 매그나칩 반도체 유한회사 | Method for forming isolation layer of semiconductor device |
| CN102543776A (en) * | 2010-12-17 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Method for forming redistribution of welding pad |
| CN102543776B (en) * | 2010-12-17 | 2014-04-02 | 中芯国际集成电路制造(上海)有限公司 | Method for forming redistribution of welding pad |
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