KR20080001279A - Method for forming isolation layer in semiconductor device - Google Patents

Abstract

A method for forming an isolation layer of a semiconductor device is provided to easily control the effective height of an SOD(Spin On Dielectric) layer by partially recessing the SOD layer using dry etching. A gate insulating layer(31), a gate conductive layer(32), and a pad nitride layer(34) are sequentially formed on a substrate(30). A trench is formed in the substrate. A liner nitride layer(40) is formed on the trench. An SOD layer(41B) is filled in the trench. The SOD layer is planarized to be not exposed the pad nitride layer. The SOD layer is partially recessed by dry etching. An HDP(High Density Plasma) is formed on the SOD layer.

Description

METHODS FOR FORMING ISOLATION LAYER IN SEMICONDUCTOR DEVICE}

1A to 1D are cross-sectional views illustrating a method of forming an isolation layer in a general flash memory device.

2A to 2H are cross-sectional views illustrating a method of forming an isolation layer in a flash memory device according to an embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

30: substrate

31: high voltage gate oxide

32: polysilicon film

33: buffer oxide film

34: pad nitride film

35: hard mask oxide film

36 hard mask nitride film

37: photosensitive film pattern

39A, 39B: first and second trenches

40: liner HDP film

41, 41A, 41B: SOD film

42, 45: CMP process

43: dry etching process

44: HDP film

47: device isolation film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technology of a semiconductor device, and more particularly, to a method of forming an isolation layer of a flash memory device.

As the degree of integration of semiconductor devices increases, the width of device isolation layers in a shallow trench isolation (STI) process is further reduced. Conventionally, device isolation films using HDP (High Density Plsma) chemical vapor deposition (CVD) have been used. However, as the width of the trench is reduced, there is a limit to the fine pattern embedding characteristics of the conventional HDP film. This problem is no exception to flash memory devices. For example, at present, there is a limitation in embedding characteristics in forming a device isolation layer using an HDP film as in the conventional manufacturing process of a flash memory device.

In addition, the SOD (Spin On Dilectric) film having excellent fluidity has excellent fine pattern embedding characteristics, but the density of the buried SOD film is low so that the device insulation role is lost due to the loss of the SOD film in the subsequent etching and cleaning process, and the subsequent ion implantation process. There is a problem in that deterioration of device characteristics due to ion permeation occurs in the SOD film having a low density, which is problematic in use alone.

Accordingly, recently, a method of forming an isolation layer by depositing an SOD film having excellent fluidity and then depositing an HDP film has been proposed. This is a method of embedding a hard-to-embedded portion with an SOD film. Hereinafter, a method of forming the device isolation film of the flash memory device will be described in detail with reference to the accompanying drawings.

First, as shown in FIG. 1A, the gate oxide film 11 / the floating silicon polysilicon film 12 / the buffer oxide film 13 / the pad nitride film 14 / the hard mask oxide film 15 on the substrate 10. A laminated film of the hard mask nitride film 16 is formed. Then, a trench 17 having a predetermined depth is formed in the substrate 10 through an etching process using a predetermined photoresist pattern.

Subsequently, as shown in FIG. 1B, a strip process is performed to remove the photoresist pattern, followed by a wet etching process to perform hard mask nitride film 16 (see FIG. 1A) and hard mask oxide film 15 (see FIG. 1A). ).

Next, a monthly oxidation process is performed to form a monthly oxide film (not shown) along the inner surfaces of the plurality of trenches 17 (see FIG. 1A). Then, a thin liner HDP film 19 is deposited so that a portion of the trench 17 is embedded over the entire structure on which the monthly oxide film is formed.

Subsequently, the SOD film 20 having excellent fluidity is deposited on the liner HDP film 19 so that the entire trench 17 is embedded.

Subsequently, as illustrated in FIG. 1C, a CMP process 21 (hereinafter referred to as first CMP) is performed to planarize the SOD film 20A. In the first CMP, the SOD film 20A is planarized using the pad nitride film 14 as a planarization stop film.

Subsequently, as shown in FIG. 1D, the wet cleaning process is performed to recess the SOD film 20B. Then, the HDP film 23 is deposited on the SOD film 20B so that the trench 17 (see FIG. 1A) is embedded, and then the HDP film 23 is performed by performing a CMP process (hereinafter, referred to as a second CMP). ) Is flattened. In the second CMP, the HDP film 23 is planarized using the pad nitride film 14 as a planarization stop film.

However, when the SOD film 20B is recessed in the wet cleaning process as shown in FIG. 1D, it is difficult to control the effective height (EFH, EFfective Hight) of the SOD film 20B. In this case, the effective height refers to the remaining height of the SOD film 20B to be used as the device isolation film. Due to the difficulty in controlling the effective height, when the SOD film 20B is excessively recessed, the aspect ratio of the trench 17 of the portion where the HDP film 23 is to be deposited is increased to reduce the embedding characteristics of the HDP film 23. Occurs. For example, there is a problem that voids (see 'V' region) occur in the HDP film 23.

In addition, according to the related art, as shown in FIGS. 1C and 1D, the first and second CMPs are performed. In the second CMP, the pad nitride film 14 is used as the planarization stop film. There is a fear that all of the nitride films 14 are lost and cannot function as planarization stop films.

Accordingly, an object of the present invention is to provide a method for forming a device isolation film of a semiconductor device capable of controlling the effective height of the SOD film to an optimum height when the device isolation film is formed using the SOD film. have.

Another object of the present invention is to provide a method of forming a device isolation film of a semiconductor device capable of minimizing a loss of the planarization stop film during the planarization process for forming a device isolation film.

According to an aspect of the present invention, a gate insulating film, a gate conductive film, and a pad nitride film are sequentially formed on a substrate, and an etching process using a hard mask pattern is performed to form trenches in the substrate. Forming a liner insulating film on the entire structure surface including the trench so that a portion of the trench is buried, depositing a SOD film on the liner insulating film so as to fill the trench, and exposing the pad nitride film. Planarizing the SOD film to an upper portion of the pad nitride film so as to prevent the pad nitride film from being formed, recessing the SOD film to a predetermined depth by performing a dry etching process, and forming an HDP film on the SOD film so as to be isolated in the trench. A device isolation film forming method of a semiconductor device is provided.

Recently, a technique of using a SOD film with excellent fluidity and depositing an HDP film on top of the device isolation film is proposed in forming a device isolation film in a relatively difficult part, that is, a buried property is deteriorated. When applying the technology, it was difficult to control the effective height of the SOD film. In addition, when the HDP film is planarized, there is a concern that all of the pad nitride films serving as planarization stop films may be lost.

In order to solve this problem, the present invention does not use the pad nitride film as a planarization stop film during the first CMP to planarize the SOD film, but stops the CMP at the top of the pad nitride film once, and then recesses the SOD film by a predetermined depth through a dry etching process. In addition, the effective height of the SOD film can be precisely controlled and the loss of the pad nitride film can be minimized.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

2A to 2H are cross-sectional views illustrating a method of forming an isolation layer of a flash memory device according to an exemplary embodiment of the present invention. Here, for example, the description will be limited to the high voltage region where the high voltage transistor is to be formed. This is because the steps of forming the gate insulating film in the high voltage region and the low voltage region are different because the thicknesses of the gate insulating film formed in the high voltage region and the gate insulating film formed in the low voltage region where the low voltage transistor is to be formed are different from each other.

First, as shown in FIG. 2A, a high voltage gate oxide layer 31 is formed on the substrate 30 in the high voltage region. Then, a floating silicon polysilicon film 32 is deposited on the high voltage gate oxide film 31. For example, the polysilicon film 32 is deposited to a thickness of 1000 kPa or less.

Subsequently, the buffer oxide film 33 and the pad nitride film 34 are sequentially deposited on the polysilicon film 32. Here, the pad nitride film 34 is preferably deposited to a thickness of 500 kPa or less.

Subsequently, the hard mask oxide film 35 and the hard mask nitride film 36 which are used as hard masks are deposited on the pad nitride film 34 in order. For example, the hard mask oxide film 35 and the hard mask nitride film 36 are each deposited to a thickness of 500 kPa or less.

Subsequently, as shown in FIG. 2B, a predetermined recess photoresist layer pattern 37 is formed on the hard mask nitride layer 36, and then an etching process using the photoresist layer pattern 37 as a mask is performed to perform a hard mask nitride layer. 36 and the hard mask oxide film 35 are etched. In this case, the photoresist pattern 37 is used to define an isolation region of a flash memory device, and has a structure in which the isolation regions are open.

Subsequently, the etching process using the photoresist pattern 37 as a mask or the etched hard mask pattern-hard mask nitride film 36 and the hard mask oxide film 35 as a mask is performed to provide a pad nitride film 34 and a buffer oxide film ( 33), the polysilicon film 32, the high voltage gate oxide film 31 and the substrate 30 are etched to a predetermined depth. As a result, a plurality of first and second trenches 39A and 39B having different widths and depths are formed in the cell region CELL in which the flash memory cell is to be formed and in the peripheral region PERI in which other peripheral elements are to be formed. . For example, a plurality of first trenches 39A having a narrower width and a lower depth than the ferry region PERI are formed in the cell region CELL having a relatively high pattern density.

Subsequently, as illustrated in FIG. 2C, a strip process is performed to remove the photoresist pattern 37 (see FIG. 2B), followed by a wet etching process to perform hard mask nitride layer 36 (see FIG. 2B) and a hard mask. The oxide film 35 (see FIG. 2B) is removed.

Next, a monthly oxidation process is performed to form a monthly oxide film (not shown) along the inner surfaces of the plurality of first and second trenches 39A and 39B. At this time, the monthly oxide film is deposited to a thickness of 100 kPa or less.

Subsequently, a thin liner HDP film 40 is deposited so that the entire trench 39A, 39B is not embedded on the entire structure on which the monthly oxide film is formed. For example, the liner HDP film 40 is deposited to a thickness of 1000 kPa or less. This reduces the depth of each of the first and second trenches 39A and 39B as the bottom portions of the trenches 39A and 39B are higher than in the previous process.

Next, as shown in FIG. 2D, an SOD film 41 having excellent fluidity is deposited on the liner HDP film 40 so that the first and second trenches 39A and 39B are embedded. Here, the SOD film 41 is formed so that the thickness in the cell region CELL having a high pattern density is thicker than the thickness in the ferry region PERI. In addition, the SOD layer 41 is formed by spin coating using chemicals such as silicate, siloxane, Methyl SilseQuoxane (MSQ), Hydrogen SilseQuioxane (HSQ), perhydrosilazane (TCPS), and polysilazane.

Next, as shown in FIG. 2E, the CMP process 42 is performed to planarize the SOD film 41A. In the CMP process 42, the planarization process is stopped on the pad nitride layer 34 so that the pad nitride layer 34 is not exposed unlike the conventional method. That is, in the conventional CMP process for planarizing the SOD film, the pad nitride film was used as the planarization stop film so that the CMP process was immediately stopped on the pad nitride film. However, in the embodiment of the present invention, a point spaced a predetermined distance from the upper surface of the pad nitride film 34. To stop the CMP process. Therefore, the pad nitride film 34 is prevented from being lost during the CMP process of planarizing the SOD film 41A so that the pad nitride film 34 may function as a planarization stop film during another planarization process.

For example, when the SOD film 41A is planarized, a point spaced apart from the pad nitride film 34 by a predetermined thickness is used as the starting point of the planarization stop of the SOD film 41A. Preferably, the point spaced at a maximum of 500 ms is the starting point of the flattening stop.

Next, as shown in FIG. 2F, unlike the conventional method, the dry etching process 43 is performed to recess the SOD film 41B. That is, in the past, the wet cleaning process was performed to recess the SOD film, which is difficult to control the effective height of the SOD film. Thus, in the embodiment of the present invention, the dry etching process in which the effective height of the SOD film 41B is easily controlled is performed. Then, the SOD film 41B is recessed. Therefore, according to the exemplary embodiment of the present invention, the effective height of the SOD film 41B may be controlled to the optimum height during the etching process for recessing the SOD film 41B. Preferably, during the dry etching process 43, the SOD film 41B is recessed from the upper surface of the substrate 30 to a depth of up to 500 kPa.

In the dry etching process 43, since the liner HDP film 40A which is almost similar to the etch selectivity with the SOD film 41B is also partially etched, the liner HDP film 40 on the pad nitride film 34 is removed.

Subsequently, as shown in FIG. 2G, the HDP film 44 is deposited by CVD on the entire structure so that the first and second trenches 39A and 39B are embedded. At this time, the HDP film 44 is deposited to a thickness of 5000 kPa or less. Then, the CMP process 45 is performed by the planarization process to remove the surface level difference between the HDP film 44 and the pad nitride film 34. For example, in the CMP process 45 of the HDP film 44, the pad nitride film 34 is a planarization stop film.

Subsequently, as illustrated in FIG. 2H, the pad nitride film 34 is removed by performing a wet etching process, and the buffer oxide film 33 is removed by performing a cleaning process. In this cleaning process, the HDP film 44 is recessed along with the buffer oxide film 33 at a predetermined depth. This increases the area of the dielectric film to be subsequently deposited.

Subsequently, a pre-cleaning process for removing impurities is performed before the dielectric film is deposited. This completes the device isolation film 47 having the liner HDP film 40 / SOD film 41B / HDP film 44 laminated film structure having the optimum effective height in the trenches 39A and 39B.

Although the embodiments of the present invention have been described with limited to the high voltage region, this technique of the present invention can be applied to the low voltage region.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, in the CMP process for planarizing the SOD film, the CMP process is stopped at the top of the pad nitride film without stopping the pad nitride film as the planarization stop film, and then the SOD film is removed at a predetermined depth through the dry etching process. By accessing, the effective height of the SOD film can be easily controlled to the optimum height and the loss of the pad nitride film can be minimized.

Claims (10)

Sequentially forming a gate insulating film, a gate conductive film, and a pad nitride film on the substrate; Forming a trench in the substrate by performing an etching process using a hard mask pattern; Forming a liner insulating film on the entire structure surface including the trench such that a portion of the trench is embedded; Depositing a SOD film on the liner insulating film so that the trench is buried; Planarizing the SOD layer to an upper portion of the pad nitride layer so that the pad nitride layer is not exposed; Performing a dry etching process to recess the SOD film to a predetermined depth; And Forming an HDP film on the SOD film to be isolated in the trench Device isolation film forming method of a semiconductor device comprising a. The method of claim 1, The method of forming a device isolation film of a semiconductor device during the dry etching process to recess the SOD film to a depth of 10 ~ 500Å from the upper surface of the substrate. The method of claim 2, The planarization of the SOD film may include: A method of forming a device isolation film for a semiconductor device by performing a planarization stop point at a point spaced from the pad nitride film upper surface by a thickness of 10 to 500 Å. The method of claim 3, wherein The hard mask pattern is Sequentially forming an oxide film for a hard mask and a nitride film on the pad nitride film; And Etching the hard mask nitride layer and the oxide layer through a predetermined photoresist pattern A device isolation film forming method of a semiconductor device, including forming. The method of claim 4, wherein Before forming the liner insulating film, And forming a monthly oxide film along an inner surface of the trench to protect sidewalls of the trench. The method according to any one of claims 1 to 5, Forming the HDP film, Depositing an HDP film on the SOD film to fill the trench; And Performing a planarization process using the pad nitride film as a planarization stop film Device isolation film forming method of a semiconductor device comprising a. The method of claim 6, After the gate conductive film is formed, And forming a buffer oxide film on the gate conductive film. The method of claim 7, wherein After the HDP film is formed, Removing the pad nitride film; And Recessing the HDP film to a predetermined depth while removing the buffer oxide film. Device isolation film forming method of a semiconductor device further comprising. The method of claim 6, And the gate conductive film is formed of a floating silicon polysilicon film of a flash memory device. The method of claim 6, The SOD film is a method of forming a device isolation layer of a semiconductor device formed by using a chemical such as silicate, siloxane, Methyl SilseQuoxane (MSQ), Hydrogen SilseQuioxane (HSQ), perhydrosilazane (TCPS), polysilazane.

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