KR20070098322A - Method for fabricating isolation layer in flash memory device - Google Patents

Abstract

A method for fabricating an isolation layer in a flash memory device is provided to improve the reliability of the flash memory device and secure the operational stability of the device by filling a material according to properties of a cell area and a peripheral circuit area. A method for fabricating an isolation layer in a flash memory device includes the steps of: forming trenches for isolating each device on a cell area and a peripheral circuit area of a semiconductor substrate(51); and filling an insulating film having a high reflow property in the trench formed on the cell area. The step of filling the insulating film in the trench includes the steps of: filling a first insulating film(58) having a high reflow property in the trench formed on the cell area; selectively removing the first insulating film(58) of the upper part of the peripheral circuit area; filling a second insulating film(61) in the trench formed on the peripheral circuit area; planarizing the first and second insulating films(58,61) simultaneously; and performing a cleaning process to control EFH(Effective Field Oxide Height).

Description

Device isolation method of flash memory device {METHOD FOR FABRICATING ISOLATION LAYER IN FLASH MEMORY DEVICE}

1 is a cross-sectional view showing a device isolation method of a flash memory device according to the prior art.

2A to 2F are cross-sectional views illustrating a device isolation method of a flash memory device according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

51 semiconductor substrate 52 tunnel oxide film

53 polysilicon film for floating gate 58 SOD film

59: HDP oxide film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of separating a flash memory device during a flash memory device manufacturing process.

The device isolation layer of the semiconductor device electrically isolates adjacent semiconductor devices. Due to the high integration tendency of semiconductor devices, it is required to develop a device isolation technology having an excellent insulating property while occupying a small area.

Currently, a widely used device isolation film process is a trench trench isolation (STI). The trench isolation layer is formed by etching a predetermined region of the semiconductor substrate to a predetermined depth, and then filling the trench with an insulating film. The trench device isolation film has a smaller area than the LOCOS (LOCal Oxidation of Silicon) device isolation film formed of a thermal oxide film in a predetermined region of the semiconductor substrate and has excellent insulation characteristics.

The semiconductor device may be classified into a volatile memory device and a nonvolatile memory device. Volatile memory devices include memory devices that lose data stored in memory cells, for example, DRAM devices and SRAM devices, when power supply is interrupted. In contrast, a nonvolatile memory device includes a memory device, for example, a flash memory device, which retains data stored in the memory cell even when power supply is interrupted.

1 is a cross-sectional view illustrating a device isolation layer of a flash memory device according to the prior art.

Referring to FIG. 1, a tunnel oxide film 12, a floating gate polysilicon film 13, a pad oxide film 14, and a pad nitride film are formed on an active region of a semiconductor substrate 11 divided into a cell region and a peripheral circuit region. 15) is formed, and the sidewall protective film 16 and the device isolation film 17 are formed in the device isolation region.

However, the device isolation film 17 in the cell region has a large aspect ratio of the device isolation trench due to the characteristics of the cell region, and thus, defects A and V are likely to occur when the device isolation layer 17 is embedded. Such void and seam (A) defects result in loss of device isolation film in subsequent recess cleaning, making it difficult to control effective field oxide height (EFH). This is noticeable in the cell region of the device as a flash memo. When the cell region and the peripheral circuit region are the same EFH, the loss of the device isolation layer in the peripheral circuit region occurs when the subsequent gate pattern is formed, which is a characteristic of the flash memory device. It acts as a cause of deterioration.

The present invention has been proposed to solve the above problems of the prior art, and provides a device isolation method of a flash memory device in which a buried defect does not occur when forming a device isolation film of a cell region and a peripheral circuit region in a flash memory device. The purpose.

According to an aspect of the present invention for achieving the above object, the step of sequentially depositing a tunnel oxide film, a floating silicon polysilicon film and a pad layer on a semiconductor substrate divided into a cell region and a peripheral circuit region, the cell region Etching the pad layer, the floating gate polysilicon film, the tunnel oxide film, and the semiconductor substrate to form a first trench of a predetermined depth, embedding a first insulating film in the first trench of the cell region, the peripheral portion Etching the pad layer, the floating gate polysilicon layer, the tunnel oxide layer, and the semiconductor substrate in the circuit region to form a second trench having a predetermined depth, and filling a second insulating layer in the second trench in the peripheral circuit region. And planarizing the first insulating film and the second insulating film, and performing a cleaning process for adjusting the effective field oxide film height (EFH). A device isolation method of a flash memory device is provided.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2A through 2F are cross-sectional views illustrating a device isolation method of a flash memory device according to an embodiment of the present invention.

First, as shown in FIG. 2A, a tunnel oxide film 52, a floating silicon polysilicon film 53, a hard mask nitride film 54, and a pad are formed on a semiconductor substrate 51 divided into a cell region and a peripheral circuit region. As a layer, the pad oxide film 55 and the pad nitride film 56 are sequentially deposited. The tunnel oxide film 52 may have a thickness of 80 to 120 GPa, the floating gate polysilicon film 53 may be 800 to 1000 GPa, and the hard mask nitride film 54 may have a thickness of 300 to 600 GPa. The pad oxide film 55 and the pad nitride film 56 are formed to have a thickness of 300 to 600 kPa.

Next, as shown in FIG. 2B, an etching mask covering the peripheral circuit region of the semiconductor substrate 51 and opening the device isolation region of the semiconductor substrate 51 of the cell region is formed. ) Is etched to form a first trench 57 for device isolation having a predetermined depth.

Next, the pad oxide layer 55 and the pad nitride layer 56 adjacent to the first trench 57 are removed.

Next, as illustrated in FIG. 2C, a spin on dielectric (SOD) film having a good reflow characteristic so that the first trench 57 is buried in the entire surface of the substrate on which the first trench 57 is formed. 58) Deposit. The SOD layer 58 may be formed of any one of silicate, siloxane, methyl silsequioxane (MSQ), hydrogen silsequioxane (HSQ), perhydropolysilazane, and polysilazane. do.

In addition, when the SOD film 58 is buried in the first trench 57 in the cell region, the SOD film 58 is deposited in the peripheral circuit region, which is performed by performing an OBN process, which is a wet etching process. The SOD film 58 deposited in the peripheral circuit area is removed. Here, the OBN process has a BOE solution of 300: 1 and a process time of 800 ~ 1200 seconds.

Next, as shown in FIG. 2D, the cell region of the semiconductor substrate 51 in which the SOD film 58 is embedded in the first trench 57 is covered, and among the peripheral circuit regions of the semiconductor substrate 51. An etching mask for opening the device isolation region is formed, and the semiconductor substrate 51 is etched using the etching barrier to form a second trench 60 for device isolation having a predetermined depth.

Subsequently, the pad oxide film 55 and the pad nitride film 56 adjacent to the second trench 60 are removed.

Next, as shown in FIG. 2E, the HDP (High Density Plasma) oxide layer 61 is buried in the device isolation second trench 60 by CVD (Chemical Vapor Deposition). Here, the HDP oxide layer 61 is formed to a thickness of 3000 ~ 5000Å.

Next, as shown in FIG. 2F, the SOD film 58 and the HDP oxide film 61 are subjected to chemical mechanical polishing (CMP) processes to planarize them.

Subsequently, the hard mask nitride film 54 is removed, and finally, a wet cleaning process is performed to control the height of the device isolation film (EFH).

As described above, according to the present invention, the cell region in which voids and seam defects occur when the device isolation region is formed so that voids and seam defects occur when the device isolation layer is embedded is formed as the device isolation layer, thereby providing an SOD film 58 having excellent embedding characteristics. In the peripheral circuit region where the device isolation region is wider than the cell region, the defect is solved by using the HDP oxide film 61.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

As described above, the present invention improves the buried property by embedding the device isolation layer of the cell region and the peripheral circuit region of the flash memory device with a material suitable for each region. Therefore, it is possible to improve the reliability of the flash memory device and to ensure the stability of the device operation.

Claims (16)

Forming trenches for device isolation in the cell region and the peripheral circuit region of the semiconductor substrate, respectively; And Filling an insulating film in the trench, but filling the insulating film with a good reflow characteristic in at least the trench formed in the cell region; Device isolation method of a flash memory device comprising a. The method of claim 1, The step of embedding the insulating film in the trench, Filling a first insulating film having a good reflow characteristic into a trench formed in the cell region; Selectively removing the first insulating layer on the peripheral circuit area; Embedding a second insulating film in the trench formed in the peripheral circuit region; Simultaneously planarizing the first insulating film and the second insulating film; And A device isolation method of a flash memory device comprising the step of performing a cleaning process for controlling the effective field oxide film height (EFH). The method of claim 2, And the first insulating film is formed of an SOD film. The method of claim 3, The SOD layer may be formed of any one of silicate, siloxane, methyl silsequioxane (MSQ), hydrogen silsequioxane (HSQ), perhydropolysilazane, and polysilazane (Polysilazane). Device isolation method of a memory device. The method of claim 2, The second insulating layer is a device for separating the flash memory device, characterized in that the HDP oxide film is formed by a CVD (Chemical Vapor Deposition) method and a thickness of 3000 ~ 5000Å. The method of claim 2, Selectively removing the first insulating layer on the peripheral circuit area, Forming a mask pattern on the first insulating layer to cover the cell region and to open the peripheral circuit region; And And wet etching the first insulating layer in the peripheral circuit area using the mask pattern as an etch barrier. The method of claim 6, The wet etching of the first insulating layer may be performed by an OBN process. The method of claim 7, wherein The OBN process is a device separation method of a flash memory device, characterized in that proceeds with a 300: 1 BOE solution and a processing time of 800 ~ 1200 seconds. Sequentially depositing a tunnel oxide film, a floating silicon polysilicon film, and a pad layer on a semiconductor substrate in which a cell region and a peripheral circuit region are divided; Etching the pad layer, the floating gate polysilicon layer, the tunnel oxide layer, and the semiconductor substrate in the cell region to form a first trench having a predetermined depth; Filling a first insulating film in the first trench in the cell region; Etching the pad layer, the floating gate polysilicon layer, the tunnel oxide layer, and the semiconductor substrate in the peripheral circuit area to form a second trench having a predetermined depth; Filling a second insulating film in the second trench in the peripheral circuit area; Planarizing the first insulating film and the second insulating film; And Step of cleaning process to control effective field oxide height (EFH) Device isolation method of a flash memory device comprising a. The method of claim 9, And separating the first insulating layer into a spin on dielectric (SOD) layer. The method of claim 10, The SOD layer may be formed of any one of silicate, siloxane, methyl silsequioxane (MSQ), hydrogen silsequioxane (HSQ), perhydropolysilazane, and polysilazane (Polysilazane). Device isolation method of a memory device. The method of claim 9, The second insulating layer is a device for separating the flash memory device, characterized in that the HDP oxide film is formed by a CVD (Chemical Vapor Deposition) method and a thickness of 3000 ~ 5000Å. The method of claim 9, Embedding a first insulating layer in the first trench of the cell region; Depositing a first insulating film having a good reflow characteristic on the entire surface of the substrate such that the trench formed in the cell region is embedded; And And selectively removing the first insulating layer on the peripheral circuit area. The method of claim 13, The removing of the first cut-off film on the upper portion of the peripheral circuit area is performed by the OBN process. The method of claim 14, The OBN process is a device separation method of a flash memory device, characterized in that proceeds with a 300: 1 BOE solution and a processing time of 800 ~ 1200 seconds. The method of claim 9, The pad layer may be formed by sequentially stacking a pad oxide film, a pad nitride film, and a hard mask nitride film each having a thickness of 300 to 600 Å.

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