KR101005699B1 - Method for manufacturing flash memory of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor flash memory manufacturing techniques, and more particularly to a method of forming a floating gate of a flash memory. In a conventional semiconductor flash memory manufacturing process, several etching processes are inevitably involved, and reliability of process stability is low. Accordingly, the present invention changes the floating gate semiconductor process of the flash memory to a process using a floating insulating mask by changing the complex floating gate forming process of the hard mask method using the oxide insulating film which is most widely used in the multilayer gate type flash memory. Can be simplified. In addition, by effectively forming the floating gate of the flash memory by coating the photoresist and the partial etching method by dry etching method, it is expected to have a significant influence on the development of the next-generation flash memory because the process can be performed stably.

Flash memory, floating gate

Description

METHOD FOR MANUFACTURING FLASH MEMORY OF SEMICONDUCTOR DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor flash memory manufacturing technology, and more particularly, to a semiconductor flash memory manufacturing method suitable for forming a floating gate in a flash memory manufacturing process of a semiconductor device.

Flash memory is a non-volatile memory, starting with the use of device components, and recently, as a mass storage application, as well as its utilization, chip density is increasing, and it is embedded in general logic and applied to various products. It is becoming.

Flash memory is a memory that has different characteristics from dynamic random access memory (DRAM) or static random access memory (SRAM) .It is a volatile memory that retains information even when power is turned off in electronic products. Mostly, only silicon (poly-silicon) and silicon substrates were used, but at present, the most stable property is to manufacture nonvolatile memory using two layers of polysilicon.

In this two-layer polysilicon, the gate at the bottom of the flash memory is called a floating gate, and a method of isolating a neighboring cell to form a floating gate is one of the technical skills in flash memory manufacturing. It is becoming a measure of.

Currently, in the case of a flash memory using two general polysilicon films, an oxide space etching method for forming a pattern by using a deposition insulator oxide film as a double layer when forming a floating gate is mainly performed in 0.25 μm or less manufacturing technology. Commonly used.

A semiconductor flash memory manufacturing method for forming such a floating gate will be described in detail with reference to FIGS. 1A to 1H.

First, as shown in FIG. 1A, a field on the semiconductor underlayer 100 is formed by using shallow trench isolation through thin silicon etching that defines an active region for isolating unit flash cells. An oxide film 102 is formed.

Next, after completing the well process for improving the leakage current through the silicon substrate or the performance of the unit transistor, the tunnel oxide 104, which is the most important oxide film of the flash cell, is thermally processed by about 100 kW. To grow.

In FIG. 1B, a first poly-silicon 106 to be used as a terminal of a floating gate is stacked on the semiconductor lower layer 100 on which the tunnel oxide layer 104 is formed to have a predetermined thickness, for example, about 1000 μs. In this case, the polysilicon used is doped polysilicon.

The first insulating layer 108 to be used as a hard mask is stacked on the polysilicon 106. As the insulating film at this time, for example, a TEOS oxide film is used as the LP (Low Pressure) oxide film, and the laminated thickness thereof is, for example, about 2300 kPa.

In FIG. 1C, a photoresist pattern 110 for forming a pattern to be used as a floating gate is formed. As described above, forming a cell having a minimum gap between a flash cell and a cell is a difference between semiconductor technologies. In the current 0.18um flash technology, this gap is formed to about 100nm, and in 0.13um flash technology, it is formed to about 80nm.

Therefore, if you use the normal mask process, you need to use the advanced scanner (KrF) or higher to form the floating gate of the flash memory. As a way of overcoming this limitation, it is necessary to implement a 90nm pattern while using general DUV equipment, and thus, a desired pattern is formed using a hard mask method using an oxide insulating film as mentioned above.

Using a floating gate mask, the space length between the floating gate and the gate is first formed to be about 0.2 um.

Thereafter, in FIG. 1D, only the first insulating layer 108, which is an LP-TEOS layer used as a hard mask layer, is etched through the oxide insulating layer etching process, for example, a dry etching process, using the prototype resist pattern 110 as a mask. In FIG. 1D, reference numeral 108 ′ represents an insulating film after this etching process.

Next, in FIG. 1E, after removing the photoresist pattern 110, a second insulating film 112 to be used as a second oxide insulating film for a hard mask using an oxide film is deposited. Similarly to the first insulating film 108, the second insulating film 112 at this time uses an LP-TEOS film, and the deposition thickness thereof is, for example, about 750 A.

Subsequently, in FIG. 1F, a blanket etching process slightly larger than the deposition thickness of the second insulating layer 112 deposited without the photoresist pattern is performed. When the blanket etching process is performed, a second deposited second insulating film 112 is formed like a space next to the first insulating film 108 ′ having a pattern formed thereon, and a polysilicon to be used as a lower floating gate ( 106) is revealed. In FIG. 1F, reference numeral 112 ′ represents a second insulating layer having a space formed after the blanket etching process.

Next, in FIG. 1G, the polysilicon 106 exposed in FIG. 1F is etched, for example, the polysilicon 106 is dry etched along the second insulating film 112 ′ spaced by the blanket etching. In FIG. 1G, reference numeral 106 'represents polysilicon after this dry etching process.

At this time, when the etching ratio between the polysilicon and the TEOS oxide film is set to, for example, 2.5: 1, the polysilicon between the floating gates is etched to insulate the floating gates without affecting the polysilicon to be used as the floating gate. Such an insulating gap between the floating gates is a floating gate gap as a final target, and may preferably be insulated at intervals of 100 nm.

Thereafter, the LP-TEOS insulating layers 108 'and 112' remaining on the floating gate may be removed through a subsequent subsequent process, for example, a wet etching process using HF, and the floating gate of the flash cell formed through such processes. The final form of is as illustrated in Figure 1h.

Through the manufacturing process as described above, a semiconductor flash memory having minute cells and cell-to-cell spacings of the flash memory may be implemented.

However, in the conventional semiconductor flash memory manufacturing process, one photo mask process may be applied, but there is a problem that a plurality of etching processes are involved. For example, the LP-TEOS oxide insulating film must be performed twice, three times of insulating film etching (two dry and one wet), and the polysilicon etching is performed once by the dry method. Is accompanied.

In addition, the cleaning process is a complex process that requires great attention, which makes it difficult to build a stable process, requires careful attention, and is very likely to cause an accident.

Accordingly, the present invention is to provide a semiconductor flash memory manufacturing technology that can simplify the process and stably manufacture the floating gate of the flash memory.

According to a preferred embodiment of the present invention, a process of forming an interlayer insulating film after forming a field oxide film on a semiconductor lower layer, and after forming a photoresist pattern for forming a floating gate on the interlayer insulating film, Etching the interlayer insulating layer using a photoresist pattern as a mask, laminating polysilicon for floating gate on the etched interlayer insulating layer, and partially etching the floating gate polysilicon and the interlayer insulating layer Provided is a method of manufacturing a semiconductor flash memory including the step of planarizing a patterned upper surface of a polysilicon layer and an interlayer insulating layer.

According to the present invention, the floating gate semiconductor process of the flash memory is changed by changing the complicated floating gate forming process of the hard mask method using the oxide insulating film which is most widely used in the multilayer gate type flash memory to the process using the floating insulating film mask. Can be simplified. In addition, by effectively forming the floating gate of the flash memory by coating the photoresist and the partial etching method by dry etching method, it is expected to have a significant influence on the development of the next-generation flash memory because the process can be performed stably.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

Prior to the description, the technical gist of the present invention is to form a floating gate first by using an insulating film such as USG (Undoped Silicate Glass), and to laminate the polysilicon for floating gate, and then to coat a photoresist (photo resist) laminating by forming a floating gate by etching a polysilicon outside the region to form the floating gate through blanket etching using a dry etching method, and etching a USG floating insulating film by a wet etching method. By stably manufacturing the floating gate of the flash memory using the gate, it is possible to easily achieve the object of the present invention from this technical idea.

The present invention uses the CMOS semiconductor fabrication technology using the Shallow Trench Isolation (STI) method as it is for the active region and the well region constituting the flash cell.

That is, N-well and P-well are first processed through high energy impurity implantation into the well region after the STI process for distinguishing active regions. After the well impurity implantation is completed, the thermal process is performed by RTP (Rapid Temperature Procedure) for 1095 ° C./20 seconds to form a well.

2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor flash memory according to a preferred embodiment of the present invention.

First, as shown in FIG. 2A, after the field oxide layer 202 is formed on the semiconductor lower layer 200 by using thin silicon etching (STI), which defines an active region for insulating the unit flash cell. Then, the well process for improving the leakage current through the silicon substrate or the performance of the unit transistor is completed.

2B, the interlayer insulating film 204 according to the present embodiment is formed by a high density chemical vapor deposition (HDP) method. As the interlayer insulating film at this time, for example, a USG (Undoped Silicate Glass) film may be used, and the lamination thickness thereof is preferably 1.5 to 1.8 times the lamination thickness of the subsequent polysilicon for floating gate, and more preferably 1,500. It may be laminated to a thickness of kPa to 2,000 kPa.

Next, in FIG. 2C, an insulating film mask process for forming a floating gate is performed. For example, after a photoresist (not shown) is applied on the interlayer insulating layer 204, the field oxide layer 202 is formed with a photoresist pattern 206 for patterning the interlayer insulating layer 204 through an etching process or the like. To correspond to

In FIG. 2D, the interlayer insulating film 204 is etched using the photoresist pattern 206 as a mask. In FIG. 2D, reference numeral 204 'denotes an interlayer insulating film etched by the photoresist pattern 206, and the thickness of the final interlayer insulating film (USG film) 204' is 1,500 kPa to 2,000 kPa, and the width thereof is 300 kPa to 500 kPa. Has

Next, in FIG. 2E, the photoresist pattern 206 is removed and then etched by a wet etching method. At this time, an oxide film of about 80 kV is left on the silicon surface in the entire process. In this embodiment, since the tunnel oxide film must be grown in this region, the semiconductor lower layer 200 is etched to a predetermined depth. At this time, the etching depth is 130 kPa to 140 kPa, for example, wet etching may be applied as an etching method.

Next, the tunnel oxide film 208, which is the most important insulating film that serves as an electron passage of the flash memory, is grown on the semiconductor lower layer 200 to a predetermined thickness, for example, 90 kPa to 110 kPa.

After the tunnel oxide film 208 is grown on the semiconductor lower layer 200, the polysilicon 210 for floating gate is stacked according to the present embodiment. At this time, the polysilicon 210 may be laminated to a thickness of, for example, 900 kPa to 1,100 kPa.

2F, the photoresist (not shown) is coated thinly. The photoresist is used for flattening. When etching is performed by a blanket etching method using a dry etching apparatus without a mask pattern, an already patterned interlayer insulating film (USG film) 204 'and a floating gate are used. The polysilicon 210 is partially etched and planarized. In FIG. 2F, reference numerals 204 ″ and 210 ′ denote the interlayer insulating film (USG film) and the polysilicon 210 after the blanket etching.

Then, the wet etching is performed to remove the photoresist remaining on the polysilicon 210, and finally, a cross section as shown in FIG. 2F is completed.

As described above, in the present invention, in forming a floating gate of a semiconductor flash memory, the floating gate is first formed by using an insulating film such as USG, and the polysilicon for the floating gate is laminated, and then photoresist is formed. By forming a floating gate by coating, etching the polysilicon outside the region where the floating gate is to be formed through a blanket etching in a dry etching manner, and etching a USG floating insulating layer in a wet etching manner. It is implemented to simplify the whole process by reducing the etching process.

Meanwhile, the process subsequent to FIG. 2F is an insulating film for insulation between the floating gate and the control gate, for example, a pure oxide film, an oxide film, a nitride film, and an oxide film (ONO) are sequentially stacked and used as a control gate. When the first polysilicon is stacked and patterned using a mask, a pattern to the control gate of the flash memory is formed. Such subsequent steps are easily understood by those of ordinary skill in the art, and thus detailed descriptions with reference to the drawings will be omitted.

While the embodiments of the present invention have been described in detail, the present invention is not limited to these embodiments, and various modifications may be made by those skilled in the art within the spirit and scope of the present invention described in the claims below. .

1A to 1H are cross-sectional views illustrating a method of manufacturing a conventional semiconductor flash memory;

2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor flash memory in accordance with a preferred embodiment of the present invention.

Claims (5)

Forming an interlayer insulating film after forming a field oxide film on the semiconductor underlayer, Forming an interlayer insulating film having a floating gate shape by forming a photoresist pattern for forming a floating gate on the interlayer insulating film and then etching the interlayer insulating film using the photoresist pattern as a mask; Removing the photoresist pattern and laminating polysilicon for floating gate on the interlayer insulating layer having the floating gate shape; Coating a photoresist on an upper surface of the floating silicon polysilicon; Removing the polysilicon for the floating gate and a part of the interlayer insulating layer having the floating gate form by a blanket etching method Semiconductor flash memory manufacturing method comprising a. The method of claim 1, The interlayer insulating film is a semiconductor flash memory manufacturing method, characterized in that the USG (Undoped Silicate Glass) film formed by high density chemical vapor deposition (HDP). The method of claim 1, The interlayer insulating film is a semiconductor flash memory manufacturing method, characterized in that formed to be 1.5 times to 1.8 times the thickness of the polysilicon for the floating gate. The method of claim 1, The semiconductor flash memory manufacturing method, Removing the photoresist pattern and etching the semiconductor lower layer to a predetermined depth; A process of growing a tunnel oxide layer to a predetermined thickness in a region of the semiconductor lower layer etched to the predetermined depth. The semiconductor flash memory manufacturing method further comprising. delete

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