JP2009152360A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To embed an insulating film in an element isolation region without producing cracks around an element isolating groove. <P>SOLUTION: The element isolating groove 3 is formed in a silicon substrate 2, and a polysilazane film 4b is formed in the element isolating groove 3. Since a level difference is produced on the top face of the polysilazane film 4b in a peripheral circuit region P, a BPSG film 4c is deposited on the polysilazane film 4b. In this case, a melting treatment is applied to the BPSG film 4c to convert the polysilazane film 4b to an element isolating insulating film 4 by heat. The BPSG film 4c is deposited on the polysilazane film 4b to make the BPSG film 4c function as a cap film. In addition, stress can be relieved by reducing the level difference part H2 by a reflow effect by applying melting treatment to the BPSG film 4c, thereby preventing cracks. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device for embedding an insulating film in an element isolation region having an STI (Shallow Trench Isolation) structure.

  In semiconductor devices with fast technological innovation, low power consumption and high speed are constantly being achieved, and the degree of integration has been improved by miniaturization. At present, there are many advantages such as cost reduction and operation speed improvement with miniaturization, but conversely, a phenomenon that has not caused much problems before has become more obvious, and it is necessary to take countermeasures ing.

  As the element isolation width becomes narrower, the aspect ratio of the element isolation region also increases, so that it is becoming difficult to achieve element isolation without generating voids that can cause defects. Therefore, instead of the conventionally used HDP-CVD (High Density Plasma-Chemical Vapor Deposition) method or the like method for forming an element isolation insulating film, a solution having fluidity using a coating technique in the element isolation groove A method of applying a solution and converting the solution into an insulating film has been used (see, for example, Patent Documents 1 and 2).

For example, in the method described in Patent Document 1, a groove is formed on a substrate, a solution containing a perhydrogenated silazane polymer is applied on the substrate, and the solution is heated to form a film containing a perhydrogenated silazane polymer. Then, the film is oxidized in a water vapor atmosphere under reduced pressure, and the film is converted into an insulating film containing silicon and oxygen. However, when a solution containing a perhydrogenated silazane polymer is applied in the groove, a step is likely to occur on the surface after application, particularly in the vicinity of a region where the groove is formed deeply and / or widely. When the coating solution is converted to a silicon oxide film, it is necessary to cause a chemical reaction to desorb the organic solvent. At this time, film shrinkage occurs. When the surface level difference in the vicinity of the groove is large, the coating solution is excessively stressed due to film shrinkage, causing a crack, and the crack reaches the inside of the semiconductor substrate. The technical idea described in Patent Document 3 is disclosed as a technique related to the present invention.
JP 2006-269899 A JP 2004-179614 A JP 2000-77625 A

  An object of the present invention is to provide a method of manufacturing a semiconductor device in which an insulating film can be embedded in an element isolation region without causing cracks around the element isolation groove.

  One embodiment of the present invention includes a step of forming an element isolation groove in a semiconductor substrate, a step of applying a solution containing a perhydrogenated silazane polymer in the element isolation groove, and a heat treatment of the solution to form a polysilazane film. A step of depositing a BPSG (Boron-Phosphorus Silicate Glass) film on the polysilazane film, a step of melt-treating the BPSG film and reflowing, and a step of removing the reflowed BPSG film. Yes.

  Another aspect of the present invention includes a step of forming an element isolation groove in a semiconductor substrate, a step of applying a solution containing a perhydrogenated silazane polymer in the element isolation groove to form a polysilazane film, and the polysilazane film. Heat treating at a first temperature, depositing a BPSG (Boron-Phosphorus Silicate Glass) film on the polysilazane film, and subjecting the BPSG film to a melt treatment at a second temperature higher than the first temperature. A step of reflowing, and a step of removing the reflowed BPSG film.

  Another aspect of the present invention includes a step of forming a first polycrystalline silicon film on a semiconductor substrate on which a gate insulating film is formed, and a step of forming a silicon nitride film on the first polycrystalline silicon film. Sequentially etching the silicon nitride film, the first polycrystalline silicon film, the gate insulating film, and the semiconductor substrate to form an element isolation groove; and a perhydrogenated silazane polymer in the element isolation groove. A step of forming a polysilazane film, a step of heat-treating the polysilazane film at a first temperature, a step of depositing a BPSG (Boron-Phosphorus Silicate Glass) film on the polysilazane film, and the BPSG A step of melt-treating the film at a second temperature higher than the first temperature and reflowing; and a reflow process by CMP (Chemical Mechanical Polish) using the silicon nitride film as a stopper. Removing the formed BPSG film, removing the silicon nitride film and exposing the first polycrystalline silicon film, and forming an interpoly insulating film on the exposed first polycrystalline silicon film And a step of forming a second polycrystalline silicon film on the interpoly insulating film.

  According to the present invention, the insulating film can be embedded in the element isolation region without causing a crack in the vicinity of the groove.

  Hereinafter, an embodiment in which the present invention is applied to a NAND flash memory device will be described with reference to the drawings. In the following description in the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

  FIG. 2A shows a structure in the memory cell region by a schematic plan view, and FIG. 2B shows a structure in the peripheral circuit region by a schematic plan view. 2A and 2B, the NAND flash memory device 1 is partitioned into a memory cell region M and a peripheral circuit region P, and is formed by a guard ring region (not shown). Electrically separated.

  FIG. 1 shows an equivalent circuit in a memory cell region of a NAND flash memory device. A memory cell array Ar is configured in the memory cell region M, and a peripheral circuit PC (see FIG. 2B) for driving the memory cell array Ar is configured in the peripheral circuit region P.

  As shown in FIG. 1, the memory cell array Ar in the memory cell region M of the flash memory device Z includes two (plural) selection gate transistors Trs1 and Trs2, and a plurality of series connected between the selection gate transistors Trs1 and Trs2. A NAND cell unit UC including 32 (for example, 32) memory cell transistors Trm is formed in a matrix. In the NAND cell unit UC, a plurality of memory cell transistors Trm are formed by sharing adjacent source / drain regions (not shown).

  In FIG. 1, the memory cell transistors Trm arranged in the X direction are commonly connected by a word line (control gate line) WL. Further, the select gate transistors Trs1 arranged in the X direction in FIG. 1 are commonly connected by a select gate line SGL1. Similarly, in FIG. 1, the select gate transistors Trs2 arranged in the X direction are commonly connected by a select gate line SGL2.

  A bit line contact CB is connected to the drain region of the select gate transistor Trs1. The bit line contact CB is connected to a bit line BL extending in the Y direction orthogonal to the X direction in FIG. The select gate transistor Trs2 is connected to a source line SL extending in the X direction in FIG. 1 through a source region.

  As shown in FIG. 1, a plurality of NAND cell units UC are arranged side by side in the X direction. The NAND cell units UC arranged in parallel in the X direction constitute one block B1, and the block B1 Are configured in the Y direction. FIG. 1 shows two blocks B1 and B2.

  FIG. 2A schematically shows a plan view in the memory cell region M. FIG. As shown in FIG. 2A, in the memory cell region M, the word line WL is formed along the X direction in FIG. 2A perpendicular to the extending direction of the active region Sa. A gate electrode MG of the memory cell transistor Trm is formed on each active region Sa intersecting with the word line WL. These gate electrodes MG are juxtaposed in the X direction and the Y direction orthogonally intersecting the X direction. The word line WL is formed along the X direction in FIG. 2A, and is formed along the X direction by coupling the gate electrodes MG arranged in parallel in the X direction.

  The selection gate line SGL1 is formed along the X direction in FIG. 2A that intersects perpendicularly with the extending direction of the active region Sa. A selection gate electrode SG of the selection gate transistor is formed on each active region Sa intersecting with the selection gate line SGL1. A pair of selection gate lines SGL1 are formed in the Y direction orthogonal to the X direction, and bit line contacts CB are formed on the plurality of active regions Sa located between the pair of selection gate lines SGL1 to SGL1, respectively. .

  Further, the selection gate line SGL2 is formed along the X direction in FIG. 2A orthogonal to the extending direction of the active region Sa. A selection gate electrode SG of the selection gate transistor is formed on each active region Sa intersecting with the selection gate line SGL2. A pair of selection gate lines SGL2 are formed in the Y direction orthogonal to the X direction, and source line contacts CS are formed on the plurality of active regions Sa positioned between the pair of selection gate lines SGL2 to SGL2, respectively. .

  FIG. 2B schematically shows a plan view of a part in the peripheral circuit region. As shown in FIG. 2B, the peripheral circuit region P is configured by combining a high voltage transistor HVTr and a low voltage transistor LVTr. The peripheral circuit PC is provided for reading, writing, and erasing data stored in the memory cells of the memory cell array Ar in a nonvolatile manner.

  In each of the high breakdown voltage transistor HVTr and the low breakdown voltage transistor LVTr, a plurality of active regions Sa are provided in a rectangular shape on the silicon substrate 2, and STI (Shallow Trench Isolation) is provided so as to cover the outer periphery of each of the active regions Sa. ) Structure element isolation region Sb is formed. The gate electrode HVG of the high breakdown voltage transistor HVTr and the gate electrode LVG of the low breakdown voltage transistor LVTr are respectively positioned above the plurality of active regions Sa and configured to cross the active region Sa.

  A source / drain region 2b is provided in the active region Sa on both sides of the gate electrode HVG of the high breakdown voltage transistor HVTr. On both sides of the gate electrode LVG of the low breakdown voltage transistor LVTr, a source / drain region 2c is provided in the active region Sa.

  FIG. 3A schematically shows a cross section (a cross section in the word line direction of the gate electrode MG of the memory cell transistor) along the line AA in FIG. 2A. FIG. 3B schematically shows a cross section (a cross section in the bit line direction of the memory cell transistor) along the line BB in FIG. 2A. FIG. 3C schematically shows a cross section (cross section of the high voltage transistor HVTr) along the line CC in FIG. 2B. Since the low breakdown voltage transistor LVTr is the same as the high breakdown voltage transistor HVTr except for the thickness of the gate insulating film, the description of its cross section is omitted.

  Hereinafter, the structure of the memory cell transistor Trm in the memory cell region M will be described. In the predetermined region R1 of the memory cell region M, as shown in FIG. 3A, the surface layer of the p-type silicon substrate 2 includes an N well and a P well (both not shown), and the surface layer of the well An element isolation trench 3 is formed in the upper part. These element isolation trenches 3 are configured to isolate a plurality of active regions Sa in the word line direction, and an element isolation insulating film 4 is formed in the element isolation trench 3. The element isolation insulating film 4 is configured such that the upper portion protrudes upward from the surface of the silicon substrate 2. On each of the plurality of active regions Sa of the silicon substrate 2, a gate insulating film 5 is formed of, for example, a silicon oxide film.

  The gate insulating film 5 is configured as a tunnel insulating film with its side surfaces in contact with part of the upper side surface of the element isolation insulating film 4. On these gate insulating films 5, a conductive layer 6 is composed of a semiconductor layer such as polycrystalline silicon doped with an impurity such as phosphorus, and functions as a floating gate electrode FG. The conductive layer 6 is disposed in contact with the uppermost portion of the side surface of the element isolation insulating film 4, and its upper surface protrudes upward from the upper end of the element isolation insulating film 4. The upper side surface of the element isolation insulating film 4 protruding upward from the silicon substrate 2 is formed flush with the side surface of the gate insulating film 5 and the lower side surface of the conductive layer 6. The element isolation insulating film 4 is configured to mainly include a coating type insulating film 4 a in most of the element isolation trench 3.

  The coating type insulating film 4a is made of, for example, a polysilazane spin on glass (SOG) film, and is excellent in fluidity and is more embedded than a TEOS oxide film or the like. The coating type insulating film 4 a is configured such that its upper end is located above the upper surface of the gate insulating film 5.

The inter-gate insulating film (interpoly insulating film) 7 is formed along the upper surface of the element isolation insulating film 4, the upper side surface of the conductive layer 6, and the upper surface of the conductive layer 6. The inter-gate insulating film 7 has a laminated structure of, for example, a silicon oxide film / a high dielectric insulating film / a silicon oxide film. As the high dielectric insulating film, for example, a silicon nitride film or an aluminum oxide (Al ₂ O ₃ ) film having a relative dielectric constant higher than that of the silicon oxide film is used. In the inter-gate insulating film 7, silicon nitride films may be formed by plasma nitriding (radical nitriding) treatment above and below the silicon oxide film / high dielectric insulating film / silicon oxide film.

  A conductive layer 8 is formed on the intergate insulating film 7. The conductive layer 8 is composed of, for example, polycrystalline silicon and a silicide layer made of metal such as tungsten or cobalt formed on the polycrystalline silicon, and functions as the control gate electrode CG and the word line WL. As described above, the gate electrode MG of the memory cell transistor Trm is formed on the silicon substrate 2 with the stacked structure of the conductive layer 6, the intergate insulating film 7, and the conductive layer 8 through the gate insulating film 5.

  As shown in FIG. 3B, the gate electrodes MG of the memory cell transistors Trm are arranged in parallel in the bit line direction, and each gate electrode MG is electrically divided in the dividing region GV. The films 6 to 8 constituting each gate electrode MG have the same side surface. Although not shown, an interlayer insulating film, a barrier film for suppressing unnecessary material permeation, and the like are formed in the dividing region GV. A source / drain region 2a is formed on both sides of the gate electrode MG of the memory cell transistor Trm and located on the surface layer of the silicon substrate 2. The memory cell transistor Trm includes the gate insulating film 5, the gate electrode MG, and the source / drain region 2a.

  On the other hand, as shown in FIG. 3C, a high breakdown voltage transistor HVTr is configured in a predetermined region R2 of the peripheral circuit region P. The high breakdown voltage transistor HVTr includes a gate electrode HVG formed on the silicon substrate 2 via a gate insulating film 15, and source / drain regions 2 b formed on both sides of the gate electrode HVG and on the surface layer of the silicon substrate 2. It is comprised including.

  In the formation region R2 of the high breakdown voltage transistor HVTr, the gate insulating film 15 is formed thicker than the gate insulating film 5 formed in the memory cell region M. A polycrystalline silicon layer 6, an inter-gate insulating film 7, and a conductive layer 8 are sequentially stacked on the gate insulating film 15, thereby forming a gate electrode HVG.

  An opening 7a for conducting the polycrystalline silicon layer 6 and the conductive layer 8 is formed in the inter-gate insulating film 7 of the gate electrode HVG, and the conductive layer 8 is buried in the opening 7a, thereby polycrystalline silicon. The layer 6 and the conductive layer 8 are electrically connected to each other. The side surfaces of the layers 6 to 8 are formed flush with each other.

  An element isolation trench 3 is formed along the peripheral edge of the active region Sa of the silicon substrate 2, and an element isolation insulating film 4 is embedded in the element isolation trench 3. Since the element isolation insulating film 4 is formed of the same material as that of the memory cell region M, the peripheral circuit region P is denoted by the same reference numeral. Note that the gate electrode HVG of the high breakdown voltage transistor HVTr is electrically divided in the dividing region GV, and although not shown, an interlayer insulating film or the like is formed in the dividing region GV.

  In the memory cell region M, high integration of memory cells is required, and a narrow element isolation region Sb is required. On the other hand, in the peripheral circuit region P where the driving transistor HVTr for driving the memory cell is formed, an element isolation region Sb that can withstand a high breakdown voltage is required. That is, the width of the element isolation region Sb in the peripheral circuit region P is wider than the width of the element isolation region Sb in the memory cell region M.

  As described above, in the flash memory device 1 in which the wide and narrow element isolation regions Sb are mixed, when the solution containing the perhydrogenated silazane polymer is applied using the coating technique and oxidized in the water vapor atmosphere, the width is particularly wide. In the vicinity of the boundary between the active element isolation region Sb and the active region Sa, a crack is generated in the film after the oxidation treatment, and the defect that the crack erodes into the silicon substrate 2 occurs. Therefore, in the present embodiment, the following manufacturing method is adopted.

  In the following, a method for manufacturing the memory cell transistor Trm and the high breakdown voltage transistor HVTr in the memory cell region M, which is a characteristic part of the present embodiment, will be mainly described. In addition, you may add suitably the process required in order to manufacture the other area | region which is not shown in figure. The method of manufacturing the low breakdown voltage transistor LVTr is the same as the method of manufacturing the gate insulating film 5 of the memory cell transistor Trm in the memory cell region M except for the thickness of the gate insulating film on the silicon substrate 2. Since this is almost the same as the manufacturing method, the description thereof is omitted.

  As shown in FIG. 4, a sacrificial oxide film 20 is formed on the entire upper surface of the p-type silicon substrate 2, the memory cell region M is covered with a resist mask pattern 21, and the sacrificial oxide film in the formation region R2 of the high breakdown voltage transistor HVTr. 20 is processed by dry etching, and the upper surface of the silicon substrate 2 in the region R2 is dug down. Next, ions are implanted using a photolithography technique and an implantation technique, and heat treatment is performed. The sacrificial oxide film 20 is peeled off before or after ion implantation.

  Next, as shown in FIG. 5, the upper surface of the silicon substrate 2 is thermally oxidized to form a gate insulating film 15 for the high voltage transistor HVTr. Next, as shown in FIG. 6, the region R2 is covered with a mask pattern 22, the thermal oxide film in the regions R1 and M is subjected to isotropic etching, and the gate insulating film 15 is formed in the formation region R2 of the high breakdown voltage transistor HVTr. To remain.

  Next, as shown in FIG. 7, the mask pattern 22 is peeled off, and a thermal oxide film thinner than the gate insulating film 15 formed in the formation region R2 of the high breakdown voltage transistor HVTr is removed from the gate insulating film 5 for the memory cell transistor Trm. Form as.

  Next, as shown in FIG. 8, amorphous silicon doped with impurities such as phosphorus is deposited by LP-CVD. Since this amorphous silicon is transformed into a polycrystalline silicon layer by a subsequent heat treatment, it is denoted by reference numeral 6.

  Next, as shown in FIG. 9, a silicon nitride film 23 is deposited on the upper surface of the polycrystalline silicon layer 6 by LP-CVD, and then a silicon oxide film 24 is deposited by LP-CVD as a hard mask. .

  Next, as shown in FIG. 10, a photoresist (not shown) is applied on the silicon oxide film 24, so that the photoresist remains in a region other than the region for forming the element isolation trench 3. The silicon oxide film 24 is patterned into a shape, and the silicon oxide film 24 is anisotropically etched by RIE (Reactive Ion Etching) using the resist as a mask. Next, the active region Sa and the element isolation region Sb are partitioned by forming the element isolation trench 3 on the respective films 5, 6, 15, 23 and the silicon substrate 2 using the silicon oxide film 24 as a mask. Note that the thickness of the silicon oxide film 24 serving as a hard mask is reduced while the element isolation trench 23 is formed. In this way, the active region Sa in the memory cell region M and the peripheral circuit region P is partitioned.

  Next, as shown in FIG. 11, a solution containing a perhydrogenated silazane polymer is applied to the element isolation groove 3 by the SOG method to fill the element isolation groove 3, and this solution is then baked. A polysilazane film 4b is formed. After the polysilazane film 4b is formed, the active region Sa and the element isolation region Sb are formed in the vicinity of the formation region R2 of the high breakdown voltage transistor HVTr, which is a region where the width of the element isolation trench 3 and the active region Sa are wide. In the region R2a in the vicinity of the boundary, a step H1 occurs between the first upper surface 4ba located above the active region Sa of the polysilazane film 4b and the second upper surface 4bb located above the element isolation region Sb.

  The polysilazane film 4b needs to be subjected to high temperature heat treatment in order to convert it into an oxide film. During this high temperature heat treatment, excessive stress is applied to the step H1 of the polysilazane film 4b, and cracks are generated in the oxide film formed by the high temperature heat treatment in the vicinity of the region R2a. This crack generates an inter-film stress, which may cause deterioration of characteristics of elements (such as a transistor HVTr) formed in the vicinity of the crack.

  Therefore, in the present embodiment, the following process is employed to convert the polysilazane film 4b into an oxide film. First, steam oxidation treatment (WVG: Water Vapor Generator) is performed for a predetermined time (for example, 30 minutes) under a predetermined condition of a first temperature (low temperature of 200 ° C. to 400 ° C., for example, 280 ° C.). This steam oxidation treatment is performed as a film quality stabilization heat treatment of the polysilazane film 4b. In a state where such steam oxidation treatment is performed, the polysilazane film 4b is not a high-quality film, and a silicon-hydrogen (Si—H) bond, a nitrogen-hydrogen (N—H) bond, Silicon-nitrogen (Si-N) bonds and the like remain.

  Next, warm water treatment is performed under predetermined conditions (for example, 65 ° C., 10 minutes to several tens of minutes). By this hot water treatment, unnecessary substances such as carbon and nitrogen in the polysilazane film 4b that may adversely affect the transistor characteristics are removed. Next, the polysilazane film 4b treated with warm water is treated with a hydrogen peroxide solution and a sulfuric acid solution.

  Next, as shown in FIG. 12, a BPSG film 4c is deposited on the upper surface of the polysilazane film 4b with a predetermined film thickness (several tens of nm (for example, 80 nm or more)) by a CVD method. Next, instead of high-temperature heat treatment of the polysilazane film 4b by steam oxidation, the BPSG film 4c is melt-processed at a second temperature (for example, 850 ° C.) higher than the first temperature to be reflowed (softened), and the polysilazane film 4b is subjected to A high temperature heat treatment is applied. At this time, the BPSG film 4c functions as a cap film, and the phenomenon of cracks in the polysilazane film 4b can be suppressed. Further, the step H1 generated in the above-described process can be reduced by exhibiting the deposition process and reflow effect of the BPSG film 4c (see the step H2 in FIG. 12). Through these steps, the polysilazane film 4b is converted into a high-quality silicon oxide film (coating insulating film 4a) as an SOG film.

  Next, as shown in FIG. 13, by using CMP (Chemical Mechanical Polish) method, the BPSG film 4c is removed using the silicon nitride film 23 as a stopper, and the coating type insulating film 4a is planarized, and the coating type in the element isolation trench 3 is formed. The insulating film 4 a is configured as the element isolation insulating film 4.

  Next, as shown in FIG. 14, the element isolation insulating film 4 in the memory cell region M is etched back by dilute hydrofluoric acid (dilute hydrofluoric acid) treatment, and the upper surface 4z of the element isolation insulating film 4 is formed on the silicon substrate 2 and the gate. Adjustment is made so as to be located near the interface with the insulating film 5 (above or below the interface), and then the silicon nitride film 23 is removed by hot phosphoric acid treatment. The process of dropping the upper surface 4z of the element isolation insulating film 4 in the memory cell region M is performed in order to ensure the coupling ratio of the memory cell.

  Next, as shown in FIG. 15, the intergate insulating film 7 is formed by using a CVD method, an ALD (Atomic Layer Deposition) method, a radical nitriding treatment, or the like. Next, polysilicon is thinly deposited by a CVD method (not shown), an opening 7a is formed in the inter-gate insulating film 7 for the high breakdown voltage transistor HVTr, the low breakdown voltage transistor LVTr, and the selection gate transistor Trs. A conductive layer 8 is formed on the intermediate insulating film 7 for the control gate electrode CG.

  Next, as shown in FIGS. 3B and 3C, the conductive layer 8, the intergate insulating film 7, and the polycrystalline silicon layer 6 are subjected to a cutting process in the cutting region GV by an anisotropic etching process. Note that the upper silicidation step of the silicon metal constituting the conductive layer 8 may be performed either before or after the dividing region GV is formed depending on the metal material to be applied. Through these steps, the gate electrodes HVG and MG of the transistors HVTr and Trm can be processed and formed.

  Next, ion implantation processing for forming source / drain regions 2a and 2b of HVTr and Trm of each transistor is performed, and spacers, contact regions, interlayer insulating films, bit line contacts CB, and source line contacts (not shown) are performed. The flash memory device 1 can be configured by forming wiring layers such as CS and the upper bit line BL.

  According to the present embodiment, as a filling technique using the element isolation insulating film 4 in the element isolation trench 3, a polysilazane film 4b is formed after applying a solution containing a buried perhydrogenated silazane polymer, and this polysilazane film 4b is formed. Since the BPSG film 4c is deposited thereon, an effect as a cap material can be obtained. Moreover, since the BPSG film 4c is melt-processed, the step portion can be reduced by reflowing, the stress can be relaxed, and cracks can be prevented. Further, the amount of the polysilazane film 4b applied in the element isolation trench 3 can be reduced by depositing the BPSG film 4c.

(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.
Although the p-type silicon substrate 2 is applied, a silicon substrate in which a p-well is formed on the n-type silicon substrate 2 may be applied, or other types of semiconductor substrates may be applied.
By applying a BPSG film 4c as a cap film of the polysilazane film 4b and depositing the BPSG film 4c and reflowing the BPSG film 4c, a process of depositing a d-TEOS (plasma TEOS) film is provided. You may make it reduce a level | step difference.

The element isolation insulating film 4 is composed of a polysilazane film 4b and an HTO (High Temperature Oxide) film, an LTO (Low Temperature Oxide) film, an HDP (High Density Plasma) film, etc. formed by chemical vapor deposition (CVD). You may be comprised by the laminated structure.
Although applied to a NAND flash memory device, it may be applied to a NOR flash memory device as long as it is a semiconductor device in which wide and narrow element isolation regions Sb are mixed, or a DRAM (Dynamic-RAM), You may apply to PSRAM (Pseudo-SRAM) etc.
As the inter-gate insulating film 7, a laminated structure in which an oxide film and / or a nitride film is sandwiched between upper and lower layers of a high dielectric insulating film such as alumina (Al ₂ O ₃ ) is applied, but an ONO film (silicon oxide film-silicon nitride) (Film-silicon oxide film) or the like may be applied.

The figure which shows a part of electrical structure of the memory cell area | region of the flash memory device which shows one Embodiment of this invention typically A plan view schematically showing a part of a memory cell region A plan view schematically showing the transistor structure in the peripheral circuit region Sectional drawing typically shown along line AA in FIG. 2A Sectional drawing typically shown along line BB in FIG. 2A Sectional drawing typically shown along line CC in FIG. 2B Sectional drawing which shows one manufacturing process typically (the 1) Sectional drawing which shows one manufacturing process typically (the 2) Sectional drawing which shows one manufacturing process typically (the 3) Sectional drawing which shows one manufacturing process typically (the 4) Sectional drawing which shows one manufacturing process typically (the 5) Sectional drawing which shows one manufacturing process typically (the 6) Sectional drawing which shows one manufacturing process typically (the 7) Sectional drawing which shows one manufacturing process typically (the 8) Sectional drawing which shows one manufacturing process typically (the 9) Sectional drawing which shows one manufacturing process typically (the 10) Sectional drawing which shows one manufacturing process typically (the 11) Sectional drawing which shows one manufacturing process typically (the 12)

Explanation of symbols

  In the drawing, 3 is an element isolation trench, 4b is a polysilazane film, and 4c is a BPSG film (cap film).

Claims (5)

Forming an element isolation groove in a semiconductor substrate;
Applying a solution containing a perhydrogenated silazane polymer in the element isolation groove;
Heat-treating the solution to form a polysilazane film;
Depositing a BPSG (Boron-Phosphorus Silicate Glass) film on the polysilazane film;
Melting and reflowing the BPSG film;
And a step of removing the reflowed BPSG film. Forming an element isolation groove in a semiconductor substrate;
Applying a solution containing a perhydrogenated silazane polymer in the element isolation trench to form a polysilazane film;
Heat-treating the polysilazane film at a first temperature;
Depositing a BPSG (Boron-Phosphorus Silicate Glass) film on the polysilazane film;
Melting and reflowing the BPSG film at a second temperature higher than the first temperature;
And a step of removing the reflowed BPSG film. Forming a first polycrystalline silicon film on the semiconductor substrate on which the gate insulating film is formed;
Forming a silicon nitride film on the first polycrystalline silicon film;
Etching the silicon nitride film, the first polycrystalline silicon film, the gate insulating film, and the semiconductor substrate sequentially to form an element isolation trench;
Applying a solution containing a perhydrogenated silazane polymer in the element isolation trench to form a polysilazane film;
Heat treating the polysilazane film at a first temperature;
Depositing a BPSG (Boron-Phosphorus Silicate Glass) film on the polysilazane film;
Melting and reflowing the BPSG film at a second temperature higher than the first temperature;
Removing the BPSG film reflowed by CMP (Chemical Mechanical Polish) using the silicon nitride film as a stopper;
Removing the silicon nitride film and exposing the first polycrystalline silicon film;
Forming an interpoly insulating film on the exposed first polycrystalline silicon film;
And a step of forming a second polycrystalline silicon film on the interpoly insulating film.   Between the step of heat-treating the polysilazane film at a first temperature and the step of depositing a BPSG film on the polysilazane film, the step of warm-treating the polysilazane film; 4. A method of manufacturing a semiconductor device according to claim 2, further comprising a step of treating with water and a sulfuric acid solution.   5. The method of manufacturing a semiconductor device according to claim 2, wherein the step of heat-treating the polysilazane film at a first temperature includes a steam oxidation treatment step.

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