JP2002110828A - Semiconductor device having desirable gate profile and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method for a nonvolatile memory device or other semiconductor device where a control gate consisting of conductive material is formed equally. SOLUTION: A silicon layer is made on a buffer oxide film in the shape of a semiconductor substrate. After formation of the buffer oxide film, a check film is made. A control gate consisting of conductive material such as the control gate of an EEPROM memory device is provided on the silicon layer, a gate oxide film, and a substrate. Next, the top of the substrate is etched to form a trench. The sidewall of a trench is oxidized to produce bird's beaks equally at the top and bottom of the control gate substance. Next, a field oxide film is made to stop the trench.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a control gate such as a floating gate of a memory device and a method of manufacturing the same. More specifically, the present invention provides a self-aligned shallow trench isolation for simultaneously forming a gate and an active region.
Low Trench Isolation) technology.

[0002]

2. Description of the Related Art In the manufacture of a memory device, the degree of integration of a cell is mainly determined by the layout of a cell array and its own physical dimensions. Below the half-micron design rule, a photolithographic resolution at which proportional scalability can be achieved during the manufacturing process
(resolution) and the alignment error of the mask used in the process. Alignment errors are limited by the mechanical techniques used to form the mask and the technique of printing the mask between layers. It is desirable to use fewer masks because multi-stage manufacturing alignment errors accumulate. Fewer masks minimizes the possibility of misalignment. Therefore, "self-alignment (self-align
ed) "Process steps have been developed.

A device isolation structure between individual cells in a memory cell array, for example, a field oxide film consumes a chip area useful for active circuit elements. Therefore, it is desirable to minimize the size of the device isolation structure in order to increase the integration of the memory cells and the active circuits in the substrate. However, the size of the element isolation structure is limited by its manufacturing process and alignment.

[0004] Typically, device isolation structures are grown in various regions of the chip by a thermal field oxidation process such as a LOCal Oxidation of Silicon (LOCOS). According to the LOCOS method, after a pad oxide film and a nitride film are sequentially formed, the nitride film is patterned. Next, the silicon substrate is selectively oxidized using the patterned nitride film as a mask to form a field oxide film region. However, according to the LOCOS device isolation, the growth of the oxide film on the side surface of the pad oxide film is eroded below the nitride film provided as a mask during the selective oxidation of the silicon substrate, and a bird's beak is formed at the end of the field oxide film.
(bird's beak). Due to the bird's beak, the field oxide film is extended to the active region of the memory cell to reduce the width of the active region, thereby deteriorating the electrical characteristics of the memory device.

For such reasons, a shallow trench isolation (hereinafter, referred to as "STI") structure has attracted attention in ultra-highly integrated semiconductor devices. In the STI process, first, a silicon substrate is etched to form a trench, and then an oxide film is deposited to fill the trench. Next, the oxide film is etched back (etch back) or chemical mechanical polishing (chemical mechani
The field oxide film is formed inside the trench by etching using cal polishing (CMP) method.

The above-mentioned LOCOS and STI methods commonly include a mask step for defining an element isolation region on a substrate and a step of forming a field oxide film in this region. After forming the isolation structure, a mask step for forming a memory cell is performed. Therefore, the alignment error due to the formation of the isolation structure and the alignment error due to the layout of the memory cells accumulate to induce a misalignment that causes a failure of the device.

As one method for solving such an alignment problem, there has been proposed a method of forming a LOCOS element isolation structure by self-alignment with a floating gate when forming a floating gate of a nonvolatile memory device. Also, a method of forming an STI structure by self-alignment with a floating gate is disclosed in US Pat.
No. 13,551, and the like. According to this method, since the floating gate and the active region are simultaneously defined and manufactured using one mask,
No alignment errors are accumulated.

[0008] Non-volatile memory devices have an almost unlimited storage capacity, but recently there has been an increasing demand for flash memories capable of electrically inputting and outputting data together with EEPROMs. The memory cells of these devices generally have a vertically stacked gate structure with a floating gate formed on top of a silicon substrate. Multi-layer gate structures typically include one or more tunnel oxide or dielectric films and a control gate formed on or around the floating gate. In the flash memory cell having this structure, data is stored by applying an appropriate voltage to the control gate and the substrate and taking in and extracting electrons from the floating gate. At this time,
The dielectric film functions to maintain a potential on the floating gate.

The self-aligned STI process has the advantage that a floating gate and an active region can be formed simultaneously, but the aspect ratio of the gap (aspec
gap ratio by increasing the
filling) when cracks (seam) or voids (voi)
The disadvantage is that d) is more likely to be generated. Also, when a high density plasma (hereinafter referred to as "HDP") oxide film having an excellent ability to fill the gap is used, the edge portion of the polishing end layer under the HDP oxide film is eroded when the HDP oxide film is deposited.
n) and the field oxide region has a negative slope (negat
ive slope). As a result, a gate residue is generated under the inclined portion of the field region during a subsequent gate etching process.

[0010] However, the above-mentioned problems have been sufficiently solved by optimizing the deposition conditions of the HDP oxide film to improve the gap filling capability, or by using a method of removing the negative inclination of the field region using a wet etching solution. Can be solved.

FIGS. 1A-1E illustrate a self-aligned ST.
FIG. 9 is a perspective view illustrating a method of manufacturing a conventional flash memory device according to the I technology. Referring to FIG. 1A, after a gate oxide film (ie, a tunnel oxide film) 11 is formed on a silicon substrate 10, a first oxide film is formed on the gate oxide film 11.
A polysilicon layer 13 and a nitride film 15 are sequentially deposited.

Referring to FIG. 1B, the nitride film 15, the first polysilicon layer 13 and the gate oxide film 11 are patterned by photolithography to form a nitride film pattern 16, a first floating gate 14 and a gate oxide film pattern 12. I do. Next, the exposed portion of the substrate 10 is etched to a predetermined depth to form the trench 18. That is, an active region and a floating gate are simultaneously defined during a trench forming process using one mask.

Referring to FIG. 1C, an exposed portion of the trench 18 is exposed to an oxidizing atmosphere to cure a silicon damage caused by high energy ion bombardment during a trench etching process. Heat treatment. Then, an oxidation reaction between the exposed silicon and the oxidizing agent forms a trench oxide film 20 on the inner surface including the base surface and the side wall.

During the oxidation step, an oxidizing agent is applied to the side of the gate oxide film pattern 12 below the first floating gate 14.
(oxidant) penetrates to form bird's beaks at both ends of the gate oxide film pattern 12. Due to the bird's beak, both edges of the gate oxide film pattern 12 are expanded and the base edge of the first floating gate 14 is bent outward, so that the lower part of the sidewall of the first floating gate 14 has a positive slope. . Here, the fact that the side wall has a positive slope means that the side wall has a slope that is eroded by the etchant. That is, as shown in the drawing, the invasion of the oxidizing agent is suppressed directly below the nitride film pattern 16 due to the presence of the nitride film pattern 16, and the upper portion of the sidewall of the first floating gate 14 has a negative slope.
On the other hand, since the bottom edge of the lower portion of the first floating gate 14 is bent outward and has a positive inclination, it is eroded by an etchant introduced in the upper direction of the substrate, such as a sidewall of a mesa structure, or is exposed to the etchant. On the other hand, it acts as a blocking film for the underlying layer.

Referring to FIG. 1D, a chemical vapor deposition is performed to fill the trench 18.
n: Hereinafter, referred to as “CVD”), an oxide film (not shown) is formed, and then CVD-CVD is performed until the upper surface of the nitride film 16 is exposed.
The oxide film is removed by a CMP process. As a result, a field oxide film 22 including the trench oxide film 18 is formed inside the trench 18.

Next, after the nitride film pattern 16 is removed in a phosphoric acid strip process, the first floating gate 14 is removed.
In order to form a second floating gate on the field oxide layer 22, the same material as the first polysilicon layer 13 is deposited to form a second polysilicon layer (not shown). The second polysilicon layer on the field oxide film 22 is partially removed by photolithography to form a second floating gate 24 separated from an adjacent cell. The second floating gate 24 is in electrical contact with the first floating gate 14 to increase an area of an interlayer dielectric formed in a subsequent process.

Next, an ONO interlayer dielectric film 2 is formed on the entire surface of the resulting product.
6 and the control gate layer 28 are sequentially formed. The control gate layer 28 has a polycide structure in which a doped polysilicon layer and a tungsten silicide layer are stacked.

Referring to FIG. 1E, after patterning the control gate layer 28 by photolithography, the exposed interlayer dielectric film 26 and the second and first layers are continuously exposed.
The floating gates 24 and 14 are anisotropically dry-etched to complete a nonvolatile memory device.

At this time, the lower portion of the side wall of the first floating gate 14 has a positive slope as seen from the portion indicated by the dotted line A in FIG. 1D. Therefore, the base edge portion of the first floating gate 14 masked by the field oxide film 22 remains without being etched due to the anisotropic etching characteristic of the dry etching process (that is, the characteristic that the etching proceeds only in the vertical direction). Become like As a result, a line-shaped polysilicon residue 14a is formed along the surface boundary between the field oxide film 22 and the active region. The polysilicon residue 14a forms an electrical bridge between adjacent floating gates and causes electrical failure of the device.
(fail) will be triggered.

[0020]

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to realize a good profile without a positive slope of a sidewall of a gate or other conductive structure such as a floating gate structure in a flash memory device. It is an object of the present invention to provide a method of manufacturing a non-volatile memory device or other device that can be used.

[0021]

According to the present invention, there is provided a self-alignment method for manufacturing a semiconductor device including a floating gate and an active region associated therewith, and a corresponding semiconductor device. I do. The floating gate and the active region are formed in a region of the substrate of the semiconductor memory device at least partially defined by a field oxide region formed in the trench. The trench is formed with the formation of at least a first segment of the floating gate. The method includes, before forming the trench, uniformly forming an oxide film on a sidewall of the first segment of the floating gate, forming a buffer layer on the first segment of the gate, and Removing the buffer membrane. According to the method, the sidewalls of the first segment can be oxidized more evenly before stacking at least another segment of a different conductive material on the first segment of the floating gate.

According to another embodiment, a gate oxide film is formed on a semiconductor substrate, and a first oxide film is formed on the gate oxide film.
Forming a buffer layer on the first conductive layer after forming the conductive layer;
(Eg, an oxide film) is formed. Next, a blocking layer is formed on the buffer layer, and the blocking layer and the buffer layer are patterned to form a blocking layer pattern and a buffer layer pattern. The first conductive layer and the gate oxide layer are patterned to form a floating gate layer and a gate oxide layer pattern of the first conductive layer pattern, and an upper portion of the substrate is etched to form a trench. An inner surface of the trench is oxidized to form a trench oxide film on the inner surface of the trench, and a bird's beak is formed on the upper and lower portions of the floating gate layer to form a positive profile on a sidewall of the patterned floating gate layer. To prevent that. Next, a field oxide film for filling the trench is formed.

Further, the object of the present invention is to form a gate oxide film on a semiconductor substrate, to form a first conductive layer on the gate oxide film, and to form an oxide film on the first conductive layer. Forming such a buffer film, forming a blocking film on the buffer oxide film, and using a single mask to form the blocking film, the buffer oxide film, the first conductive layer, the gate oxide film, and the substrate. A floating gate is formed from the first conductive layer by patterning, and at the same time, a trench is formed in the substrate adjacent to the floating gate and aligned with the floating gate to define an active region of the substrate. Oxidizing the inner surface of the trench to form a trench oxide film on the inner surface of the trench, And forming a bird's beak underneath to prevent the formation of a positive profile on the side wall of the patterned floating gate layer, and forming a field oxide film filling the trench. be able to.

According to another embodiment of the present invention, a buffer layer provided as an oxide mask layer is formed between the floating gate layer and the nitride layer, and the buffer layer is formed above and below the floating gate layer when a sidewall of a subsequent trench is oxidized. Generates bird's beak. Then, the bird's beak prevents the sidewall of the floating gate layer from having a positive slope, and prevents a gate residue during subsequent gate etching from causing electrical failure of the device.

The above objects and other features and advantages of the present invention will become apparent from the following description of preferred embodiments of the present invention with reference to the following.

[0026]

Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Embodiment 1 FIGS. 2A to 2I are perspective views illustrating a method of manufacturing a nonvolatile memory device according to a first embodiment of the present invention.

Referring to FIG. 2A, a silicon oxide film or a silicon oxynitride film is grown on a semiconductor substrate 100 made of a material such as silicon to form a gate oxide film (eg, a silicon oxide film) of a cell transistor.
A tunnel oxide film) 101 is formed. Semiconductor substrate 100
Above, when exposed to the atmosphere, it reacts with oxygen in the atmosphere to form a natural oxide film. Therefore, although not shown, a natural oxide film is also formed on the semiconductor substrate 100 according to the present embodiment. In this embodiment, the thickness is about 10 to 500 mm except for such a natural oxide film, preferably about 75 mm for a low-voltage semiconductor element, and about 300 mm for a high-voltage semiconductor element. The gate oxide film 101 is grown thin.

A first silicon layer 103 used as a floating gate is formed on the gate oxide film 101 by a low pressure chemical vapor deposition (LPCVD) method to a thickness of about 200 to 1500 、, preferably 500 Å. Doping method such as POCl ₃ diffusion, ion implantation, or in-
high concentration of the first silicon layer 103 by in situ doping.
Doping with N-type impurities. Preferably, the first silicon layer 103 is made of polysilicon or amorphous silicon. At this time, the first silicon layer 103 is exposed to the atmosphere and has a native oxide of about 30 to 35.
It is formed with a thickness of Å.

The buffer film 1 is formed on the first silicon layer 103.
05 is formed to a thickness of about 10 to 500 ° (excluding the thickness of the native oxide film) which is approximately the same thickness as the gate oxide film 102. The buffer film 105 may be formed by thermal oxidation or plasma-enhanced chemical vapor deposition.
It can be an oxide film formed by cal vapor deposition (PE-CVD). Further, the buffer film 105 is made of oxygen (O
₂ ) Alternatively, the first silicon layer 103 may be formed by partially oxidizing the surface of the first silicon layer 103 by plasma treatment with an oxidizing gas such as a nitrous oxide (N ₂ O) gas. In addition, any buffer material other than the oxide film may be used to prevent the gate from being formed irregularly at the time of forming the trench or to planarize the edge or the side wall of the first or other segment of the gate. As described above, if a buffer material is not used before the trench is oxidized, the floating gate may be deformed or have an undesirable positive slope.

An etch stopping layer 107 is deposited on the buffer oxide layer 105 by LPCVD to a thickness of about 100 to 3000 、, preferably 1500 Å. The blocking layer 107 functions as a polishing termination layer during a subsequent CMP process or an etch back process. The blocking layer 107 covers the buffer oxide layer 105 during the subsequent thermal oxidation process of the trench and also serves to prevent oxygen and oxidant from entering the first silicon layer 103 through the buffer oxide layer 105. Therefore, the blocking film 107 is made of a material having oxidation resistance, for example, Si.
It is desirable to use a nitride such as N, SiON or BN.

The blocking film 107 is formed by using polysilicon.
Can also be formed. In this case, the blocking film 107 is partially oxidized during a subsequent oxidation process, but can be used as an end-point detecting layer during an etch-back process or a CMP process.

Optionally, an anti-reflection film is formed on the blocking film 107 by a CVD method in order to smoothly perform subsequent photolithography. Such an anti-reflective coating is made of polysilicon, silicon oxide such as high temperature oxide (High Temperature Oxide) or medium temperature oxide (Medium Temperature Oxide), or silicon oxynitride (SiON).
It can be formed using such as. The antireflection film can be formed of a single layer or a plurality of layers.

In this embodiment, a high temperature oxide layer (hereinafter referred to as "HTO") is used as an antireflection film.
A double layer composed of 140 and the SiON film 150 is formed. The HTO film 140 and the SiON film 150 can be easily formed by a known CVD method, and these serve as an anti-reflection film for preventing light from being reflected from a lower substrate during photolithography, and a photoresist. Facilitates pattern formation. The HTO film 140 is 200 to 20
00Å, preferably 500Å, and the Si
The ON film 150 is formed to have a thickness of 200 to 3000 、, preferably 800 Å.

Referring to FIG. 2B, a photoresist is coated on the SiON film 150 by spin coating to form a photoresist film (not shown). Next, a photoresist pattern 160 defining the layout of the floating gate is formed by exposing and developing the photoresist film using a photomask.

Using the photoresist pattern 160 as an etching mask, the SiON film 160 and the HTO film 15 are formed.
0, the blocking film 107 and the buffer oxide film 105 are sequentially etched to form the SiON film pattern 16 as shown in FIG.
1. A pattern structure including the HTO film pattern 151, the blocking film pattern 108, and the buffer oxide film pattern 106 is formed. Next, the photoresist pattern 160 is removed through an essing and stripping process.

Referring to FIG. 2C, the resultant is transferred to another etching chamber to perform a polysilicon and oxide etching process. Here, an etching gas for etching polysilicon and oxide is introduced to etch the first silicon layer 103 to form a first silicon layer pattern 104. At this time, the first silicon layer pattern 104 is used as a first floating gate of the nonvolatile memory device.

Next, the gate oxide film 101 is etched in the same etching chamber to form a gate oxide film pattern 1.
Then, the substrate 100 is etched to a depth of about 1000 to 5000 °, preferably 2700 ° to form the trench 109. As a result, the floating gates defined by the first silicon layer pattern 104 are separated from each other by the trench 109.

In the process of etching the first silicon layer pattern 104 and the upper portion of the semiconductor substrate 100, the SiON film pattern 15 formed on the blocking film pattern 108 is etched.
1 and the HTO film pattern 141 are removed.

By forming the trench 109, an active region and a floating gate are simultaneously defined using one mask. Thus, the floating gate is self-aligned with the active area.

Referring to FIG. 2D, the inner surface of the trench 109 is treated in an oxidizing atmosphere to remove silicon damage caused by high-energy ion bombardment during the trench etching process and to prevent generation of leakage current. I do. Then, a trench oxide film 110 is formed to a thickness of about 10 to 500 、, preferably 30 to 40 て along the inner surface of the trench 109, that is, along the bottom surface and the side walls. The trench oxide film 110 is formed of nitrogen (N
It can be formed by a dry oxidation method in a mixed atmosphere of ₂ ) and oxygen (O ₂ ), or can be formed by a wet oxidation method at a temperature of 700 ° C. or more.

As widely known, an oxide film forming reaction is represented by the following equation. Si + O ₂ → SiO ₂ Si + 2H ₂ O → SiO ₂ + 2H _{2 As} can be seen from the above formula, the oxidizing agent is diffused as a layer having a silicon (Si) source and oxidation of silicon proceeds, so that An oxide film is grown on the surface of the one silicon layer pattern 104 and the surface of the silicon substrate 100.

FIG. 3 is an enlarged sectional view of a portion B in FIG. 2D. When the trench oxide layer 110 is formed, as shown in FIG. 3, an oxidant (or an oxidizing gas) enters a side surface of the gate oxide layer pattern 102 below the first silicon layer pattern 104 to form a first bird's beak (a). ) Occurs. At the same time, an oxidant penetrates into the side surface of the buffer oxide film pattern 106 below the blocking film pattern 108, and a second bird's beak (b) also occurs above the first polysilicon layer pattern 104.

According to the conventional method shown in FIG. 1C, a bird's beak occurs only below a silicon pattern used as a floating gate. During the oxidation, the oxide film grown at the base edge of the floating gate expands and the lower part of the gate sidewall has a positive slope. On the contrary, in the present invention, since the first bird's beak (a) and the second bird's beak (b) are simultaneously formed on the lower and upper portions of the gate sidewall, a phenomenon occurs in which the base edge portion of the gate sidewall is bent outward. Absent. That is,
The second layer formed on the first silicon layer pattern 104
The bird's beak (b) prevents a positive tilt. Therefore, according to the present invention, the floating gate formed of the first silicon layer pattern 104 has a desirable profile.

Referring to FIG. 2E, an oxide film 112 having an excellent gap filling property, such as USG, O ₃ -TEOS USG, or HDP oxide, is deposited to a thickness of about 5000 CVD by a CVD method so as to fill the trench 109. I do. Preferably,
HD using SiH ₄ , O ₂ and Ar gas as plasma source
A P oxide film 112 is formed.

At this time, the trench 109 is buried by filling the gap of the HDP oxide film 112 to improve the capability so that cracks and voids are not generated inside the trench 109.

Since the HDP oxide film 112 has the property that deposition and sputter etching proceed simultaneously, the HDP oxide film 112 is deposited at a constant speed in a wide area, but is deposited after being deposited to a constant thickness in a narrow area. The rate and sputter etch rate are the same, and no more oxide film is deposited.
When the sputter etching capability is increased to improve the characteristics of the HDP oxide film 112 after the gap is filled, the edge portion of the blocking film pattern 106 including nitride is eroded, and the field oxide film has a negative slope. In order to prevent such a problem, a method of changing a deposition condition or removing a negative tilt of the field oxide film using a wet etchant when forming the blocking film 105 can be used.

Next, Si (OC ₂ H ₅ ) _{4 is formed} on the HDP oxide film 112.
A capping oxide film (not shown) made of PE-TEOS can be deposited by a plasma method using as a source.

If necessary, the HDP oxide film 112 is densified to reduce a wet etching rate for a subsequent cleaning process by about 800 to 1050.
Annealing is performed at a high temperature of ℃ and an inert gas atmosphere.

Referring to FIG. 2F, the blocking film pattern 10 is formed.
Etchback or CM until the top surface of 8 is exposed
The P method is performed to planarize the HDP oxide film 112. Accordingly, the HDP oxide film 112 on the blocking film is partially removed to form a field oxide film 124 in the trench 109.

Referring to FIG. 2G, the blocking film pattern 108 made of silicon nitride in the phosphoric acid stripping process is used.
Is removed. At this time, the buffer oxide film pattern 106
Prevents the first silicon layer pattern 104 of the first floating gate made of silicon under the silicon nitride removal process by the phosphoric acid strip from being damaged.

Next, a step of pre-cleaning the substrate for about 30 seconds with an etching solution containing hydrofluoric acid (pre-cleanin
g) is performed. The strip of the blocking film pattern 108 and the field oxide film 124 are formed by the pre-cleaning process.
Is partially removed, and the first silicon layer pattern 104 is removed.
The buffer oxide film pattern 106 formed thereon is also removed. At this time, the field oxide film 124 is about 250 °
The above thickness is removed.

Referring to FIG. 2H, a second silicon layer such as polysilicon or amorphous silicon is formed on the exposed first silicon layer pattern 104 and the field oxide layer 124.
(Not shown) is deposited to a thickness of about 2000 mm or more by the LPCVD method. The second silicon layer is formed to be in electrical contact with the first silicon layer pattern 104 of the first floating gate. Next, the second floating gate 126 is doped with a high concentration of N-type impurities by a usual doping method, for example, POCl ₃ diffusion, ion implantation, or in-situ doping to form a second conductive layer.

Also, without performing another doping step,
The second conductive layer may be formed by performing a CVD method while implanting an impurity during the formation of the second silicon layer and depositing polysilicon doped with the impurity. The second floating gate formed by the second conductive layer is formed to increase the area of an interlayer dielectric film formed in a subsequent process, and is preferably formed as thick as possible.

Next, the second conductive layer on the field oxide film 124 is partially removed by ordinary photolithography to form a second silicon layer pattern 126 constituting a second floating gate. Then, the second floating gate thus formed is separated from the floating gates and the like of the adjacent cells.

Next, an interlayer dielectric 128 made of ONO is formed on the entire surface of the resultant structure so as to completely insulate the second silicon pattern 126 of the second floating gate. For example, after oxidizing the second floating gate 126 to grow a first oxide film having a thickness of about 100 mm, a nitride film having a thickness of about 130 mm is deposited thereon, and a first oxide film having a thickness of about 40 mm is deposited on the nitride film. An interlayer dielectric film 1 having an equivalent oxide thickness of about 100 to 200 °
28 are formed.

Next, a polysilicon layer doped with N ⁺ type and tungsten silicide are formed on the interlayer dielectric film 128.
A control gate layer 130 of a third conductive layer formed by stacking a metal silicide layer such as (WSix), titanium silicide (TiSix), cobalt silicide (CoSix), and tantalum silicide (TaSix) is formed. Preferably, the polysilicon layer of the control gate layer 130 is formed to a thickness of about 1000 degrees, and the metal silicide layer is formed to a thickness of about 100 to 1500 degrees.

Referring to FIG. 2I, after patterning the control gate layer 130 by photolithography,
The exposed interlayer dielectric 128, the second floating gate segment 126, and the first floating gate segment 104 are sequentially patterned for each cell by dry etching to form a stick type floating gate of a memory cell. At this time, the dry etching is performed until the upper surface of the substrate 100 between the field oxide layers 124 is exposed.

Since the side wall of the first silicon layer pattern 104, which is the first floating gate, does not have a positive slope, the side wall portion of the first silicon layer pattern 104 is not deformed and does not have an outwardly bent portion. . Therefore, the portion exposed by the mask pattern of the first silicon layer pattern 104 is completely removed during the above-described dry etching process, so that the field oxide film 124
No silicon residue is formed at the surface boundary between the active region and the active region.

Next, although not shown, after forming the source / drain regions of the memory cell in the ion implantation process, an interlayer insulating film (ILD) is applied on the resultant. After the interlayer insulating film is etched to form a contact hole exposing the source / drain region, a contact plug for filling the contact hole is formed. Next, a metallization layer (metallization l) that is in electrical contact with the contact plug
a), and performs a back-end process using an interlayer dielectric (IMD), a via, and a metal mask.

Embodiment 2 The processes illustrated in FIGS. 2B and 2C of Embodiment 1 are performed in separate etching chambers.
However, according to the second embodiment of the present invention, the above process is continuously performed in one etching chamber. Embodiment 2 is the same as Embodiment 1 except that the anti-reflection film is not formed and the substrate is etched in one etching chamber using a photoresist as an etching mask. Here, reference numerals as in the first embodiment indicate the same members.

FIGS. 4A and 4B are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to a second embodiment of the present invention. Referring to FIG. 4A, a gate oxide film 101, a first silicon layer 103, a buffer oxide film 105, and a blocking film 107 are sequentially formed on a substrate 100 as in the first embodiment.

Referring to FIG. 4B, using a photomask for defining a floating gate, a photoresist pattern 160 is formed on the blocking layer 107 as in the first embodiment, and then the photoresist pattern is formed. 160 as an etching mask
7, the buffer oxide film 105, the first silicon layer 103, and the gate oxide film 101 are patterned to form a blocking film pattern 108, a buffer oxide film pattern 106, a first silicon layer pattern 104, and a gate oxide film pattern 102.
To form a patterned structure.

Subsequently, the trenches 109 are formed by etching the substrate 100, and then the photoresist pattern 160 is removed by performing an etching or stripping process.

Thereafter, the floating gate of the nonvolatile memory device according to the second embodiment of the present invention is provided by performing the processes shown in FIGS. 2C to 2I of the first embodiment.

[0065]

As described above, according to the present invention, a bird's beak is generated above the floating gate by additionally forming a buffer oxide film between the first segment of the floating gate layer and the blocking film. . When the sidewall of the subsequent trench is oxidized, the first
Bird beaks created at the top and bottom of the segment flatten the sidewalls of the floating gate. Then
As a result, it is possible to prevent the sidewall of the floating gate layer from having an undesired inclination, thereby implementing a nonvolatile memory device having a gate having a desired profile.

Further, since no silicon residue is formed during the subsequent dry etching for forming the gate, it is possible to prevent adjacent gates from being short-circuited to each other due to the silicon residue and causing electrical failure of the device.

It is clear that the present invention can be applied to the case where another conductive layer is formed in a semiconductor device which requires uniformity as well as the uniform formation of the floating gate. That is, the present invention can be applied anywhere where the suppression of the bird's beak phenomenon described above is required.

Although the present invention has been described in detail with reference to the embodiments, the present invention is not limited to the embodiments, and any person having ordinary knowledge in the technical field to which the present invention belongs can apply the idea and spirit of the present invention. The invention could be modified or changed without departing.

[Brief description of the drawings]

1A is a perspective view illustrating a method of manufacturing a flash memory device having a self-aligned shallow trench element isolation according to a conventional method, and FIG. 1B is a perspective view illustrating a method having a self-aligned shallow trench element isolation according to a conventional method. FIG. 4 is a perspective view for explaining a method for manufacturing a flash memory device,
C is a perspective view for explaining a method of manufacturing a flash memory device having a self-aligned shallow trench isolation according to a conventional method, and D is a method of manufacturing a flash memory device having a self-aligned shallow trench isolation according to a conventional method. FIG. 7E is a perspective view illustrating a method, and FIG. 7E is a perspective view illustrating a method of manufacturing a flash memory device having a self-aligned shallow trench isolation according to a conventional method.

2A is a perspective view illustrating a method of manufacturing a floating gate of a nonvolatile memory device according to a first embodiment of the present invention, and FIG. 2B is a perspective view illustrating a floating gate of the nonvolatile memory device according to the first embodiment of the present invention; FIGS. 4A and 4B are perspective views for explaining a manufacturing method, C is a perspective view for explaining a floating gate manufacturing method of the nonvolatile memory device according to the first embodiment of the present invention, and D is a first embodiment of the present invention.
FIG. 7 is a perspective view for explaining a method of manufacturing a floating gate of the nonvolatile memory device according to the embodiment, and E is a perspective view for explaining the method of manufacturing the floating gate of the nonvolatile memory device according to the first embodiment of the present invention. ,
F is a perspective view for explaining a method of manufacturing the floating gate of the nonvolatile memory device according to the first embodiment of the present invention, and G is a method for manufacturing the floating gate of the nonvolatile memory device according to the first embodiment of the present invention. FIG. 1H is a perspective view illustrating a method of manufacturing a floating gate of a nonvolatile memory device according to a first embodiment of the present invention, and I is a perspective view illustrating a nonvolatile memory device according to a first embodiment of the present invention. It is a perspective view for explaining the floating gate manufacturing method of an apparatus.

FIG. 3 is an enlarged sectional view of a portion B in FIG. 2D.

FIG. 4A is a perspective view illustrating a method of manufacturing a floating gate of a memory device according to a second embodiment of the present invention, and FIG. 4B is a diagram illustrating a method of manufacturing a floating gate of a memory device according to a second embodiment of the present invention. FIG.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 semiconductor substrate 101 gate oxide film 102 gate oxide pattern 103 first silicon layer 104 first silicon layer pattern 105 buffer oxide film 106 buffer oxide film pattern 107 blocking film 108 blocking film pattern 109 trench 110 trench oxide film 112 CVD-oxide film 124 Field oxide film 126 Second silicon layer pattern 128 Interlayer dielectric film 130 Control gate 140 HTO film 141 HTO film pattern 150 SiON film 151 SiON film pattern 160 Photoresist pattern

[Procedure amendment]

[Submission date] October 12, 2001 (2001.10.
12)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

32. A semiconductor substrate; a gate oxide film formed on the substrate; forming a first conductive layer on the gate oxide film; forming a buffer film on the first conductive layer; Forming a blocking layer on the buffer layer, patterning the blocking layer and the buffer layer to form a blocking layer pattern and a buffer layer pattern, and patterning the first conductive layer to form a first segment of the floating gate. Forming a gate oxide pattern and a trench by etching the upper portion of the gate oxide film and the substrate; and oxidizing an inner surface of the trench to form a trench oxide film on the inner surface of the trench. A bird's beak is formed above and below the first segment of the floating gate to form a trench oxide film. A first conductive layer formed by flattening a side wall of the first segment of the floating gate during formation; a field oxide film formed in the trench while oxidizing an inner surface of the trench; And a second segment of the floating gate formed to planarize the field oxide film until the first segment is exposed and to make electrical contact with the first segment. A self-aligned floating gate and associated active area of a semiconductor memory device.

33. The first of said floating gate
33. The self-aligned floating gate and associated active region according to claim 32 , wherein the segments are made of polysilicon or amorphous silicon.

34. The self-aligned floating gate according to claim 32 , wherein the buffer layer is an oxide layer formed by thermal oxidation.

35. The buffer film according to claim 35, wherein the buffer film is formed by plasma-excited chemical vapor deposition.
32. The self-aligned floating gate and active region associated therewith according to 32 .

36. The buffer layer is a floating, which is self-aligned according to claim 32, characterized by being formed an oxidizing gas to the plasma processing to oxidize the surface of the first segment of the floating gate Gate and its associated active area.

37. The claim 36 wherein the oxidizing gas is characterized by the use of oxygen (O _2), nitrous oxide (N ₂ O) gas
5. The self-aligned floating gate and active region associated therewith according to claim 1.

38. The self-aligned floating gate according to claim 32 , wherein the buffer layer is formed to a thickness of 10 to 500 degrees.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F001 AA01 AA25 AA30 AA31 AA43 AA63 AB08 AD12 AD60 AG02 AG07 AG10 AG28 5F083 EP05 EP23 EP55 EP56 JA04 JA05 JA35 JA39 JA53 MA06 MA19 NA01 PR03 PR05 PR06 PR12 PR21 PR29 PR33 PR39 PR40 5F101 BA BA07 BA12 BA13 BA29 BA36 BB05 BD02 BD35 BH03 BH13 BH14 BH19

Claims (45)

[Claims] 1. A conductive layer and an active region corresponding to the conductive layer are manufactured in a region defined at least in part by a field oxide film region formed in a trench of the substrate in a substrate of a semiconductor device. A self-alignment method for forming at least a first segment of a control gate on a dielectric material, comprising: forming a buffer layer on the first segment of the control gate before forming the trench; and removing the buffer layer. A step of oxidizing a side wall of the first segment even more before stacking at least one other segment on the first segment of the control gate. 2. The method of claim 1, wherein the first segment includes at least one of polysilicon and amorphous silicon. 3. The method according to claim 1, wherein the buffer film is an oxide film formed by thermal oxidation. 4. The method according to claim 1, wherein the buffer film is formed by plasma-enhanced chemical vapor deposition. 5. The method of claim 1, wherein the buffer film is formed by performing a plasma treatment on an oxidizing gas to oxidize a surface of the first segment of the control gate. 6. The method according to claim 5, wherein the oxidizing gas uses oxygen (O ₂ ) or nitrous oxide (N ₂ O) gas. 7. The method according to claim 1, wherein the buffer film is formed to a thickness of 10 to 500 degrees. 8. A self-alignment method for forming a floating gate and an associated active area on a substrate of a semiconductor device, comprising: forming a gate oxide film on a semiconductor substrate; and forming a first conductive layer on the gate oxide film. Forming a buffer oxide film on the first conductive layer; forming a blocking film on the buffer oxide film; patterning the blocking film and the buffer oxide film to form a blocking film pattern And forming a buffer oxide film pattern, patterning the first conductive layer to form a floating gate as a first conductive layer pattern, and etching the gate oxide film and an upper portion of the substrate to form a gate oxide film. Forming a pattern and a trench; oxidizing an inner surface of the trench to form a trench on the inner surface of the trench; Forming a passivation film, forming bird's beaks on the upper and lower portions of the floating gate layer to prevent the formation of a positive profile on sidewalls of the patterned floating gate layer, and forming a field oxide film for filling the trench. A method of self-aligning, comprising forming. 9. The method according to claim 8, wherein the first conductive layer includes at least one of polysilicon and amorphous silicon. 10. The method of claim 8, wherein said blocking film includes a nitride component. 11. The method according to claim 8, wherein the buffer oxide film is formed by a thermal oxidation method. 12. The method according to claim 1, wherein the buffer oxide film is plasma-
9. The method according to claim 8, wherein the method is formed by excited chemical vapor deposition. 13. The method of claim 8, wherein the buffer oxide film is formed by oxidizing a surface of the first conductive layer by performing a plasma treatment on an oxidizing gas. 14. The method according to claim 1, wherein the oxidizing gas uses oxygen (O ₂ ) or nitrous oxide (N ₂ O) gas.
3. The method according to 3. 15. The method according to claim 15, wherein the buffer oxide film has a thickness of 30 to 50.
9. The method of claim 8, wherein said method is formed with a thickness of 0 °. 16. The field oxide film forms an oxide film covering the blocking film while filling up the trench, and chemically mechanically polishes the oxide film until the surface of the blocking film pattern is exposed. The method according to claim 8, wherein the etching is performed to have a flat surface by a method or an etch-back method. 17. The method of claim 8, further comprising forming an anti-reflection film on the blocking film by a chemical vapor deposition method. 18. The method of claim 17, wherein the anti-reflection film is made of at least one material selected from the group consisting of polysilicon, silicon nitride, silicon oxynitride, and silicon oxide. 19. After forming a photoresist pattern for forming a floating gate on the anti-reflection film, using the photoresist pattern as an etching mask in a first etching chamber, forming an anti-reflection film, a blocking film, and the like. After the photoresist pattern is removed by patterning a buffer oxide film, the first conductive layer pattern, the gate oxide film pattern and the trench are formed while removing the antireflection film pattern in a second etching chamber. The method according to claim 17, wherein 20. After a photoresist pattern for forming a floating gate is formed on the blocking layer, the photoresist pattern is used as an etching mask to continuously perform an etching process in one etching chamber. Patterning a blocking layer, a buffer oxide layer, a first conductive layer and a gate oxide layer, and etching an upper portion of the substrate to form the blocking layer pattern, the first conductive layer pattern, the gate oxide layer pattern and the trench; The method of claim 17, wherein: 21. A step of forming a gate oxide film on a semiconductor substrate, forming a first conductive layer on the gate oxide film, forming a buffer film on the first conductive layer, Forming a blocking layer on the buffer layer; patterning the blocking layer, the buffer layer, the first conductive layer, the gate oxide layer and the substrate using a single mask to form a floating gate from the first conductive layer. Forming a trench aligned with the floating gate in the substrate adjacent to the floating gate to define an active region in the substrate; and oxidizing an inner surface of the trench to form the trench. Forming a trench oxide film on the inner surface and forming bird's beaks on the upper and lower portions of the floating gate layer to form the patterned oxide film; Phase and, and a manufacturing method of a floating gate structure of the nonvolatile memory device having a step of forming a field oxide film filling up the trenches to prevent the formation of positive profile of the sidewalls of the floating gate layer. 22. The method according to claim 21, wherein the first conductive layer includes at least one of polysilicon and amorphous silicon. 23. The method according to claim 21, wherein the blocking film includes a nitride component. 24. The method according to claim 21, wherein the buffer film is formed of an oxide film formed by thermal oxidation. 25. The buffer film according to claim 2, wherein the buffer film is formed by plasma-excited chemical vapor deposition.
2. The method for manufacturing a memory device according to item 1. 26. The buffer film according to claim 26, wherein the surface of the first conductive layer is plasma-treated with an oxidizing gas to oxidize the surface of the first conductive layer. 22. The method for manufacturing a memory device according to 21. 27. The oxidizing gas according to claim 26, wherein oxygen (O ₂ ) or nitrous oxide (N ₂ O) gas is used.
6. The method for manufacturing a memory device according to claim 1. 28. The method according to claim 28, wherein the buffer film has a thickness of 30 to 500 °.
22. The method according to claim 21, wherein the memory device is formed with a thickness. 29. After the step of forming the field oxide film, flattening the field oxide film with the surface of the blocking film, removing the patterned blocking film, and forming an interlayer dielectric on the floating gate. 22. The method of claim 21, further comprising sequentially forming a film and a control gate. 30. The method as claimed in claim 21, further comprising forming an anti-reflection film on the blocking film by a chemical vapor deposition method. 31. The method according to claim 30, wherein the anti-reflection film is made of at least one material selected from the group consisting of polysilicon, silicon oxynitride, and silicon oxide. . 32. A floating gate semiconductor memory device comprising a substrate, an insulating layer and a floating gate on the insulating layer, wherein the floating gate is formed in a trench of the substrate together with the formation of the floating gate. A buffer film is formed on the first segment of the floating gate before forming the trench, and at least a second segment of the floating gate is formed after forming the first segment. Removing the buffer film so as to oxidize the upper and lower portions of the first segment side wall more evenly before stacking the second segment on the first segment of the floating gate. Gugeto semiconductor memory device. 33. The first gate of the floating gate.
33. The floating gate semiconductor memory device according to claim 32, wherein the segments are made of polysilicon or amorphous silicon. 34. The floating gate semiconductor memory device according to claim 32, wherein the buffer film is an oxide film formed by thermal oxidation. 35. The floating gate semiconductor memory device of claim 32, wherein the buffer film is formed by plasma-enhanced chemical vapor deposition. 36. The floating gate semiconductor memory device according to claim 32, wherein the buffer film is formed by oxidizing a surface of the first segment of the floating gate by performing a plasma treatment on an oxidizing gas. . 37. The oxidizing gas according to claim 36, wherein oxygen (O ₂ ) or nitrous oxide (N ₂ O) gas is used.
3. The floating gate semiconductor memory device according to claim 1. 38. The buffer film according to claim 17, wherein
33. The floating gate semiconductor memory device according to claim 32, wherein the floating gate semiconductor memory device is formed with a thickness. 39. A semiconductor substrate; a gate oxide film formed on the substrate; forming a first conductive layer on the gate oxide film; forming a buffer film on the first conductive layer; Forming a blocking layer on the buffer layer, patterning the blocking layer and the buffer layer to form a blocking layer pattern and a buffer layer pattern, and patterning the first conductive layer to form a first segment of the floating gate. Forming a gate oxide pattern and a trench by etching the upper portion of the gate oxide film and the substrate; and oxidizing an inner surface of the trench to form a trench oxide film on the inner surface of the trench. A bird's beak is formed above and below the first segment of the floating gate to form a trench oxide film. A first conductive layer formed by flattening a side wall of the first segment of the floating gate during forming; a field oxide film formed in the trench while oxidizing an inner surface of the trench; And a second segment of the floating gate formed to planarize the field oxide film until the first segment is exposed and to make electrical contact with the first segment. A self-aligned floating gate and associated active area of a semiconductor memory device. 40. The first of the floating gates
40. The self-aligned floating gate and associated active region according to claim 39, wherein the segments are made of polysilicon or amorphous silicon. 41. The self-aligned floating gate according to claim 39, wherein the buffer layer is an oxide layer formed by thermal oxidation. 42. The self-aligned floating gate and its associated active region according to claim 39, wherein the buffer layer is formed by plasma-enhanced chemical vapor deposition. 43. The self-aligned floating floating gate according to claim 39, wherein the buffer layer is formed by oxidizing a surface of the first segment of the floating gate by performing a plasma process on an oxidizing gas. Gate and its associated active area. 44. The method of claim 43, wherein the oxidizing gas uses oxygen (O ₂ ) or nitrous oxide (N ₂ O) gas.
5. The self-aligned floating gate and active region associated therewith according to claim 1. 45. The self-aligned floating gate according to claim 39, wherein the buffer layer is formed to a thickness of 10Å500 °.