JP2004172567A - Manufacturing method of semiconductor element - Google Patents

Manufacturing method of semiconductor element Download PDF

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Publication number
JP2004172567A
JP2004172567A JP2003208569A JP2003208569A JP2004172567A JP 2004172567 A JP2004172567 A JP 2004172567A JP 2003208569 A JP2003208569 A JP 2003208569A JP 2003208569 A JP2003208569 A JP 2003208569A JP 2004172567 A JP2004172567 A JP 2004172567A
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Japan
Prior art keywords
film
oxide film
polysilicon
polysilicon film
layer
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JP2003208569A
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JP4886163B2 (en
Inventor
Senju Kin
占 壽 金
Jung Ryul Ahn
正 烈 安
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SK Hynix Inc
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Hynix Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor element which can form a floating gate without using a mask process and form a floating gate of a small size. <P>SOLUTION: The method comprises a step for forming a tunnel oxide film, a first polysilicon film and a pad nitride film one by one on a semiconductor substrate, a step for forming a trench in the semiconductor substrate by partially etching the pad nitride film, the first polysilicon film, the tunnel oxide film and the semiconductor substrate in the patterning process, a step for flattening the oxide film to expose the pad nitride film after deposition of the oxide film on the whole structure including the trench, a step for forming an oxide film projecting part by etching the pad nitride film, a step for flattening a second polysilicon film to expose the oxide film projecting part after deposition of the second polysilicon film on the whole structure and a step for forming a dielectric film and a control gate after forming a floating gate by etching a part of the exposed oxide projecting part. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体素子の製造方法に係り、特に、自己整列方法でフローティングゲートを形成するフラッシュ素子のフローティングゲート形成方法に関する。
【０００２】
【従来の技術】
最近、デザインルール及び素子サイズが減少することにより、ＥＴＯＸ（ＥＥＰＲＯＭ Ｔｕｎｎｅｌ Ｏｘｉｄｅ）セルにおいてフローティングゲート間の間隔及びカップリングに最も大きい影響を及ぼすフィールド酸化膜（Ｆｉｅｌｄ Ｏｘｉｄｅ； ＦＯＸ）オーバーラップの調節に困っている。一般にＳＴＩ工程を用いてフラッシュメモリーセルを実現しているが、フローティングゲートのアイソレーションを行う際にマスクを用いたパターニング工程の作業は、マスク臨界寸法（Ｃｒｉｔｉｃａｌ Ｄｉｍｅｎｓｉｏｎ； ＣＤ）の変化によるウェーハの均一化が容易でないため、素子間のカップリング比が均一ではないという問題点が生じる。また、フラッシュメモリー素子のプログラム及び消去の際に高いバイアス電圧を印加すると、不均一なフローティングゲートによってフラッシュメモリー素子の欠陥が発生する。アイソレーションマスクとポリマスクとの間に整列誤差及びマスク工程の増加は、歩留りの低下とコストアップの原因になっている。
【０００３】
【発明が解決しようとする課題】
そこで本発明は、かかる従来の問題点を解決するためのもので、その目的は、フローティングゲートを形成するためのトンネル酸化膜及び第１ポリシリコン膜膜を蒸着した状態でパターニング工程を行ってＳＴＩ構造の素子分離膜を形成し、第１ポリシリコン膜膜上に第２ポリシリコン膜膜を蒸着してフローティングゲートを形成することにより、マスク工程を使用することなく、フローティングゲートを形成することができ、小さなサイズのフローティングゲートを形成することができる半導体素子の製造方法を提供することにある。
【０００４】
【課題を解決するための手段】
上記目的を達成するために、本発明は、半導体基板上にトンネル酸化膜、第１ポリシリコン膜及びパッド窒化膜を順次形成する段階と、前記パターニング工程によって前記パッド窒化膜、前記第１ポリシリコン膜、前記トンネル酸化膜及び前記半導体基板の一部をエッチングして前記半導体基板内にトレンチを形成する段階と、前記トレンチを含む全体構造上に酸化膜を蒸着した後、前記パッド窒化膜が露出するように前記酸化膜を平坦化する段階と、前記パッド窒化膜をエッチングして酸化膜凸部を形成する段階と、全体構造上に第２ポリシリコン膜を蒸着した後、前記酸化膜凸部が露出するように前記第２ポリシリコン膜を平坦化する段階と、前記露出した酸化膜凸部の一部をエッチングしてフローティングゲートを形成した後、誘電体膜及びコントロールゲートを形成する段階とを含んでなることを特徴とする。
【０００５】
【発明の実施の形態】
以下、添付図を参照して本発明の実施例をさらに詳しく説明する。ところが、本発明は、下記の実施例に限定されるものではなく、様々な変形実現が可能である。これらの実施例は本発明の開示を完全にし、当技術分野で通常の知識を有する者に本発明の範疇を知らせるために提供されるものである。一方、図面上において、同一の符号は同一の要素を示す。
【０００６】
図１〜図４は本発明に係る半導体素子の製造方法を説明するための断面図である。
【０００７】
図１（ａ）を参照すると、半導体基板１０上に、基板表面の結晶欠陥抑制または表面処理及びイオン注入の際にバッファー層の役割をするスクリーン酸化膜（図示せず）を蒸着した後イオン注入を行ってウェルを形成する。前記スクリーン酸化膜を除去した後、トンネル酸化膜１２、第１ポリシリコン膜１４及びパッド窒化膜１６を蒸着する。
【０００８】
具体的に、前記スクリーン酸化膜の形成の前に、半導体基板１０の洗浄のために、５０：１のＨ２ＯとＨＦとの混合比率を有するＤＨＦ（Ｄｉｌｕｔｅ ＨＦ）、ＮＨ４ＯＨ、Ｈ２Ｏ２及びＨ２ＯからなるＳＣ−１（Ｓｔａｎｄａｒｄ Ｃｌｅａｎｉｎｇ−１）とを用いて、或いは１００：１〜３００：１のＮＨ４ＦとＨＦとの混合比率を有するＢＯＥ（Ｂｕｆｆｅｒｅｄ Ｏｘｉｄｅ Ｅｔｃｈ）とＮＨ４ＯＨ、Ｈ２Ｏ２及びＨ２ＯからなるＳＣ−１とを用いて前処理洗浄工程を行う。７５０〜８００℃の温度範囲内でドライまたはウェット酸化を行って厚さ３０〜１００Åの前記スクリーン酸化膜を形成する。イオン注入の後、５０：１のＨ２ＯとＨＦとの混合比率を有するＤＨＦ、ＮＨ４ＯＨ、Ｈ２Ｏ２及びＨ２ＯからなるＳＣ−１とを用いて前記スクリーン酸化膜をエッチングする。トンネル酸化膜１２を７５０〜８００℃の温度でウェット酸化方式によって８５〜１１０Åの厚さに形成し、トンネル酸化膜１２の蒸着後９００〜９１０℃の温度でＮ２を用いて２０〜３０分間熱処理工程を行うことにより、トンネル酸化膜１２と半導体基板１０間の界面の欠陥密度を最小化する。トンネル酸化膜１２上に、５３０〜６８０℃の温度と０．１〜３．０ｔｏｒｒの圧力下でＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）、ＬＰＣＶＤ（Ｌｏｗ Ｐｒｅｓｓｕｒｅ ＣＶＤ）、ＰＥＣＶＤ（Ｐｌａｓｍａ Ｅｎｈａｎｃｅｄ ＣＶＤ）又はＡＰＣＶＤ（Ａｔｍｏｓｐｈｅｒｉｃ Ｐｒｅｓｓｕｒｅ ＣＶＤ）法で、ＳｉＨ４またはＳｉ２Ｈ６とＰＨ３ガスを用いて厚さ２００〜１０００Åの第１ポリシリコン膜１４を蒸着する。かくして、第１ポリシリコン膜１４の粒度が最小化されることにより、電界集中を防止することができる。第１ポリシリコン膜１４上にＬＰ−ＣＶＤ法で厚さ約１３００〜３０００Åのパッド窒化膜１６を形成する。
【０００９】
図１（ｂ）を参照すると、パッド窒化膜１６、第１ポリシリコン膜１４、トンネル酸化膜１２及び半導体基板１０をＩＳＯマスクパターニング（Ｉｓｏｌａｔｉｏｎ ｍａｓｋ ｐａｔｔｅｒｎｉｎｇ）によって順次エッチングしてＳＴＩ（Ｓｈａｌｌｏｗ Ｔｒｅｎｃｈ Ｉｓｏｌａｔｉｏｎ）構造のトレンチ１８を形成することで活性領域とフィールド領域を定義する。ＳＴＩ構造のトレンチ１８側壁のエッチングダメージを補償するためのドライ酸化工程を行い、急速熱処理工程（Ｒａｐｉｄ Ｔｈｅｒｍａｌ Ｐｒｏｃｅｓｓ）を行ってトレンチ１８のコーナー部分をラウンディングする。全体構造上に高温酸化膜（Ｈｉｇｈ Ｔｅｍｐｅｒａｔｕｒｅ Ｏｘｉｄｅ； ＨＴＯ）を薄く蒸着して高温で緻密化工程を行い、ライナー酸化膜（図示せず）を形成する。
【００１０】
具体的に、全体構造上に感光膜を塗布した後、感光膜マスクを用いたフォトリソグラフィ工程を行って感光膜パターン（図示せず）を形成する。前記感光膜パターンをエッチングマスクとするエッチング工程を行ってパッド窒化膜１６、第１ポリシリコン膜１４、トンネル酸化膜１２及び半導体基板１０をエッチングしてＳＴＩ構造のトレンチ１８を形成する。前記エッチング工程によるトレンチ１８側壁のダメージを補償するために８００〜１０００℃の温度範囲内でドライ酸化工程を行って側壁酸化膜を５０〜１５０Åの厚さに形成する。水素を用いた急速熱処理工程を行って（すなわち、半導体基板の原子移動性質を利用）トレンチコーナー部分と角が立った部分をラウンディングすることにより、電場集中を抑制して素子の動作特性を向上させる。急速熱処理工程は、高速熱処理（Ｆａｓｔ Ｔｈｅｒｍａｌ Ｐｒｏｃｅｓｓ； ＦＴＰ）型装備で６００〜１０５０℃の温度範囲と３００〜３８０ｔｏｒｒの圧力下で１００〜２０００ｓｃｃｍの水素ガスを流入して５〜１５分間行う。
【００１１】
後続工程の酸化膜とトレンチ１８との接着特性を向上させるとともにモウト（Ｍｏａｔ）の発生を防止するために、ＤＣＳ（Ｄｉｃｈｌｏｒｏ Ｓｉｌａｎｅ； ＳｉＨ２Ｃｌ２）ガスを用いて形成されたＨＴＯを５０〜１５０Åの厚さに蒸着した後、１０００〜１１００℃の温度でＮ２を用いて２０〜３０分間高温緻密化工程を行い、ライナー酸化膜（図示せず）を形成する。高温緻密化工程によりライナー酸化膜の組職が緻密になってエッチング抵抗性を増加させ、ＳＴＩの実現の際にモウト形成を抑制し、しかも漏洩電流を防止する役割を果たす。
【００１２】
図２（ａ）を参照すると、全体構造上に高密度プラズマ（Ｈｉｇｈ Ｄｅｎｓｉｔｙ Ｐｌａｓｍａ； ＨＤＰ）酸化膜２０を蒸着してトレンチ１８の内部を埋め込む。パッド窒化膜１６を停止層とする平坦化工程を行う。パッド窒化膜１６をエッチング停止層として、パッド窒化膜１６上のＨＤＰ酸化膜２０及びライナー酸化膜を除去するための平坦化工程を行う。
【００１３】
具体的に、トレンチ１８の空白を満たすために厚さ５０００〜１００００Åの範囲でＨＤＰ（Ｈｉｇｈ Ｄｅｎｓｉｔｙ Ｐｌａｓｍａ）酸化膜２０を形成する。この際、トレンチ１８内部に空間が形成されないように前記ＨＤＰ酸化膜２０を蒸着する。ＣＭＰを用いた平坦化工程を行った後、パッド窒化膜１６上に残存する可能性のある酸化膜を除去するために、ＢＯＥまたはＨＦを用いたポスト洗浄工程を行う。この際、オーバーエッチングに起因する前記ＨＤＰ酸化膜２０の高さの減少を最大限抑制する必要がある。
【００１４】
図２（ｂ）を参照すると、パッド窒化膜１６をリン酸ディップアウト（Ｈ３ＰＯ４ ｄｉｐ ｏｕｔ）を用いた窒化膜ストリップ工程を行うことにより、ＨＤＰ酸化膜凸部２２を形成する。パッド窒化膜１６のストリップの際、ＨＤＰ酸化膜凸部２２は第１ポリシリコン膜１４から７００〜２５００Åの高さにとなるようにする。この際、第１ポリシリコン膜１４とフィールド酸化膜の段差は、後続工程で形成される第２ポリシリコン膜の厚さ程度に２００〜３００Å程度の小さい厚さを持つように残す。
【００１５】
図３（ａ）を参照すると、前処理洗浄工程を行った後、全体構造上に第２ポリシリコン膜２４を蒸着する。平坦化工程を行ってＨＤＰ酸化膜凸部２２上に形成された第２ポリシリコン膜２４を除去することにより、フローティングゲート電極２６を形成する。具体的に、ＤＨＦとＳＣ−１を用いた前処理ウェット洗浄工程を行い、フィールド酸化膜とポリシリコン膜とのオーバーラップを形成する。この時、ウェット洗浄時間を調節してセル地域のモウト形状及び第１ポリシリコン膜１４下部のトンネル酸化膜１２の損失を防止する。また、ウェット洗浄工程によって第１ポリシリコン膜１４の厚さの２／３程度（１００〜７００Å）が開放されるように、ウェット洗浄工程を制御する。第１ポリシリコン膜１４と同一の材質の第２ポリシリコン膜２４を８００〜２５００Åの厚さに蒸着してＨＤＰ酸化膜凸部２２を埋め込む。ＰＥ−ＣＶＤ法を用いて、ＰＥ−ＴＥＯＳ（Ｐｌａｓｍａ Ｅｎｈａｎｓｅｄ Ｔｅｔｒａ Ｅｔｈｙｌｅ Ｏｒｔｈｏ Ｓｉｌｉｃａｔｅ）、ＰＥ−Ｎｉｔ、ＰＳＧ（Ｐｈｏｓｐｈｏｒｕｓ Ｓｉｌｉｃａｔｅ Ｇｌａｓｓ）及びＢＰＳＧ（Ｂｏｒｏｎ Ｐｈｏｓｐｈｏｒｕｓ Ｓｉｌｉｃａｔｅ Ｇｌａｓｓ）のようなバッファー層（図示せず）を形成し、ＣＭＰを用いた平坦化工程で発生するおそれのあるバラツキを防止する。前記バッファー層は１００〜１０００Åの厚さに蒸着する。
【００１６】
化学的機械的研磨によってＨＤＰ酸化膜凸部２２上のバッファー層と第２ポリシリコン膜２４を除去して第２ポリシリコン膜２４を孤立させることにより、第１及び第２ポリシリコン膜１４、２４からなるフローティングゲート電極２６を形成する。また、化学的機械的研磨によってフローティングゲート電極（第１及び第２ポリシリコン膜の全厚）を厚さ１０００〜２５００Åの範囲で均一に残留させる。
【００１７】
図３（ｂ）を参照すると、ＣＭＰ工程後の前処理洗浄工程でＨＦまたはＢＯＥを用いて、露出したＨＤＰ酸化膜凸部２２を厚さ５００〜２０００Åだけ除去する。これにより、既存のマスキング方式によって実現する時より小さなフローティングゲート電極２６の幅と表面積を形成してカップリング比を大きくすることができる。
【００１８】
図４を参照すると、誘電体膜２８を全体構造の段差に沿って形成した後、コントロールゲートを形成するための第３ポリシリコン膜３０とタングステンシリサイド（ＷＳｉ）膜３２を順次蒸着する。具体的に、半導体素子に使われる多様な形態の誘電体膜を蒸着するが、本実施例ではＯＮＯ（酸化膜／窒化膜／酸化膜（ＳｉＯ２−Ｓｉ３Ｎ４−ＳｉＯ２）またはＯＮＯＮ構造の誘電体膜２８を蒸着する。ＯＮＯ構造の誘電体膜２８において、ＯＮＯ構造における酸化膜は、耐圧及びＴＤＤＢ特性に優れたＤＣＳ（ＳｉＨ２Ｃｌ２）とＮ２Ｏガスを用いて０．１〜３ｔｏｒｒの低圧と８１０〜８５０℃程度の温度下で約３５〜６０Åの厚さにＬＰ−ＣＶＤ法によって蒸着する。
【００１９】
また、ＯＮＯ構造における窒化膜は、ＤＣＳとＮＨ３ガスを用いて１〜３ｔｏｒｒの低圧と６５０〜８００℃程度の温度下で約５０〜６５Åの厚さにＬＰ−ＣＶＤ法によって蒸着する。前記ＯＮＯ工程を行った後、ＯＮＯ酸化膜の質を向上させるとともに各階間のインタフェースを強化させるために、ウェット酸化方式で約７５０〜８００℃の温度でモニタリングウェーハを基準として約１５０〜３００Åの厚さに酸化するようにスチームアニールを行うことができる。ひいては、前記ＯＮＯ工程と前記スチームアニールを行う際、各工程間の遅延時間が数時間以内の工程を行って自然酸化膜または不純物による汚染を防止する。
【００２０】
第３ポリシリコン膜３０は、タングステンシリサイド膜３２を蒸着する際に誘電体膜２８に置換固溶されて酸化膜の膜厚を増加させることが可能なフッ酸の拡散を防止するために、ドープされた膜とドープされていない膜（ｄｏｐｅｄ ａｎｄ ｕｎｄｏｐｅｄ）の２重膜構造で、約５１０〜５５０℃の温度と１．０〜３ｔｏｒｒの圧力下でＬＰ−ＣＶＤ法によってアモルファスシリコン膜で蒸着する。この時、ドープされた膜とドープされていない膜との比率を１：２〜６：１とし、フローティングゲート電極２６同士の間の空間が十分埋め込まれるように約５００〜１０００Åの厚さに前記非晶質シリコン膜を形成することにより、後続のタングステンシリサイド膜３２の蒸着時に隙間形成を抑制してワードライン抵抗Ｒｓを減少させることができる。前記２重構造の第３ポリシリコン膜層を形成する際、ＳｉＨ４またはＳｉ２Ｈ６とＰＨ３ガスを用いて、ドープされた膜を形成し、その後ＰＨ３ガスを遮断して、連続的にドープされていない膜を形成することが望ましい。
【００２１】
タングステンシリサイド膜３２は、低いフッ素含有率と低いポストアニールドストレス（ｐｏｓｔ ａｎｎｅａｌｅｄ ｓｔｒｅｓｓ）並びに良好な接着強度を有するＭＳ（ＳｉＨ４）またはＤＣＳ（ＳｉＨ２Ｃｌ２）とＷＦ６との反応を用いて、３００〜５００℃の温度で適切なステップカバレッジ（ｓｔｅｐ ｃｏｖｅｒａｇｅ）を実現し、ワードライン抵抗Ｒｓを最小化することが可能な化学量論比である２．０〜２．８程度に成長させた方が良い。タングステンシリサイド膜３２上にＳｉＯｘＮｙまたはＳｉ３Ｎ４を用いてＡＲＣ層（図示せず）を蒸着し、ゲートマスクとエッチング（Ｇａｔｅ ｍａｓｋ ａｎｄ ｅｔｃｈｉｎｇ）工程と、セルフアラインマスクとエッチング（Ｓｅｌｆ ａｌｉｇｎｅｄ ｍａｓｋ ａｎｄ ｅｔｃｈｉｎｇ）工程を行い、コントロールゲート電極を形成する。
【００２２】
【発明の効果】
以上説明したように、本発明は既存のマスクとエッチング工程によってフローティングゲートを形成した代わりに、フィールド酸化膜上に酸化膜凸部を形成し、酸化膜凸部同士の間にフローティングゲートを形成することにより、素子の臨界寸法を最小化し、素子の大きさを容易に調節でき、ウェーハ全体にわたって均一なフローティングゲートを形成することができる。また、均一なフローティングゲートによってセル間のカップリング比の差を減らすことにより、フラッシュメモリー素子の特性を向上させることができ、活性臨界寸法を減らすことにより、カップリング比を極大化することができる。
【００２３】
また、マスキング工程を減らすことにより、マスキング工程から発生するおそれのある問題点を解決することができ、工程の単純化を図ることができ、歩留り向上とコストダウンを実現することができる。また、酸化膜凸部の高さ及び間隔を調節することにより、多様な工程マージンを容易に確保することができる。
【図面の簡単な説明】
【図１】本発明に係る半導体素子の製造方法を説明するための断面図である。
【図２】本発明に係る半導体素子の製造方法を説明するための断面図である。
【図３】本発明に係る半導体素子の製造方法を説明するための断面図である。
【図４】本発明に係る半導体素子の製造方法を説明するための断面図である。
【符号の説明】
１０ …半導体基板
１２ …トンネル酸化膜
１４ …第１ポリシリコン膜
１６ …パッド窒化膜
１８ …トレンチ
２０ …ＨＤＰ酸化膜
２２ …ＨＤＰ酸化膜凸部
２４ …第２ポリシリコン膜
２６ …フローティングゲート電極
２８ …誘電体膜
３０ …第３ポリシリコン膜
３２ …タングステンシリサイド膜[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a floating gate of a flash device, which forms a floating gate by a self-alignment method.
[0002]
[Prior art]
Recently, as design rules and device sizes have decreased, it has been difficult to control field oxide (FOX) overlap, which has the greatest effect on the spacing and coupling between floating gates in an ETOX (EEPROM Tunnel Oxide) cell. ing. In general, a flash memory cell is realized by using an STI process. However, when performing isolation of a floating gate, the operation of a patterning process using a mask involves uniformity of a wafer due to a change in a critical dimension (CD) of a mask. However, there is a problem that the coupling ratio between the elements is not uniform because of the difficulty in the implementation. In addition, when a high bias voltage is applied during programming and erasing of the flash memory device, a defect of the flash memory device occurs due to an uneven floating gate. An alignment error between the isolation mask and the poly mask and an increase in the number of mask steps cause a decrease in yield and an increase in cost.
[0003]
[Problems to be solved by the invention]
Therefore, the present invention is to solve such a conventional problem, and an object of the present invention is to perform a patterning process in a state in which a tunnel oxide film and a first polysilicon film for forming a floating gate are deposited, and an STI is performed. By forming an element isolation film having a structure and depositing a second polysilicon film on the first polysilicon film to form a floating gate, the floating gate can be formed without using a mask process. It is an object of the present invention to provide a method of manufacturing a semiconductor device which can form a small-sized floating gate.
[0004]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a method of forming a tunnel oxide film, a first polysilicon film and a pad nitride film on a semiconductor substrate, and forming the pad nitride film and the first polysilicon film by the patterning process. Forming a trench in the semiconductor substrate by etching the film, the tunnel oxide film and a portion of the semiconductor substrate, and exposing the pad nitride film after depositing an oxide film on the entire structure including the trench. Flattening the oxide film, etching the pad nitride film to form an oxide film convex portion, depositing a second polysilicon film on the entire structure, and then forming the oxide film convex portion. Planarizing the second polysilicon film so that the oxide film is exposed; and etching a part of the exposed oxide film protrusion to form a floating gate, and then forming a dielectric. And characterized in that it comprises a step of forming a control gate.
[0005]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments, and various modifications can be realized. These examples are provided to complete the disclosure of the present invention and to inform those of ordinary skill in the art of the scope of the present invention. On the other hand, in the drawings, the same reference numerals indicate the same elements.
[0006]
1 to 4 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the present invention.
[0007]
Referring to FIG. 1A, a screen oxide film (not shown) serving as a buffer layer is formed on a semiconductor substrate 10 for suppressing crystal defects on a substrate surface or for performing a surface treatment and ion implantation, and then performing ion implantation. To form a well. After removing the screen oxide film, a tunnel oxide film 12, a first polysilicon film 14, and a pad nitride film 16 are deposited.
[0008]
Specifically, before the screen oxide film is formed, DHF (Dilute HF), NH 4 OH, H 2 having a mixing ratio of 50: 1 H 2 O and HF is used for cleaning the semiconductor substrate 10. BOE (Buffered Oxide Etch) and NHE using SC-1 (Standard Cleaning-1) composed of O 2 and H 2 O or having a mixing ratio of NH 4 F and HF of 100: 1 to 300: 1. A pretreatment cleaning step is performed using SC-1 consisting of 4 OH, H 2 O 2 and H 2 O. Dry or wet oxidation is performed within a temperature range of 750 to 800 ° C. to form the screen oxide film having a thickness of 30 to 100 °. After the ion implantation, 50: etching the screen oxide film using the first DHF having a mixing ratio of H 2 O and HF, NH 4 OH, and SC-1 consisting of H 2 O 2 and H 2 O . The tunnel oxide film 12 is formed to a thickness of 85 to 110 ° by a wet oxidation method at a temperature of 750 to 800 ° C., and is heat-treated at 900 to 910 ° C. using N 2 for 20 to 30 minutes after the deposition of the tunnel oxide film 12. By performing the process, the defect density at the interface between the tunnel oxide film 12 and the semiconductor substrate 10 is minimized. On the tunnel oxide film 12, at a temperature of 530 to 680 ° C. and a pressure of 0.1 to 3.0 torr, CVD (Chemical Vapor Deposition), LPCVD (Low Pressure CVD), PECVD (Plasma Enhanced CVD) or APCVD (Atmospheric Pressure). The first polysilicon film 14 having a thickness of 200 to 1000 Å is deposited using SiH 4 or Si 2 H 6 and PH 3 gas by a CVD method. Thus, the electric field concentration can be prevented by minimizing the grain size of the first polysilicon film 14. A pad nitride film 16 having a thickness of about 1300 to 3000 ° is formed on the first polysilicon film 14 by the LP-CVD method.
[0009]
Referring to FIG. 1B, the pad nitride film 16, the first polysilicon film 14, the tunnel oxide film 12, and the semiconductor substrate 10 are sequentially etched by ISO mask patterning to form an STI (Shallow Trench Isolation) structure. The active region and the field region are defined by forming the trench 18 of FIG. A dry oxidation process for compensating for etching damage on the side wall of the trench 18 having the STI structure is performed, and a corner portion of the trench 18 is rounded by performing a rapid thermal process. A high temperature oxide (HTO) is thinly deposited on the entire structure, and a densification process is performed at a high temperature to form a liner oxide film (not shown).
[0010]
Specifically, after a photosensitive film is applied on the entire structure, a photolithography process using a photosensitive film mask is performed to form a photosensitive film pattern (not shown). The pad nitride film 16, the first polysilicon film 14, the tunnel oxide film 12 and the semiconductor substrate 10 are etched by performing an etching process using the photoresist pattern as an etching mask to form a trench 18 having an STI structure. In order to compensate for the damage of the sidewall of the trench 18 due to the etching process, a dry oxidation process is performed within a temperature range of 800 to 1000 ° C. to form a sidewall oxide film having a thickness of 50 to 150 °. By performing a rapid heat treatment process using hydrogen (ie, utilizing the atomic transfer properties of the semiconductor substrate), rounding the corners of the trench and the corners of the trench to suppress the electric field concentration and improve the operating characteristics of the device Let it. The rapid thermal process is performed using a Fast Thermal Process (FTP) type device and flowing hydrogen gas of 100 to 2000 sccm under a temperature range of 600 to 1050 ° C. and a pressure of 300 to 380 torr for 5 to 15 minutes.
[0011]
In order to improve the adhesion characteristics between the oxide film and the trench 18 in the subsequent process and prevent generation of moat, HTO formed using DCS (Dichloro Silane; SiH 2 Cl 2 ) gas is 50 to 150 °. Then, a high-temperature densification process is performed at a temperature of 1000 to 1100 ° C. using N 2 for 20 to 30 minutes to form a liner oxide film (not shown). The high-temperature densification process makes the structure of the liner oxide film dense, increases the etching resistance, and suppresses the formation of moats when implementing STI, and also serves to prevent leakage current.
[0012]
Referring to FIG. 2A, a high-density plasma (HDP) oxide film 20 is deposited on the entire structure to fill the trench 18. A planarization process is performed using the pad nitride film 16 as a stop layer. Using the pad nitride film 16 as an etching stop layer, a planarization step for removing the HDP oxide film 20 and the liner oxide film on the pad nitride film 16 is performed.
[0013]
More specifically, an HDP (High Density Plasma) oxide film 20 is formed in a thickness range of 5000 to 10000 ° to fill the blank of the trench 18. At this time, the HDP oxide film 20 is deposited so that no space is formed inside the trench 18. After performing the planarization process using CMP, a post-cleaning process using BOE or HF is performed to remove an oxide film that may remain on the pad nitride film 16. At this time, it is necessary to suppress a decrease in the height of the HDP oxide film 20 due to the over-etching to a maximum.
[0014]
Referring to FIG. 2B, the HDP oxide film protrusion 22 is formed by performing a nitride film stripping process on the pad nitride film 16 using phosphoric acid dip-out (H 3 PO 4 dip out). When the pad nitride film 16 is stripped, the HDP oxide film protrusion 22 is set to a height of 700 to 2500 ° from the first polysilicon film 14. At this time, the step between the first polysilicon film 14 and the field oxide film is left so as to have a thickness of about 200 to 300 ° which is about the same as the thickness of the second polysilicon film formed in a subsequent process.
[0015]
Referring to FIG. 3A, after performing a pretreatment cleaning process, a second polysilicon film 24 is deposited on the entire structure. A floating gate electrode 26 is formed by removing the second polysilicon film 24 formed on the HDP oxide film protrusion 22 by performing a planarization process. More specifically, a pretreatment wet cleaning process using DHF and SC-1 is performed to form an overlap between the field oxide film and the polysilicon film. At this time, the wet cleaning time is adjusted to prevent the loss of the mout shape in the cell region and the tunnel oxide film 12 under the first polysilicon film 14. Further, the wet cleaning process is controlled so that about 2/3 (100 to 700 °) of the thickness of the first polysilicon film 14 is opened by the wet cleaning process. A second polysilicon film 24 of the same material as the first polysilicon film 14 is deposited to a thickness of 800 to 2500 ° to bury the HDP oxide film protrusion 22. Using PE-TEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), PE-Nit, PSG (Phosphorus Silicate Glass) and BPSG (Boron Phosphorus) In addition, variations that may occur in a planarization process using CMP are prevented. The buffer layer is deposited to a thickness of 100 to 1000 °.
[0016]
By removing the buffer layer and the second polysilicon film 24 on the HDP oxide film protrusion 22 by chemical mechanical polishing to isolate the second polysilicon film 24, the first and second polysilicon films 14, 24 are isolated. Is formed. In addition, the floating gate electrode (the entire thickness of the first and second polysilicon films) is uniformly left in a thickness range of 1000 to 2500 ° by chemical mechanical polishing.
[0017]
Referring to FIG. 3B, the exposed HDP oxide film protrusions 22 are removed by a thickness of 500 to 2000 Å using HF or BOE in a pretreatment cleaning process after the CMP process. As a result, the width and surface area of the floating gate electrode 26 can be formed smaller than those realized by the existing masking method, and the coupling ratio can be increased.
[0018]
Referring to FIG. 4, after a dielectric film 28 is formed along a step of the entire structure, a third polysilicon film 30 and a tungsten silicide (WSi) film 32 for forming a control gate are sequentially deposited. Specifically, various types of dielectric films used for semiconductor devices are deposited. In this embodiment, an ONO (oxide film / nitride film / oxide film (SiO 2 —Si 3 N 4 —SiO 2 ) or ONON structure) is used. In the dielectric film 28 having the ONO structure, the oxide film in the ONO structure is formed using DCS (SiH 2 Cl 2 ) and N 2 O gas having excellent withstand voltage and TDDB characteristics. A low pressure of about 3 torr and a temperature of about 810 to 850 ° C. are deposited by LP-CVD to a thickness of about 35 to 60 °.
[0019]
Further, the nitride film in ONO structure is deposited by the LP-CVD method to a thickness of about 50~65Å at a temperature of about the low-pressure and 650 to 800 ° C. for 1~3torr using DCS and NH 3 gas. After performing the ONO process, in order to improve the quality of the ONO oxide film and strengthen the interface between the floors, the thickness of the wet wafer is about 150 to 300 ° C. based on the monitoring wafer at a temperature of about 750 to 800 ° C. Steam annealing can be performed so as to oxidize. In addition, when the ONO process and the steam annealing are performed, a process in which a delay time between each process is within several hours is performed to prevent contamination by a natural oxide film or impurities.
[0020]
The third polysilicon film 30 is doped to prevent the diffusion of hydrofluoric acid, which can be replaced with the dielectric film 28 when the tungsten silicide film 32 is deposited and solid oxide can increase the thickness of the oxide film. An amorphous silicon film is deposited by LP-CVD at a temperature of about 510 to 550 [deg.] C. and a pressure of 1.0 to 3 torr in a double layer structure of a doped layer and an undoped layer. At this time, the ratio of the doped film to the undoped film is set to 1: 2 to 6: 1, and the thickness is set to about 500 to 1000 ° so that the space between the floating gate electrodes 26 is sufficiently filled. By forming the amorphous silicon film, it is possible to suppress the formation of a gap during the subsequent deposition of the tungsten silicide film 32 and reduce the word line resistance Rs. When forming the third polysilicon film layer having the double structure, a doped film is formed using SiH 4 or Si 2 H 6 and PH 3 gas, and then the PH 3 gas is cut off to continuously form the doped film. It is desirable to form an undoped film.
[0021]
The tungsten silicide film 32 is formed by using a reaction between WF 6 and MS (SiH 4 ) or DCS (SiH 2 Cl 2 ) having a low fluorine content and a low post-annealed stress and a good adhesive strength. , A suitable step coverage at a temperature of 300 to 500 ° C., and a stoichiometric ratio of about 2.0 to 2.8 capable of minimizing the word line resistance Rs. Is better. Tungsten silicide film 32 using SiOxNy or Si 3 N 4 on the deposited ARC layer (not shown), a gate mask and etching (Gate mask and Etching) process, a self-aligned mask and etching (Self aligned mask and etching Step) to form a control gate electrode.
[0022]
【The invention's effect】
As described above, according to the present invention, instead of forming a floating gate by an existing mask and an etching process, an oxide film convex portion is formed on a field oxide film, and a floating gate is formed between the oxide film convex portions. Thereby, the critical dimension of the device can be minimized, the size of the device can be easily adjusted, and a uniform floating gate can be formed over the entire wafer. Also, the characteristics of the flash memory device can be improved by reducing the difference in the coupling ratio between cells by a uniform floating gate, and the coupling ratio can be maximized by reducing the active critical dimension. .
[0023]
Further, by reducing the number of masking steps, it is possible to solve a problem that may occur from the masking step, simplify the steps, and improve the yield and reduce the cost. In addition, various process margins can be easily secured by adjusting the height and the interval of the oxide film protrusions.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to the present invention.
FIG. 2 is a sectional view illustrating a method for manufacturing a semiconductor device according to the present invention.
FIG. 3 is a sectional view illustrating a method for manufacturing a semiconductor device according to the present invention.
FIG. 4 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to the present invention.
[Explanation of symbols]
Reference Signs List 10 semiconductor substrate 12 tunnel oxide film 14 first polysilicon film 16 pad nitride film 18 trench 20 HDP oxide film 22 HDP oxide film protrusion 24 second polysilicon film 26 floating gate electrode 28 Dielectric film 30 Third polysilicon film 32 Tungsten silicide film

Claims (9)

（ａ）半導体基板上にトンネル酸化膜、第１ポリシリコン膜及びパッド窒化膜を順次形成する段階と、
（ｂ）パターニング工程によって前記パッド窒化膜、前記第１ポリシリコン膜、前記トンネル酸化膜及び前記半導体基板の一部をエッチングして前記半導体基板内にトレンチを形成する段階と、
（ｃ）前記トレンチを含む全体構造上に酸化膜を蒸着した後、前記パッド窒化膜が露出するように前記酸化膜を平坦化する段階と、
（ｄ）前記パッド窒化膜をエッチングして酸化膜凸部を形成する段階と、
（ｅ）全体構造上に第２ポリシリコン膜を蒸着した後、前記酸化膜凸部が露出するように前記第２ポリシリコン膜を平坦化する段階と、
（ｆ）前記露出した酸化膜凸部の一部をエッチングしてフローティングゲートを形成した後、誘電体膜及びコントロールゲートを形成する段階とを含んでなることを特徴とする半導体素子の製造方法。(A) sequentially forming a tunnel oxide film, a first polysilicon film and a pad nitride film on a semiconductor substrate;
(B) etching the pad nitride film, the first polysilicon film, the tunnel oxide film, and a portion of the semiconductor substrate by a patterning process to form a trench in the semiconductor substrate;
(C) depositing an oxide film on the entire structure including the trench, and planarizing the oxide film so that the pad nitride film is exposed;
(D) etching the pad nitride film to form an oxide film protrusion;
(E) depositing a second polysilicon film on the entire structure, and then planarizing the second polysilicon film so that the oxide film protrusion is exposed;
(F) etching a part of the exposed oxide film projection to form a floating gate, and then forming a dielectric film and a control gate. 前記第１ポリシリコン膜は、５３０〜６８０℃の温度と０．１〜３．０ｔｏｒｒの圧力下でＣＶＤ、ＬＰＣＶＤ、ＰＥＣＶＤまたはＡＰＣＶＤ法によってＳｉＨ４またはＳｉ２Ｈ６とＰＨ３ガスを用いて２００〜１０００Åの厚さに形成することを特徴とする請求項１記載の半導体素子の製造方法。The first polysilicon film, using CVD at a pressure of temperature and 0.1~3.0torr of five hundred thirty to six hundred and eighty ° C., LPCVD, by PECVD or APCVD method SiH 4 or Si 2 H 6 and PH 3 gas 200 2. The method according to claim 1, wherein the semiconductor device is formed to a thickness of about 1000.degree. 前記トンネル酸化膜は、７５０〜８００℃の温度でウェット酸化方式によって８５〜１１０Åの厚さに蒸着され、９００〜９１０℃の温度範囲でＮ２を用いて２０〜３０分間アニールを行って形成することを特徴とする請求項１記載の半導体素子の製造方法。The tunnel oxide film is deposited at a temperature of 750 to 800 ° C. to a thickness of 85 to 110 ° by a wet oxidation method, and is formed by annealing at 900 to 910 ° C. using N 2 for 20 to 30 minutes. The method for manufacturing a semiconductor device according to claim 1, wherein: 前記（ａ）段階の前に、イオン注入工程を行って前記半導体基板内にウェルを形成する段階をさらに含むことを特徴とする請求項１記載の半導体素子の製造方法。2. The method according to claim 1, further comprising performing an ion implantation process to form a well in the semiconductor substrate before the step (a). 前記（ｂ）段階と前記（ｃ）段階との間に、前記トレンチ形成の際に発生した前記半導体基板のダメージを補償するための側壁酸化工程を行う段階と、
前記トレンチのコーナー部分をラウンディングするための急速熱処理工程を行う段階と、
全体構造上にその段差に沿って高温酸化膜を蒸着した後、高温で緻密化工程を行う段階とをさらに含むことを特徴とする請求項１記載の半導体素子の製造方法。Performing a sidewall oxidation process between the steps (b) and (c) to compensate for damage to the semiconductor substrate that has occurred during the formation of the trench;
Performing a rapid heat treatment process for rounding a corner portion of the trench;
2. The method according to claim 1, further comprising the step of: depositing a high-temperature oxide film on the entire structure along the step, and performing a densification process at a high temperature. 前記（ｄ）段階と前記（ｅ）段階との間に、前記トンネル酸化膜の損失を防止するためのウェット洗浄工程を行って前記第１ポリシリコン膜を厚さ１００〜７００Åだけ除去する段階をさらに含むことを特徴とする請求項１記載の半導体素子の製造方法。A step of performing a wet cleaning process to prevent the loss of the tunnel oxide film between the steps (d) and (e) to remove the first polysilicon film by a thickness of 100 to 700 degrees. The method for manufacturing a semiconductor device according to claim 1, further comprising: 前記（ｅ）段階は、
全体構造上に前記第２ポリシリコン膜を蒸着する段階と、
前記第２ポリシリコン膜の上部に前記第２ポリシリコン膜の上部表面の段差を減らすためのバッファー層を蒸着する段階と、
前記酸化膜凸部を停止層とするＣＭＰ工程を行って前記バッファー層と前記第２ポリシリコン膜を平坦化する段階を含むことを特徴とする請求項１記載の半導体素子の製造方法。The step (e) includes:
Depositing the second polysilicon film on the entire structure;
Depositing a buffer layer on the second polysilicon layer to reduce a step on an upper surface of the second polysilicon layer;
2. The method according to claim 1, further comprising: performing a CMP process using the oxide film protrusion as a stop layer to planarize the buffer layer and the second polysilicon film. 前記バッファー層はＰＥ−ＣＶＤ法で形成されたＰＥ−ＴＥＯＳ層、ＰＥ−Ｎｉｔ層、ＰＳＧ層及びＢＰＳＧ層の少なくとも１つであることを特徴とする請求項７記載の半導体素子の製造方法。The method according to claim 7, wherein the buffer layer is at least one of a PE-TEOS layer, a PE-Nit layer, a PSG layer, and a BPSG layer formed by a PE-CVD method. 前記第２ポリシリコン膜は、５３０〜６８０℃の温度と０．１〜３．０ｔｏｒｒの圧力下でＣＶＤ、ＬＰＣＶＤ、ＰＥＣＶＤまたはＡＰＣＶＤ法によってＳｉＨ４またはＳｉ２Ｈ６とＰＨ３ガスを用いて８００〜２５００Åの厚さに形成することを特徴とする請求項１又は７記載の半導体素子の製造方法。The second polysilicon film may be formed by CVD, LPCVD, PECVD or APCVD at a temperature of 530-680 ° C. and a pressure of 0.1-3.0 torr using SiH 4 or Si 2 H 6 and PH 3 gas. 8. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed to a thickness of about 2500.degree.
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