KR100517351B1 - Method for manufacturing device isolation barrier of semiconductor device - Google Patents
Method for manufacturing device isolation barrier of semiconductor device Download PDFInfo
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- KR100517351B1 KR100517351B1 KR10-2003-0071029A KR20030071029A KR100517351B1 KR 100517351 B1 KR100517351 B1 KR 100517351B1 KR 20030071029 A KR20030071029 A KR 20030071029A KR 100517351 B1 KR100517351 B1 KR 100517351B1
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 238000002955 isolation Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 230000004888 barrier function Effects 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 title 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 150000004767 nitrides Chemical class 0.000 claims abstract description 20
- 229910052786 argon Inorganic materials 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000004381 surface treatment Methods 0.000 claims abstract description 5
- 230000001590 oxidative effect Effects 0.000 claims abstract description 3
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims description 5
- -1 argon ions Chemical class 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 7
- 238000001312 dry etching Methods 0.000 abstract description 5
- 239000002245 particle Substances 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000007849 functional defect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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Abstract
본 발명은 반도체 소자의 소자 분리막 형성 방법에 관한 것으로, 보다 자세하게는 실리콘 기판상에 패드 산화막(Pad Oxide)과 질화막(Nitride) 그리고 트렌치(trench)를 연속적으로 형성한 후 라이너 옥사이드(Liner-Oxide)층을 형성하고 상기 라이너 옥사이드층의 트렌치 상부 코너(corner) 부분을 제거해 주는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation layer of a semiconductor device, and more particularly, to a liner oxide after forming a pad oxide film, a nitride film, and a trench continuously on a silicon substrate. A method of forming a layer and removing a trench upper corner portion of the liner oxide layer.
본 발명의 반도체 소자의 소자 분리막 형성 방법은 실리콘 기판 위에 패드 산화막과 질화막을 형성하고 상기 질화막과 패드 산화막, 실리콘 기판을 일정 깊이로 식각하여 트렌치를 형성하는 단계; 상기 트렌치가 형성된 기판을 열산화하여 상기 트렌치 내벽에 라이너 옥사이드층을 형성하는 단계; 상기 기판 전면을 아르곤 플라즈마에 의해 식각하여 상기 트렌치 상부 코너부분의 라이너 옥사이드층 및 질화막의 일부를 제거하는 단계; 및 상기 트렌치를 산화막으로 충진하는 단계로 이루어짐에 기술적 특징이 있다.A method of forming a device isolation layer of a semiconductor device according to the present invention includes forming a pad oxide film and a nitride film on a silicon substrate, and forming a trench by etching the nitride film, the pad oxide film, and the silicon substrate to a predetermined depth; Thermally oxidizing the substrate on which the trench is formed to form a liner oxide layer on the inner wall of the trench; Etching the entire surface of the substrate by argon plasma to remove a portion of the liner oxide layer and the nitride film of the upper corner portion of the trench; And a step of filling the trench with an oxide film.
따라서, 본 발명의 반도체 소자의 소자 분리막 형성 방법은 아르곤(Ar+) 플라즈마를 이용한 건식식각을 통하여 트렌치 상부 코너 부분의 라이너 옥사이드와 하부 질화막의 일부를 제거해줌으로써 트렌치의 개구부가 넓어지고, 아르곤(Ar+) 입자에 의한 라이너 옥사이드 막의 표면처리 효과에 의해 O3-TEOS 산화막과의 계면특성이 개선됨으로써 트렌치 갭필(gap-fill)이 향상되어 종래 기술에 의해 야기될 수 있는 보이드(void)의 발생을 억제할 수 있는 효과가 있다.Accordingly, in the method of forming a device isolation layer of the semiconductor device of the present invention, the opening of the trench is widened by removing part of the liner oxide and the lower nitride film in the upper corner portion of the trench through dry etching using an argon (Ar +) plasma, and argon (Ar +). Due to the surface treatment effect of the liner oxide film by the particles, the interfacial property with the O 3 -TEOS oxide film is improved, so that the trench gap-fill is improved to suppress the generation of voids that may be caused by the prior art. It can be effective.
Description
본 발명은 반도체 소자의 소자 분리막 형성 방법에 관한 것으로, 보다 자세하게는 실리콘 기판상에 패드 산화막(Pad Oxide)과 질화막(Nitride) 그리고 트렌치(trench)를 연속적으로 형성한 후 라이너 옥사이드(Liner-Oxide) 층을 형성하고 상기 라이너 옥사이드 층의 트렌치 상부 코너(corner) 부분을 제거해 주는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation layer of a semiconductor device, and more particularly, to a liner oxide after forming a pad oxide film, a nitride film, and a trench continuously on a silicon substrate. A method of forming a layer and removing a trench upper corner portion of the liner oxide layer.
종래에는, 일반적으로 반도체 소자를 분리하는 방법으로 선택적으로 질화막을 이용하는 LOCOS(Local Oxidation of Sillicon, 이하 LOCOS) 소자 분리 방법이 이용되어 왔다. LOCOS 소자 분리 방법은 질화막을 마스크로 해서 실리콘 웨이퍼 자체를 열산화시키기 때문에 공정이 간소해서 산화막의 소자 응력 문제가 적고, 생성되는 산화막질이 좋다는 이점이 있다. 그러나, LOCOS 소자 분리 방법을 이용하면 소자 분리 영역이 크기 때문에 소자의 미세화에 한계가 있을 뿐만 아니라 버즈비크(bird's beak)가 발생하게 된다.Conventionally, a LOCOS (Local Oxidation of Sillicon, LOCOS) device isolation method using a nitride film selectively has been used as a method for separating semiconductor devices. Since the LOCOS device isolation method thermally oxidizes the silicon wafer itself using a nitride film as a mask, the process is simple, and there is an advantage that the device stress problem of the oxide film is small, and the resulting oxide film quality is good. However, when the LOCOS device isolation method is used, the device isolation region is large, thereby limiting the miniaturization of the device and generating bird's beak.
상기와 같은 문제점을 극복하기 위해 LOCOS 소자 분리 방법을 대체하는 기술로서 트렌치 소자 분리(Shallow Trench Isolation, 이하 STI)가 있다. 트렌치 소자 분리에서는 실리콘 웨이퍼에 트렌치를 만들어 절연물을 집어넣기 때문에 소자 분리 영역이 차지하는 면적이 작아서 소자의 미세화에 유리하다. 현재 적용되는 STI 공정은 반도체 기판을 건식식각하여 트렌치를 형성한 후 건식식각으로 인한 손상을 큐어링(curing)한 후, 계면특성 및 활성영역과 소자격리 영역의 모서리 라운딩 특성을 향상시키기 위해 트렌치 내부를 열산화하여 산화막을 형성하는 공정을 진행한다. 이 후 산화막이 형성된 트렌치를 메우도록 반도체 기판 전면에 절연막을 두껍게 증착하고 화학적 기계적 연마(Chemical Mechanical Polishing, 이하 CMP)를 진행하여 반도체 기판을 평탄화한다.In order to overcome the problems described above, as a technique for replacing the LOCOS device isolation method, there is trench trench isolation (hereinafter, STI). In trench device isolation, a trench is formed in a silicon wafer to insulate the insulator, so the area of the device isolation region is small, which is advantageous for miniaturization of the device. Currently applied STI process is to dry the semiconductor substrate to form the trench, and then to cure the damage caused by the dry etching, and then to improve the interface characteristics and the corner rounding characteristics of the active region and the device isolation region inside the trench Is thermally oxidized to form an oxide film. Thereafter, an insulating film is thickly deposited on the entire surface of the semiconductor substrate so as to fill the trench in which the oxide film is formed, and chemical mechanical polishing (CMP) is performed to planarize the semiconductor substrate.
그러나, 상기와 같은 종래의 STI 공정은 고집적화된 소자일수록 소자간 간격이 좁아짐과 동시에 트렌치 기울기(Trench Slope)도 거의 직각을 이룰 수 밖에 없다. 따라서 산화막의 갭필(gap-fill)이 이루어지지 않아 보이드(void)가 발생할 수 있는 문제점이 있다. 또한 상기 트렌치를 갭필하는 산화막으로는 갭필 특성과 평탄화 특성이 양호한 O3-TEOS(O3-TetraEthylOrthoSilicate, 이하 O3-TEOS) 상압화학기상증착(Atmospheric Pressure Chemical Vapor Deposition, 이하 APCVD) 산화막, 고밀도 플라즈마 화학기상증착(High Density Plasma Chemical Vapor Deposition) 산화막이 주로 사용되어 오고 있다. 상기 O3-TEOS 산화막은 하지층의 막 종류, 하지층의 막 표면 전하의 종류 및 밀도 분포에 따라 적층율 및 식각율과 표면 형상이 상이해지는 특성을 가지고 있어서 모우트 습식 에칭(Moat-Wet Etch)이나 CMP 등의 후속공정 진행시 보이드를 유발할 수 있다. 도 1에서 상기와 같은 종래의 기술에 의해 완전한 갭필이 이루어지지 않아 형성된 보이드의 단면사진을 볼 수 있다.However, in the conventional STI process as described above, the spacing between the devices becomes narrower and the trench slopes are almost right at the same time as the integrated devices become higher. Therefore, there is a problem that voids may occur because a gap-fill of the oxide layer is not performed. In addition, the oxide film gap-filling the trench may be O 3 -TEOS (O 3 -TetraEthylOrthoSilicate, hereinafter O 3 -TEOS) Atmospheric Pressure Chemical Vapor Deposition (APCVD) oxide film having high gap fill characteristics and planarization characteristics, and high density plasma. High Density Plasma Chemical Vapor Deposition An oxide film has been mainly used. The O 3 -TEOS oxide film has a characteristic that the lamination rate, the etch rate and the surface shape are different depending on the type of the base layer, the type of the surface charge of the base layer, and the density distribution, and thus the wet wet etching (Moat-Wet Etch). ) Or CMP may cause voids in the subsequent process. In Figure 1 can be seen a cross-sectional picture of the void formed by a complete gap fill is not made by the prior art as described above.
상기의 문제를 해결하기 위한 종래의 기술로서, 대한민국 공개특허 제 2002-9196호에는 O3-TEOS 산화막의 하지층 종류에 따라 적층률이 상이해지는 특성을 이용하고 있다. 도 2a에 도시된 바와 같이, 실리콘 기판(1)의 표면 전체에 패드 산화막과 질화막으로 이루어진 희생막(2)을 적층하고, 상기 반도체 기판의 필드영역을 노출시키고 나머지 영역을 마스킹하는 희생막의 패턴을 형성한다. 이어, 상기 희생막의 패턴을 마스킹 막으로 이용하고 반응성 이온 식각(Reactive Ion Etching)에 의해 상기 필드영역의 반도체 기판을 일정 깊이만큼 식각하여 트렌치(3)를 형성한다. 그런 다음, 트렌치 내의 노출된 하면부 및 측면부에 고온의 퍼니스(furnace)를 이용한 저압 화학기상증착 공정에 의해 산화막(4)을 형성한다. 이어서 상기 트렌치의 측면부에만 산화막을 남김과 아울러 상기 트렌치의 하면부 상의 다결정 실리콘막을 노출시키고 플라즈마 처리를 한다. 이렇게 하면 상기 트렌치의 측면부에서보다 하면부에서의 O3-TEOS 산화막 적층률을 높임으로써, 트렌치의 종횡비가 큰 경우에도 완전한 갭필을 이룰 수 있다. 이어서 도 2b에 도시된 바와 같이, 상압 화학기상증착공정을 이용하여 트렌치를 채울 수 있을 정도의 두꺼운 두께로 O3-TEOS 산화막을 적층하여 상기 트렌치를 갭필한다. 이어서 상기 O3-TEOS 산화막을 어닐링한 후, 도면에 도시되지 않았으나, 상기 O3-TEOS 산화막을 화학기계적 연마공정에 의해 평탄화한다. 또한, 미국 특허 US 6,387,764에서는 트렌치 내부벽에 산화막을 먼저 생성한 후 O3-TEOS를 충진하는 종래의 공정순서를 따르지 않고, CVD(Chemical Vapor Deposition)방식으로 산화막을 먼저 충진한 후에 RTP(Rapid Thermal Process) 시스템을 이용해 트렌치 내부벽에 산화막을 형성함으로써 갭필을 향상시킨다고 보고하였다. 한편 대한민국 공개특허 제 2003-43445호에는 이중경사 구조를 가지는 트렌치를 형성함으로써, 상기 트렌치 상부의 폭을 하면부의 폭보다 크게 하여 갭필 능력을 향상시키는 기술이 개시되어 있지만 공정단계가 복잡하고 그 효과가 미비하여 실효성이 적다는 단점이 있다.As a conventional technique for solving the above problem, Korean Patent Laid-Open Publication No. 2002-9196 utilizes the property that the lamination rate is different depending on the type of the underlying layer of the O 3 -TEOS oxide film. As shown in FIG. 2A, a sacrificial film 2 including a pad oxide film and a nitride film is laminated on the entire surface of the silicon substrate 1, and a pattern of a sacrificial film that exposes a field region of the semiconductor substrate and masks the remaining region is formed. Form. Subsequently, the trench 3 is formed by etching the semiconductor substrate in the field region by a predetermined depth by using the pattern of the sacrificial layer as a masking layer and by reactive ion etching. Then, the oxide film 4 is formed by a low pressure chemical vapor deposition process using a high temperature furnace in the exposed lower and side portions of the trench. Subsequently, the oxide film is left only on the side surface of the trench, and the polycrystalline silicon film on the bottom surface of the trench is exposed and subjected to plasma treatment. In this way, by increasing the O 3 -TEOS oxide film stacking ratio at the lower surface portion than at the side surface portion of the trench, a perfect gap fill can be achieved even when the aspect ratio of the trench is large. Subsequently, as illustrated in FIG. 2B, the trench is gap-filled by stacking an O 3 -TEOS oxide layer to a thickness thick enough to fill the trench using an atmospheric pressure chemical vapor deposition process. It was then annealing the O 3 -TEOS oxide film, not shown in the figure, and planarizing the O 3 -TEOS oxide film by a chemical mechanical polishing process. In addition, US Pat. No. 6,387,764 discloses an RTP (Rapid Thermal Process) after first filling an oxide film by CVD (Chemical Vapor Deposition) method, instead of following a conventional process procedure of first forming an oxide film on the trench inner wall and then filling O 3 -TEOS. It is reported that the gap fill is improved by forming an oxide film on the inner wall of the trench using the system. On the other hand, Korean Patent Laid-Open Publication No. 2003-43445 discloses a technique of improving the gap fill capability by forming a trench having a double inclined structure to make the width of the upper portion of the trench larger than the width of the lower surface portion, but the process step is complicated and the effect is There is a disadvantage in that the effectiveness is insufficient.
따라서, 본 발명의 반도체 소자의 소자 분리막 형성 방법은 아르곤 플라즈마를 이용한 건식식각을 통하여 트렌치 상부 코너 부분의 라이너 옥사이드층과 질화막의 일부를 제거해 줌으로써 트렌치의 개구부가 넓어지고, 아르곤 입자에 의한 리니어 옥사이드 막의 표면처리 효과에 의해 O3-TEOS 산화막과의 계면특성이 개선됨으로써 트렌치 갭필이 향상되어 종래 기술에 의해 야기될 수 있는 보이드의 발생을 억제할 수 있는 방법을 제공함에 본 발명의 목적이 있다.Accordingly, in the method of forming a device isolation layer of the semiconductor device of the present invention, the opening of the trench is widened by removing part of the liner oxide layer and the nitride film in the upper corner portion of the trench through dry etching using an argon plasma, and thus the linear oxide film is formed by argon particles. It is an object of the present invention to provide a method capable of suppressing the generation of voids that can be caused by the prior art by improving the trench gapfill by improving the interfacial properties with the O 3 -TEOS oxide film by the surface treatment effect.
본 발명의 상기 목적은 실리콘 기판 위에 패드 산화막과 질화막을 형성하고 상기 질화막과 패드 산화막, 실리콘 기판을 일정 깊이로 식각하여 트렌치를 형성하는 단계; 상기 트렌치가 형성된 기판을 열산화하여 상기 트렌치 내벽에 라이너 옥사이드층을 형성하는 단계; 상기 기판 전면을 아르곤 플라즈마에 의해 식각하여 상기 트렌치 상부 코너부분의 라이너 옥사이드층 및 질화막의 일부를 제거하는 단계; 및 상기 트렌치를 산화막으로 충진하는 단계를 포함하는 반도체 소자의 소자분리막 형성 방법에 의해 달성된다.The object of the present invention is to form a trench by forming a pad oxide film and a nitride film on a silicon substrate and etching the nitride film, the pad oxide film, a silicon substrate to a predetermined depth; Thermally oxidizing the substrate on which the trench is formed to form a liner oxide layer on the inner wall of the trench; Etching the entire surface of the substrate by argon plasma to remove a portion of the liner oxide layer and the nitride film of the upper corner portion of the trench; And filling the trench with an oxide film.
본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.
먼저, 도 3a는 STI 소자분리 공정에 관한 것이다. 실리콘 기판(10) 위에 패드 산화막(Pad Oxide)(11)과 질화막(12)을 연속적으로 증착하고 소자 분리막 형성을 위해 모우트 건식 에칭을 시행하여 트렌치 형성을 위한 질화막 패턴을 형성한 후 드러난 패드 산화막과 적정깊이의 실리콘 기판을 식각하여 트렌치를 형성한다.First, FIG. 3A relates to an STI device isolation process. The pad oxide film 11 and the nitride film 12 are successively deposited on the silicon substrate 10, and a morph dry etching is performed to form a device isolation layer, thereby forming a nitride film pattern for trench formation. And a silicon substrate having an appropriate depth are etched to form a trench.
다음, 도 3b는 아르곤 플라즈마를 이용해 트렌치 상부 코너를 식각하는 공정에 관한 것이다. 트렌치가 형성된 상기의 구조물을 열산화하여 트렌치 내벽에 라이너 옥사이드층을 형성한다. 상기 옥사이드층은 150 내지 300 Å 두께로 형성하는 것이 바람직하다. 이어서 아르곤 이온(14)으로 트렌치 상부 코너 부분의 라이너 옥사이드층의 일부를 제거함과 동시에 질화막의 일부를 제거하여 질화막의 패턴 폭이 트렌치 폭보다 크게 되도록 한다. 이를 통해 트렌치의 개구부가 넓어지는 효과와 더불어 아르곤 플라즈마에 의한 트렌치 내부의 라이너 옥사이드층에 표면처리 효과를 주어 결과적으로 갭필의 향상을 이룰 수 있다. 여기서 표면처리 효과란, 상기 아르곤 플라즈마에 의해 트렌치 하면부의 리니어 옥사이드층이 측면부의 옥사이드층보다 액티브(active)한 상태로 변화되어 측면부보다 상대적으로 적층률을 높일 수 있으며 결과적으로 갭필의 향상을 도모할 수 있는 실험적 효과이다. 이 때 개구부를 넓히기 위해 과도한 식각 공정을 하게 되면 STI 부분에 손상(damage)을 주게 되어 후속 공정 진행시 게이트 옥사이드(Gate-Oxide) 형성이나 다른 기능적 결함(Functional Fail)을 유발할 수 있으므로 주의하여야 한다.Next, FIG. 3B relates to a process of etching a trench upper corner using an argon plasma. The structure in which the trench is formed is thermally oxidized to form a liner oxide layer on the inner wall of the trench. The oxide layer is preferably formed to a thickness of 150 to 300 kPa. Subsequently, a portion of the liner oxide layer in the upper corner portion of the trench is removed with argon ions 14 and a portion of the nitride film is removed so that the pattern width of the nitride film is larger than the trench width. As a result, the opening of the trench may be widened, and the liner oxide layer inside the trench may be surface-treated by argon plasma, thereby improving the gap fill. Here, the surface treatment effect means that the linear oxide layer of the trench lower portion of the trench is changed to an active state than the oxide layer of the side portion by the argon plasma, thereby increasing the lamination rate relatively to the side portion and consequently improving the gap fill. It can be an experimental effect. At this time, the excessive etching process to widen the opening will damage the STI portion, which may cause the formation of gate oxide or other functional defects in the subsequent process.
다음, 도 3c는 식각이 진행된 라이너 옥사이드층 위에 STI 충진 산화막(STI-Fill Layer)(15)을 형성한 공정에 관한 것이다. 산화막의 충진은 APCVD 방식인 WJ-1000T, WJ-1500T 장비를 이용하고 O3-TEOS를 재료로 하여 8층으로 적층하는 것이 바람직하다. 도에는 도시되지는 않지만, 충진 산화막을 증착한 후 불순물을 제거하기 위해 모우트 습식 에칭을 실시하고, 증착막의 안정화를 위해 열처리를 실시한다. 이 후 후속공정을 원활히 진행하기 위한 평탄화 공정으로 CMP 공정을 진행한다.Next, FIG. 3C relates to a process of forming an STI-fill layer 15 on the liner oxide layer etched. Filling the oxide film is preferably laminated in eight layers using WJ-1000T and WJ-1500T equipment, which are APCVD methods, and using O 3 -TEOS as a material. Although not shown in the figure, after depositing the filled oxide film, a moist wet etching is performed to remove impurities, and heat treatment is performed to stabilize the deposited film. After that, the CMP process is performed as a planarization process for smoothly proceeding the subsequent process.
상세히 설명된 본 발명에 의하여 본 발명의 특징부를 포함하는 변화들 및 변형들이 당해 기술 분야에서 숙련된 보통의 사람들에게 명백히 쉬워질 것임이 자명하다. 본 발명의 그러한 변형들의 범위는 본 발명의 특징부를 포함하는 당해 기술 분야에 숙련된 통상의 지식을 가진 자들의 범위 내에 있으며, 그러한 변형들은 본 발명의 청구항의 범위 내에 있는 것으로 간주된다.It will be apparent that changes and modifications incorporating features of the invention will be readily apparent to those skilled in the art by the invention described in detail. It is intended that the scope of such modifications of the invention be within the scope of those of ordinary skill in the art including the features of the invention, and such modifications are considered to be within the scope of the claims of the invention.
따라서, 본 발명의 반도체 소자의 소자 분리막 형성 방법은 아르곤 플라즈마를 이용한 건식 식각을 통하여 트렌치 상부 코너 부분의 라이너 옥사이드층과 하부 질화막의 일부를 제거해 줌으로써 트렌치의 개구부가 넓어지고, 아르곤 입자에 의한 라이너 옥사이드 층의 표면처리 효과에 의해 O3-TEOS 산화막과의 계면특성이 개선됨으로써 트렌치 갭필이 향상되어 종래 기술에 의해 야기될 수 있는 보이드의 발생을 억제할 수 있는 효과가 있다.Therefore, in the method of forming a device isolation layer of the semiconductor device of the present invention, the opening of the trench is widened by removing part of the liner oxide layer and the lower nitride film of the upper corner portion of the trench through dry etching using argon plasma, and the liner oxide of the argon particles. By improving the interfacial properties with the O 3 -TEOS oxide film due to the surface treatment effect of the layer, the trench gapfill is improved to suppress the generation of voids that may be caused by the prior art.
도 1은 종래기술에 의해 형성된 보이드의 단면사진.1 is a cross-sectional photograph of a void formed by the prior art.
도 2a 내지 도 2c는 본 발명에 따른 소자분리막 형성의 공정단면도.2A to 2C are cross-sectional views of a device isolation film formation according to the present invention.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2003-0071029A KR100517351B1 (en) | 2003-10-13 | 2003-10-13 | Method for manufacturing device isolation barrier of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR10-2003-0071029A KR100517351B1 (en) | 2003-10-13 | 2003-10-13 | Method for manufacturing device isolation barrier of semiconductor device |
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| Publication Number | Publication Date |
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| KR20050035607A KR20050035607A (en) | 2005-04-19 |
| KR100517351B1 true KR100517351B1 (en) | 2005-09-27 |
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| KR10-2003-0071029A KR100517351B1 (en) | 2003-10-13 | 2003-10-13 | Method for manufacturing device isolation barrier of semiconductor device |
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| KR (1) | KR100517351B1 (en) |
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| KR20050035607A (en) | 2005-04-19 |
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