KR100567344B1 - Method for fabricating isolation barrier of semiconductor device - Google Patents

Method for fabricating isolation barrier of semiconductor device Download PDF

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KR100567344B1
KR100567344B1 KR1020030101789A KR20030101789A KR100567344B1 KR 100567344 B1 KR100567344 B1 KR 100567344B1 KR 1020030101789 A KR1020030101789 A KR 1020030101789A KR 20030101789 A KR20030101789 A KR 20030101789A KR 100567344 B1 KR100567344 B1 KR 100567344B1
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film
device isolation
forming
etching
semiconductor device
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KR20050069581A (en
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김인수
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동부아남반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Abstract

본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로, 보다 자세하게는 고밀도 플라즈마를 이용해 다층의 적층막과 실리콘 기판을 동시에 식각하여 소자분리막을 형성함으로써 생산성의 향상과 결함의 발생을 억제할 수 있는 방법에 관한 것이다. The present invention relates to a method for forming a device isolation film of a semiconductor device, and more particularly, to improve the productivity and suppress the occurrence of defects by forming a device isolation film by simultaneously etching a multilayer film and a silicon substrate using a high density plasma. It is about.

본 발명의 반도체 소자의 소자분리막 형성방법은 반도체 기판의 상부에 다층의 적층막을 형성하는 단계; 소자분리막이 형성될 영역을 개방하는 패턴을 형성하여 고밀도 플라즈마를 이용한 식각을 실시하는 단계; 및 다층의 적층막과 실리콘 기판을 동시에 식각하여 소자분리막을 형성하는 단계로 이루어짐에 기술적 특징이 있다.The device isolation film forming method of the semiconductor device of the present invention comprises the steps of forming a multilayer film on the semiconductor substrate; Forming a pattern for opening a region in which the device isolation layer is to be formed and performing etching using a high density plasma; And forming a device isolation film by simultaneously etching the multilayer film and the silicon substrate.

따라서, 본 발명의 반도체 소자의 소자분리막 형성방법은 고밀도 플라즈마를 이용해 다층의 적층막과 실리콘 기판을 동시에 식각하여 소자분리막을 형성함으로써 생산성의 향상과 결함의 발생을 억제할 수 있는 효과가 있다.Accordingly, the device isolation film forming method of the semiconductor device of the present invention has the effect of improving the productivity and suppressing the occurrence of defects by forming a device isolation film by simultaneously etching the multilayer film and the silicon substrate using a high density plasma.

고밀도 플라즈마, STIHigh Density Plasma, STI

Description

반도체 소자의 소자분리막 형성방법 {Method for fabricating isolation barrier of semiconductor device} Method for fabricating isolation barrier of semiconductor device             

도 1 내지 도 3은 본 발명에 의한 반도체 소자의 소자분리막 형성방법의 단면도.1 to 3 are cross-sectional views of a device isolation film forming method of a semiconductor device according to the present invention.

본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로, 보다 자세하게는 고밀도 플라즈마를 이용해 다층의 적층막과 실리콘 기판을 동시에 식각하여 소자분리막을 형성함으로써 생산성의 향상과 결함의 발생을 억제할 수 있는 방법에 관한 것이다. The present invention relates to a method for forming a device isolation film of a semiconductor device, and more particularly, to improve the productivity and suppress the occurrence of defects by forming a device isolation film by simultaneously etching a multilayer film and a silicon substrate using a high density plasma. It is about.

종래에는, 일반적으로 반도체 소자를 분리하는 방법으로 선택적으로 질화막을 이용하는 LOCOS(Local Oxidation of Sillicon, 이하 LOCOS) 소자 분리 방법이 이용되어 왔다. LOCOS 소자 분리 방법은 질화막을 마스크로 해서 실리콘 웨이퍼 자체를 열산화시키기 때문에 공정이 간소해서 산화막의 소자 응력 문제가 적고, 생성 되는 산화막질이 좋다는 이점이 있다. 그러나, LOCOS 소자 분리 방법을 이용하면 소자 분리 영역이 크기 때문에 소자의 미세화에 한계가 있을 뿐만 아니라 버즈비크(bird's beak)가 발생하게 된다.Conventionally, a LOCOS (Local Oxidation of Sillicon, LOCOS) device isolation method using a nitride film selectively has been used as a method for separating semiconductor devices. Since the LOCOS device isolation method thermally oxidizes the silicon wafer itself using a nitride film as a mask, the process is simple and there is an advantage that the device stress problem of the oxide film is small, and the resulting oxide film quality is good. However, when the LOCOS device isolation method is used, the device isolation region is large, thereby limiting the miniaturization of the device and generating bird's beak.

상기와 같은 문제점을 극복하기 위해 LOCOS 소자 분리 방법을 대체하는 기술로서 트렌치 소자 분리(Shallow Trench Isolation, 이하 STI)가 있다. 트렌치 소자 분리에서는 실리콘 웨이퍼에 트렌치를 만들어 절연물을 집어넣기 때문에 소자 분리 영역이 차지하는 면적이 작아서 소자의 미세화에 유리하다. 현재 적용되는 STI 공정은 반도체 기판을 건식식각하여 트렌치를 형성한 후 건식식각으로 인한 손상을 큐어링(curing)한 후, 계면특성 및 활성영역과 소자격리 영역의 모서리 라운딩 특성을 향상시키기 위해 트렌치 내부를 열산화하여 산화막을 형성하는 공정을 진행한다. 이 후 산화막이 형성된 트렌치를 메우도록 반도체 기판 전면에 절연막을 두껍게 증착하고 화학적 기계적 연마(Chemical Mechanical Polishing, 이하 CMP)를 진행하여 반도체 기판을 평탄화한다. 그러나, 상기와 같은 종래의 STI 공정은 고집적화된 소자일수록 소자간 간격이 좁아짐과 동시에 트렌치 기울기(Trench Slope)도 거의 직각을 이룰 수 밖에 없다. 따라서 산화막의 갭필(gap-fill)이 이루어지지 않아 보이드(void)가 발생할 수 있는 문제점이 있다. 또한 상기 트렌치를 갭필하는 산화막으로는 갭필 특성과 평탄화 특성이 양호한 O3-TEOS(O3-TetraEthylOrthoSilicate, 이하 O3-TEOS) 상압화학기상증착(Atmospheric Pressure Chemical Vapor Deposition, 이하 APCVD) 산화막, 고밀도 플라즈마 화학기상증착(High Density Plasma Chemical Vapor Deposition) 산화막이 주로 사용되어 오고 있다. In order to overcome the problems described above, as a technique for replacing the LOCOS device isolation method, there is trench trench isolation (hereinafter, STI). In trench device isolation, a trench is formed in a silicon wafer to insulate the insulator, so the area of the device isolation region is small, which is advantageous for miniaturization of the device. Currently applied STI process is to dry the semiconductor substrate to form the trench, and then to cure the damage caused by the dry etching, and then to improve the interface characteristics and the corner rounding characteristics of the active region and the device isolation region inside the trench Is thermally oxidized to form an oxide film. Thereafter, an insulating film is thickly deposited on the entire surface of the semiconductor substrate so as to fill the trench in which the oxide film is formed, and chemical mechanical polishing (CMP) is performed to planarize the semiconductor substrate. However, in the conventional STI process as described above, the spacing between the devices becomes narrower and the trench slopes are almost right at the same time as the integrated devices become higher. Therefore, there is a problem that voids may occur because a gap-fill of the oxide layer is not performed. In addition, the oxide film gap-filling the trench may be O 3 -TEOS (O 3 -TetraEthylOrthoSilicate, hereinafter O 3 -TEOS) Atmospheric Pressure Chemical Vapor Deposition (APCVD) oxide film having high gap fill characteristics and planarization characteristics, and high density plasma. High Density Plasma Chemical Vapor Deposition An oxide film has been mainly used.

그러나 소자의 고집적화가 진행됨에 따라 STI 형성을 위해 여러 단계의 공정을 거치게되므로서 품질의 저하 및 생산성의 저하를 일으키는 문제점이 발생한다.However, as the integration of devices proceeds, several steps are required to form STIs, resulting in a problem of deterioration in quality and productivity.

따라서, 본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 고밀도 플라즈마를 이용해 다층의 적층막과 실리콘 기판을 동시에 식각하여 소자분리막을 형성함으로써 생산성의 향상과 결함의 발생을 억제할 수 있는 방법을 제공함에 본 발명의 목적이 있다.
Accordingly, the present invention is to solve the problems of the prior art as described above, by forming a device isolation film by simultaneously etching a multi-layer laminated film and a silicon substrate using a high-density plasma can improve the productivity and suppress the occurrence of defects It is an object of the present invention to provide a method.

본 발명의 상기 목적은 반도체 기판의 상부에 패드산화막, 질화막, TEOS 산화막, 반사방지막이 각각 소정의 두께를 가지고 순차적으로 적층되어 이루어지는 다층의 적층막을 형성하는 단계; 소자분리막이 형성될 영역을 개방하는 패턴을 형성하여 고밀도 플라즈마를 이용한 식각을 실시하는 단계; 및 상기 다층의 적층막과 실리콘 기판을 동시에 식각하여 소자분리막을 형성하는 단계 로 이루어진 반도체 소자의 소자분리막 형성방법에 의해 달성된다.The above object of the present invention comprises the steps of forming a multi-layer laminated film formed by sequentially depositing a pad oxide film, a nitride film, a TEOS oxide film, an antireflection film each having a predetermined thickness on the semiconductor substrate; Forming a pattern for opening a region in which the device isolation layer is to be formed and performing etching using a high density plasma; And forming a device isolation film by simultaneously etching the multilayer film and the silicon substrate.

본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

먼저, 도 1은 다층의 적층막을 형성하는 단계를 나타내는 단면도이다. 반도체 기판(1)에 SiO2 패드 산화막(2)을 150Å의 두께로 형성하고 Si3N4 질화막(3)을 1500Å의 두께로 형성한다. 이후 TEOS(Tetra-ethoxysilane) 산화막(4)을 1000Å의 두께로 형성하고 그 상부에 반사방지막(5)을 600Å의 두께로 형성한다. 이후 STI 소자분리막이 형성될 영역을 개방하는 포토레지스트(photoresist) 패턴(6)을 형성한다.First, FIG. 1 is sectional drawing which shows the process of forming a multilayer laminated film. The SiO 2 pad oxide film 2 is formed on the semiconductor substrate 1 to a thickness of 150 kPa, and the Si 3 N 4 nitride film 3 is formed to a thickness of 1500 kPa. Thereafter, a TEOS (Tetra-ethoxysilane) oxide film 4 is formed to a thickness of 1000 Å, and an antireflection film 5 is formed to a thickness of 600 상부 on the top. A photoresist pattern 6 is then formed to open the region where the STI device isolation film is to be formed.

다음, 도 2는 상기 패턴을 식각마스크로 하여 다층의 적층막을 식각하는 단계를 나타내는 단면도이다. 이때 식각은 고밀도 플라즈마를 이용하여 실시하며 식각조건은 다음과 같다. 5 내지 15mTorr의 압력에서 Ar/CF4/CH2F2/HBr 혼합가스를 이용해 400 내지 1000W의 바이어스 파워와 500 내지 1000W의 소스 파워를 이용해 실시한다. 또한 혼합가스를 50 내지 200sccm의 Ar, 20 내지 100sccm의 CF4, 20 내지 100sccm의 CH2F2, 10 내지 100sccm의 HBr의 비율로 흘려주면서 식각을 실시하여 반사방지막, TEOS 산화막, 질화막 그리고 패드 산화막을 순차적으로 식각한다.Next, FIG. 2 is a cross-sectional view illustrating a step of etching a multilayer film by using the pattern as an etching mask. At this time, etching is performed using high density plasma, and etching conditions are as follows. The Ar / CF 4 / CH 2 F 2 / HBr mixed gas is used at a pressure of 5 to 15 mTorr using a bias power of 400 to 1000 W and a source power of 500 to 1000 W. In addition, the mixed gas is 50 to 200 sccm Ar, 20 to 100 sccm CF 4 , 20 to 100 sccm CH 2 F 2 , Etching is performed while flowing at a rate of 10 to 100 sccm of HBr to sequentially etch the antireflection film, the TEOS oxide film, the nitride film, and the pad oxide film.

다음, 도 3은 실리콘 기판을 식각하는 단계를 보여주는 단면도이다. 마찬가지로 고밀도 플라즈마를 이용해 동일한 챔버(chamber) 내에서 실시하며 20 내지 40mTorr의 압력에서 500 내지 1000W의 소스 파워와 200 내지 300W의 바이어스 파워 그리고 HBr/Cl2/O2 혼합가스를 이용한다. 이때 상기 혼합가스를 30 내지 100sccm의 HBr, 20 내지 60sccm의 Cl2 그리고 0 내지 10sccm의 O2의 비율로 흘려주면서 식각을 실시하여 실리콘 기판을 소정 깊이만큼 식각한다.3 is a cross-sectional view illustrating a step of etching a silicon substrate. Similarly, high density plasma is used in the same chamber, and a source power of 500 to 1000 W, a bias power of 200 to 300 W, and HBr / Cl 2 / O 2 mixed gas are used at a pressure of 20 to 40 mTorr. At this time, the silicon substrate is etched by a predetermined depth while flowing the mixed gas at a ratio of HBr of 30 to 100 sccm, Cl 2 of 20 to 60 sccm, and O 2 of 0 to 10 sccm.

즉, 동일한 챔버 내에서 플라즈마의 조건만을 간단히 조절해 다층의 적층막과 실리콘 기판을 동시에 식각할 수 있는 특징을 가진다.In other words, it is possible to simultaneously etch the multilayer film and the silicon substrate by simply adjusting the plasma conditions in the same chamber.

이후 단계는 도시되지는 않았지만 형성된 소자분리막에 라이너(liner) 산화막을 형성하고 절연막을 갭필(gap-fill)하여 소자분리막을 완성한다.Although not shown in the drawing, a liner oxide film is formed on the formed device isolation film, and the device isolation film is gap-filled to complete the device isolation film.

상세히 설명된 본 발명에 의하여 본 발명의 특징부를 포함하는 변화들 및 변형들이 당해 기술 분야에서 숙련된 보통의 사람들에게 명백히 쉬워질 것임이 자명하다. 본 발명의 그러한 변형들의 범위는 본 발명의 특징부를 포함하는 당해 기술 분야에 숙련된 통상의 지식을 가진 자들의 범위 내에 있으며, 그러한 변형들은 본 발명의 청구항의 범위 내에 있는 것으로 간주된다.It will be apparent that changes and modifications incorporating features of the invention will be readily apparent to those skilled in the art by the invention described in detail. It is intended that the scope of such modifications of the invention be within the scope of those of ordinary skill in the art including the features of the invention, and such modifications are considered to be within the scope of the claims of the invention.

따라서, 본 발명의 반도체 소자의 소자분리막 형성방법은 고밀도 플라즈마를 이용해 다층의 적층막과 실리콘 기판을 동시에 식각하여 소자분리막을 형성함으로써 생산성의 향상과 결함의 발생을 억제할 수 있는 효과가 있다.
Accordingly, the device isolation film forming method of the semiconductor device of the present invention has the effect of improving the productivity and suppressing the occurrence of defects by forming a device isolation film by simultaneously etching the multilayer film and the silicon substrate using a high density plasma.

Claims (10)

반도체 소자의 소자분리막 형성방법에 있어서,In the device isolation film forming method of a semiconductor device, 반도체 기판의 상부에 패드산화막, 질화막, TEOS 산화막, 반사방지막이 각각 소정의 두께를 가지고 순차적으로 적층되어 이루어지는 다층의 적층막을 형성하는 단계; Forming a multi-layered laminated film in which a pad oxide film, a nitride film, a TEOS oxide film, and an antireflection film are sequentially stacked on the semiconductor substrate, each having a predetermined thickness; 소자분리막이 형성될 영역을 개방하는 패턴을 형성하여 고밀도 플라즈마를 이용한 식각을 실시하는 단계; 및 Forming a pattern for opening a region in which the device isolation layer is to be formed and performing etching using a high density plasma; And 상기 다층의 적층막과 실리콘 기판을 동시에 식각하여 소자분리막을 형성하는 단계 Simultaneously etching the multilayer stack and the silicon substrate to form an isolation layer 를 포함하여 이루어짐을 특징으로 하는 반도체 소자의 소자분리막 형성방법.Device isolation film forming method of a semiconductor device, characterized in that comprises a. 삭제delete 제 1항에 있어서,The method of claim 1, 상기 식각은 실리콘 기판의 상부에 형성된 다층의 적층막을 식각하고 동시에 플라즈마의 조건을 변경하여 동일한 챔버 내에서 실리콘 기판을 식각함을 특징으로 하는 반도체 소자의 소자분리막 형성방법.The etching method of forming a device isolation film of a semiconductor device, characterized in that the etching of the multilayer film formed on top of the silicon substrate and at the same time changing the conditions of the plasma etching the silicon substrate in the same chamber. 제 3항에 있어서,The method of claim 3, wherein 상기 다층의 적층막을 식각하는 단계는 5 내지 15mTorr의 압력에서 Ar/CF4/CH2F2/HBr 혼합가스를 이용해 400 내지 1000W의 바이어스 파워와 500 내지 1000W의 소스 파워를 이용해 실시함을 특징으로 하는 반도체 소자의 소자분리막 형성방법.The etching of the multilayer film is performed using a bias power of 400 to 1000 W and a source power of 500 to 1000 W using an Ar / CF 4 / CH 2 F 2 / HBr mixed gas at a pressure of 5 to 15 mTorr. A device isolation film forming method of a semiconductor device. 제 4항에 있어서,The method of claim 4, wherein 상기 Ar/CF4/CH2F2/HBr 혼합가스는 50 내지 200sccm의 Ar, 20 내지 100sccm의 CF4, 20 내지 100sccm의 CH2F2, 10 내지 100sccm의 HBr의 비율로 혼합됨을 특징으로 하는 반도체 소자의 소자분리막 형성방법.The Ar / CF 4 / CH 2 F 2 / HBr mixed gas is 50 to 200sccm Ar, 20 to 100sccm CF 4 , 20 to 100sccm CH 2 F 2 , Method for forming a device isolation film of a semiconductor device, characterized in that the mixture at a ratio of HBr of 10 to 100sccm. 제 3항에 있어서,The method of claim 3, wherein 상기 실리콘 기판을 식각하는 단계는 20 내지 40mTorr의 압력에서 500 내지 1000W의 소스 파워와 200 내지 300W의 바이어스 파워 그리고 HBr/Cl2/O2 혼합가스를 이용해 실시함을 특징으로 하는 반도체 소자의 소자분리막 형성방법.The etching of the silicon substrate is performed using a source power of 500 to 1000 W, a bias power of 200 to 300 W, and a HBr / Cl 2 / O 2 mixed gas at a pressure of 20 to 40 mTorr. Formation method. 제 6항에 있어서,The method of claim 6, 상기 HBr/Cl2/O2 혼합가스는 30 내지 100sccm의 HBR, 20 내지 60sccm의 Cl2 그리고 0 내지 10sccm의 O2의 비율로 혼합됨을 특징으로 하는 반도체 소자의 소자분리막 형성방법.Wherein the HBr / Cl 2 / O 2 mixed gas is mixed at a ratio of HBR of 30 to 100 sccm, Cl 2 of 20 to 60 sccm, and O 2 of 0 to 10 sccm. 삭제delete 삭제delete 삭제delete
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