KR20020017796A - A method for fabricating semiconductor device - Google Patents
A method for fabricating semiconductor device Download PDFInfo
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- KR20020017796A KR20020017796A KR1020000051310A KR20000051310A KR20020017796A KR 20020017796 A KR20020017796 A KR 20020017796A KR 1020000051310 A KR1020000051310 A KR 1020000051310A KR 20000051310 A KR20000051310 A KR 20000051310A KR 20020017796 A KR20020017796 A KR 20020017796A
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- 238000000034 method Methods 0.000 title claims abstract description 44
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 150000004767 nitrides Chemical class 0.000 claims abstract description 38
- 125000006850 spacer group Chemical group 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 23
- 230000002093 peripheral effect Effects 0.000 claims abstract description 16
- 230000004888 barrier function Effects 0.000 claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 239000012212 insulator Substances 0.000 abstract 3
- 238000002513 implantation Methods 0.000 abstract 1
- 230000008569 process Effects 0.000 description 36
- 239000010410 layer Substances 0.000 description 11
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02551—Group 12/16 materials
- H01L21/02554—Oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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Abstract
Description
본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자 제조 공정 중 층간절연막 및 콘택 형성 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to an interlayer insulating film and a contact forming process in a semiconductor device manufacturing process.
반도체 소자의 고집적화에 따라 패턴 및 패턴 간극이 미세화되고 있으며, 이에 따라 공정 마진이 줄어들고 있다. 특히 비트라인 콘택이나 전하저장전극 콘택 형성시 공정 마진이 크게 감소되어 수율 저하의 주된 요인이 되었다.Patterns and pattern gaps are miniaturized with high integration of semiconductor devices, thereby reducing process margins. In particular, the process margin is greatly reduced when forming bit line contacts or charge storage electrode contacts, which is a major factor in yield reduction.
이러한 비트라인 콘택 또는 전하저장전극 콘택 형성시 공정 마진을 증가시키기 위하여 자기정렬콘택(SAC) 공정이 도입되어 사용되고 있으며, 최근에는 일종의 콘택 패드인 랜딩 플러그 콘택(landing plug contact)을 비트라인 콘택 및 전하저장전극 콘택 영역에 동시에 형성하여 콘택 공정의 공정 마진을 더욱 증가시키고 있다.In order to increase the process margin when forming the bit line contact or the charge storage electrode contact, a self-aligned contact (SAC) process is introduced and used. Recently, a landing plug contact, which is a kind of contact pad, is used as a bit line contact and a charge. The process margin of the contact process is further increased by simultaneously forming the storage electrode contact region.
첨부된 도면 도 1a 내지 도 1f는 종래기술에 따른 DRAM 제조 공정을 도시한 것으로, 이하 이를 참조하여 종래기술을 살펴본다.1A to 1F illustrate a DRAM manufacturing process according to the prior art, and the prior art will be described with reference to the following.
종래기술에 따르면, 우선 도 1a에 도시된 바와 같이 실리콘 기판(10)에 대해 소자분리 공정 및 게이트 산화 공정을 통해 소자분리막(도시되지 않음) 및 게이트 산화막(도시되지 않음)을 형성하고, 전체 구조 상부에 폴리실리콘막(11) 및 마스크 질화막(12)을 차례로 증착한 다음, 워드라인(게이트 전극) 마스크를 사용한 마스크 공정 및 식각 공정을 통해 워드라인을 패터닝한다.According to the prior art, first, a device isolation film (not shown) and a gate oxide film (not shown) are formed on the silicon substrate 10 through the device isolation process and the gate oxidation process, as shown in FIG. The polysilicon layer 11 and the mask nitride layer 12 are sequentially deposited on the upper portion, and then the word line is patterned through a mask process and an etching process using a word line (gate electrode) mask.
다음으로, 도 1b에 도시된 바와 같이 전체 구조 표면을 따라 질화막을 증착하고 이를 비등방성 건식 식각하여 워드라인(게이트 전극) 측벽에 질화막 스페이서(13)를 형성한다.Next, as illustrated in FIG. 1B, a nitride film is deposited along the entire structure surface and anisotropic dry etching is performed to form the nitride spacer 13 on the sidewall of the word line (gate electrode).
이어서, 도 1c에 도시된 바와 같이 전체 구조 표면을 따라 자기정렬 콘택 식각을 위한 베리어 질화막(14)을 증착한다.Subsequently, a barrier nitride film 14 for self-aligned contact etching is deposited along the entire structure surface as shown in FIG. 1C.
계속하여, 도 1d에 도시된 바와 같이 전체 구조 표면을 따라 산화막(15)을증착하고, 주변회로 영역의 산화막(15)을 선택적으로 비등방성 건식 식각하여 산화막 스페이서(15a)를 형성하고, 주변회로 영역에 이온주입 공정을 실시한다. 이때, 주변회로 영역에서는 베리어 질화막(14)이 식각되어 실리콘 기판(10)이 노출된 상태이다.Subsequently, as illustrated in FIG. 1D, the oxide film 15 is deposited along the entire structure surface, and the oxide film 15 in the peripheral circuit region is selectively anisotropically dry-etched to form the oxide spacer 15a. An ion implantation process is performed in the region. At this time, in the peripheral circuit region, the barrier nitride layer 14 is etched to expose the silicon substrate 10.
다음으로, 도 1e에 도시된 바와 같이 산화막(15) 및 산화막 스페이서(15a)를 제거하고, 전체 구조 표면을 따라 IPO(interpoly oxide)막(16)을 증착하고, 그 상부에 BPSG(borophospho silicate glass)막(17)을 증착하고 BPSG 플로우 및 CMP 공정을 통해 평탄화를 이룬다. 이때, IPO막(16)은 절연 작용과 함께 BPSG막(17)로부터 하부 구조로 불순물이 확산하는 것을 방지하기 위한 것이며, 주로 저압화학기상증착법을 사용하여 증착한다.Next, as illustrated in FIG. 1E, the oxide film 15 and the oxide spacer 15a are removed, an IPO (interpoly oxide) film 16 is deposited along the entire structure surface, and borophospho silicate glass is formed thereon. The film 17 is deposited and planarized through a BPSG flow and a CMP process. At this time, the IPO film 16 is to prevent the diffusion of impurities from the BPSG film 17 to the underlying structure with an insulating action, and is mainly deposited using a low pressure chemical vapor deposition method.
계속하여, 도 1f에 도시된 바와 같이 랜딩 플러그 콘택 형성을 위한 자기정렬 콘택 마스크 공정 및 식각 공정을 통해 콘택을 오픈시킨다. 앞에서 이온주입 공정은 그 설명을 생략하였다.Subsequently, as shown in FIG. 1F, the contact is opened through a self-aligned contact mask process and an etching process for forming a landing plug contact. The ion implantation process has been omitted above.
그런데, 상기와 같은 종래기술에 따른 공정을 진행함에 있어서 두 가지 문제점이 나타난다. 그 첫째는 IPO막(16) 증착 후 셀 영역의 워드라인 사이의 간극이 좁아져 BPSG막(17) 증착시 갭필 특성이 저하되는 문제점이며, 그 두번째는 랜딩 플러그 콘택 형성을 위한 자기정렬 콘택 식각 공정시 워드라인 상부 및 질화막 스페이서(13)의 손실이 발생하여 단락의 우려가 있다는 것이다. 미설명 도면 부호 'A'는 콘택 식각에 의해 워드라인이 노출된 상태를 나타낸 것이다.By the way, two problems appear in the process according to the prior art as described above. The first problem is that the gap between the word lines of the cell region after the deposition of the IPO film 16 is narrowed, so that the gap fill property is degraded when the BPSG film 17 is deposited. The second is a self-aligned contact etching process for forming a landing plug contact. The loss of the upper word line and the nitride film spacer 13 may occur, resulting in a short circuit. Unexplained reference numeral 'A' indicates a state where the word line is exposed by contact etching.
상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 본 발명은, 워드라인(게이트 전극) 간극을 매립하는 평탄화 절연막의 갭필 특성을 향상시키고, 랜딩 플러그 콘택 형성을 위한 자기정렬 콘택 식각 공정시 질화막 스페이서의 손실을 보상할 수 있는 반도체 소자 제조방법을 제공하는데 그 목적이 있다.The present invention proposed to solve the above problems of the prior art, the nitride film spacer during the self-aligned contact etching process for improving the gap-fill characteristics of the planarization insulating film filling the gap between the word line (gate electrode), forming the landing plug contact It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of compensating for the loss.
도 1a 내지 도 1f는 종래기술에 따른 DRAM 제조 공정도.1A-1F show a DRAM manufacturing process according to the prior art.
도 2a 내지 도 2f는 본 발명의 일 실시예에 따른 DRAM 제조 공정도.2A-2F illustrate a DRAM manufacturing process in accordance with one embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
20 : 실리콘 기판 21 : 폴리실리콘막20 silicon substrate 21 polysilicon film
22 : 마스크 질화막 23 : 질화막22 mask nitride film 23 nitride film
23a : 질화막 스페이서 24 : 산화막 스페이서23a: nitride film spacer 24: oxide film spacer
25 : 베리어 질화막 26 : BPSG막25: barrier nitride film 26: BPSG film
상기의 기술적 과제를 달성하기 위한 본 발명의 특징적인 반도체 소자 제조방법은, 소정의 하부 공정을 마친 반도체 기판 상에 마스크 절연막을 구비한 게이트 전극을 형성하는 제1 단계; 상기 제1 단계를 마친 전체 구조 표면을 따라 질화막을 증착하는 제2 단계; 주변회로 영역의 상기 질화막을 비등방성 식각하여 상기 주변회로 영역의 상기 게이트 전극 측벽에 질화막 스페이서를 형성하는 제3 단계; 상기 제3 단계 수행 후, 적어도 상기 주변회로 영역의 상기 게이트 전극 측벽에 산화막 스페이서를 형성하는 제4 단계; 상기 산화막 스페이서를 사용하여 소오스/드레인 형성을 위한 불순물 이온주입을 실시하는 제5 단계; 상기 산화막 스페이서를 제거하는 제6 단계; 상기 제6 단계를 마친 전체 구조 표면을 따라 베리어 질화막을 형성하는 제7 단계; 상기 제7 단계를 마친 전체 구조 상부에 상기 게이트 전극 사이의 간극을 매립하는 평탄화 절연막을 형성하는 제8 단계; 및 랜딩 플러그 콘택 영역의 상기 평탄화 절연막 및 상기 베리어 질화막을 자기정렬 방식으로 식각하여 콘택홀을 형성하는 제9 단계를 포함하여 이루어진다.A characteristic semiconductor device manufacturing method of the present invention for achieving the above technical problem, the first step of forming a gate electrode having a mask insulating film on a semiconductor substrate after a predetermined lower step; Depositing a nitride film along the entire structure surface of the first step; Anisotropically etching the nitride film of the peripheral circuit region to form a nitride spacer on the sidewall of the gate electrode of the peripheral circuit region; A fourth step of forming an oxide spacer on at least sidewalls of the gate electrode of the peripheral circuit region after performing the third step; A fifth step of implanting impurity ions to form a source / drain using the oxide spacer; A sixth step of removing the oxide spacer; A seventh step of forming a barrier nitride film along the entire structure surface of the sixth step; An eighth step of forming a planarization insulating layer filling the gap between the gate electrodes on the entire structure of the seventh step; And a ninth step of forming a contact hole by etching the planarization insulating layer and the barrier nitride layer of the landing plug contact region in a self-aligning manner.
바람직하게, 상기 제4 단계는, 상기 제3 단계를 마친 전체 구조 표면을 따라 산화막을 형성하는 제10 단계와, 상기 산화막을 전면 비등방성 식각하여 상기 산화막 스페이서를 형성하는 제11 단계를 포함하여 이루어진다.Preferably, the fourth step includes a tenth step of forming an oxide film along the entire structure surface of the third step, and an eleventh step of forming the oxide spacer by anisotropically etching the oxide film. .
바람직하게, 상기 제4 단계는, 상기 제3 단계를 마친 전체 구조 표면을 따라 산화막을 형성하는 제10 단계; 상기 셀 영역을 덮는 포토레지스트 패턴을 형성하는 제11 단계; 상기 주변회로 영역의 상기 산화막을 비등방성 식각하여 상기 산화막 스페이서를 형성하는 제12 단계; 및 상기 포토레지스트 패턴을 제거하는 제13 단계를 포함하여 이루어진다.Preferably, the fourth step may include: a tenth step of forming an oxide film along the entire structure surface of the third step; An eleventh step of forming a photoresist pattern covering the cell region; Forming an oxide spacer by anisotropically etching the oxide layer in the peripheral circuit region; And a thirteenth step of removing the photoresist pattern.
바람직하게, 상기 마스크 절연막은 질화막 또는 질화막/버퍼산화막으로 이루어진다.Preferably, the mask insulating film is formed of a nitride film or a nitride film / buffer oxide film.
바람직하게, 상기 평탄화 절연막은 BPSG막이다.Preferably, the planarization insulating film is a BPSG film.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
첨부된 도면 도 2a 내지 도 2f는 본 발명의 일 실시예에 따른 DRAM 제조 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.2A to 2F illustrate a DRAM manufacturing process according to an embodiment of the present invention, which will be described below with reference to the drawings.
본 실시예에 따르면 우선 도 2a에 도시된 바와 같이 실리콘 기판(20)에 대해 소자분리 공정 및 게이트 산화 공정을 통해 소자분리막(도시되지 않음) 및 게이트 산화막(도시되지 않음)을 형성하고, 전체 구조 상부에 폴리실리콘막(11) 및 마스크질화막(12)을 차례로 증착한 다음, 워드라인(게이트 전극) 마스크를 사용한 마스크 공정 및 식각 공정을 통해 워드라인(게이트 전극)을 패터닝한다. 이때, 마스크 질화막(12)는 플라즈마 화학기상증착법(PECVD), 저압 화학기상증착법(LPCVD), 상압 화학기상증착법(APCVD) 중 하나를 사용하여 400∼800℃의 온도에서 1000∼4000Å 두께로 증착하며, 질화막의 스트레스에 의한 리프팅 현상을 방지하기 위하여 100∼1000Å 두께의 버퍼 산화막(PE-TEOS 또는 PE-USG)을 추가적으로 증착할 수도 있다.According to the present embodiment, first, as shown in FIG. 2A, a device isolation film (not shown) and a gate oxide film (not shown) are formed through a device isolation process and a gate oxidation process with respect to the silicon substrate 20, and the overall structure. The polysilicon layer 11 and the mask nitride layer 12 are sequentially deposited on the upper portion, and then the word line (gate electrode) is patterned through a mask process and an etching process using a word line (gate electrode) mask. At this time, the mask nitride film 12 is deposited to a thickness of 1000 to 4000Å by using a plasma chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD) at a temperature of 400 ~ 800 ℃. In order to prevent the lifting phenomenon caused by the stress of the nitride film, a buffer oxide film (PE-TEOS or PE-USG) having a thickness of 100 to 1000 Å may be additionally deposited.
다음으로, 도 2b에 도시된 바와 같이 전체 구조 표면을 따라 질화막(23)을 증착하고, 주변회로 영역의 질화막(23)을 선택적으로 비등방성 건식 식각하여 게이트 전극 측벽에 질화막 스페이서(23a)를 형성한다. 즉, 셀 영역을 포토레지스트 등으로 덮은 상태에서 비등방성 건식 식각 공정을 실시한다. 종래에는 전면 식각 공정을 수행하였다. 질화막(23)은 PECVD, LPCVD, APCVD 중 하나를 사용하여 100∼1000Å 두께로 증착한다.Next, as illustrated in FIG. 2B, the nitride film 23 is deposited along the entire structure surface, and the nitride film 23 in the peripheral circuit region is selectively anisotropically dry etched to form the nitride film spacer 23a on the sidewall of the gate electrode. do. That is, an anisotropic dry etching process is performed while the cell region is covered with a photoresist or the like. Conventionally, a full surface etching process was performed. The nitride film 23 is deposited to a thickness of 100 to 1000 mW using one of PECVD, LPCVD, and APCVD.
이어서, 도 2c에 도시된 바와 같이 PECVD, LPCVD 등의 증착 방식으로 전체 구조 표면을 따라 100∼1000Å 두께로 산화막을 증착하고 이를 비등방성 건식 식각하여 산화막 스페이서(24)를 형성한다. 산화막 스페이서(24)는 셀 영역과 주변회로 영역 모두에 형성되며, 주변회로 영역의 트랜지스터의 단채널 효과를 감소시키기 위한 것이다. 따라서, 셀 영역에는 형성시키지 않아도 무관하며, 이를 위해서 셀 영역을 덮는 포토레지스트 패턴을 사용하여 주변회로 영역에만 산화막 스페이서(24)를 형성할 수도 있다.Subsequently, as illustrated in FIG. 2C, an oxide film is deposited to have a thickness of 100 to 1000 μm along the entire structure surface by a deposition method such as PECVD or LPCVD, and anisotropic dry etching is performed to form an oxide film spacer 24. The oxide film spacer 24 is formed in both the cell region and the peripheral circuit region, and is intended to reduce the short channel effect of the transistor in the peripheral circuit region. Accordingly, the oxide film spacer 24 may be formed only in the peripheral circuit region by using a photoresist pattern covering the cell region.
다음으로, 산화막 스페이서(24)를 사용하여 이온주입 공정을 실시하고 나면, 도 2d에 도시된 바와 같이 세정 공정을 실시하여 산화막 스페이서(24)를 제거하고, 전체 구조 표면을 따라 자기정렬 콘택 식각을 위한 베리어 질화막(25)을 증착한다. 이때, 베리어 질화막(25)은 PECVD, LPCVD 등의 증착 방식으로 100∼500Å 두께로 증착한다.Next, after the ion implantation process is performed using the oxide spacer 24, a cleaning process is performed to remove the oxide spacer 24 as shown in FIG. 2D, and self-aligned contact etching is performed along the entire structure surface. The barrier nitride film 25 is deposited. At this time, the barrier nitride film 25 is deposited to a thickness of 100 to 500 kPa by a deposition method such as PECVD or LPCVD.
계속하여, 도 2e에 도시된 바와 같이 전체 구조 상부에 BPSG막(26)을 증착하고, BPSG 플로우 및 CMP 공정을 통해 평탄화를 이룬다. 이때, BPSG막(26) 내의 B/P 농도는 각각 3.5∼5.0wt%로 하고, BPSG 플로우 온도는 700∼1000℃로 하며, 플로우를 위한 열처리 시간은 퍼니스 어닐의 경우 10∼90분, 급속열처리의 경우 5∼60초로 한다.Subsequently, as illustrated in FIG. 2E, the BPSG film 26 is deposited on the entire structure, and planarized through the BPSG flow and the CMP process. At this time, the B / P concentration in the BPSG film 26 is 3.5 to 5.0 wt%, the BPSG flow temperature is 700 to 1000 ° C, and the heat treatment time for the flow is 10 to 90 minutes for the furnace annealing and rapid heat treatment. In the case of 5 to 60 seconds.
이어서, 도 2f에 도시된 바와 같이 랜딩 플러그 콘택 형성을 위한 자기정렬 콘택 마스크 공정 및 자기정렬 콘택 식각 공정을 통해 콘택을 오픈시킨다. 도면 부호 'B'는 워드라인이 보호되고 있음을 나타내고 있다.Next, as shown in FIG. 2F, the contact is opened through a self-aligned contact mask process and a self-aligned contact etching process for forming a landing plug contact. Reference numeral 'B' indicates that the word line is protected.
상기의 공정에서 이온주입 공정은 기존과 크게 다르지 않기 때문에 자세히 설명하지 않았다.The ion implantation process in the above process is not described in detail because it is not very different from the existing.
상기와 같은 공정을 실시하는 경우, 워드라인 사이의 간극이 기존의 IPO막 두께 이상으로 넓어진 상태에서 평탄화 절연막인 BPSG막(26) 증착을 실시하기 때문에 BPSG막(26)의 갭필 특성을 향상시킬 수 있다. 또한, 셀 영역의 질화막(23)에 대한 스페이서 식각을 실시하지 않았기 때문에 자기정렬 콘택 식각 공정시 질화막의 손실을 어느 정도 보상해 줄 수 있다. 한편, 같은 이유로 IPO막 증착 공정을 생략할 수 있기 때문에 공정 단순화 측면에서도 유리하다.In the above process, the gap fill characteristics of the BPSG film 26 can be improved since the deposition of the BPSG film 26, which is a planarization insulating film, is performed while the gap between the word lines is wider than the conventional IPO film thickness. have. In addition, since spacer etching is not performed on the nitride layer 23 in the cell region, the loss of the nitride layer may be compensated to some extent during the self-aligned contact etching process. On the other hand, since the IPO film deposition process can be omitted for the same reason, it is advantageous in terms of process simplification.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
예컨대, 전술한 실시예에서는 마스크 절연막으로 질화막을 사용하는 경우를 일례로 들어 설명하였으나, 본 발명은 마스크 절연막으로 산화막만을 사용하는 경우에도 적용할 수 있다.For example, in the above-described embodiment, the case where the nitride film is used as the mask insulating film has been described as an example, but the present invention can be applied to the case where only the oxide film is used as the mask insulating film.
전술한 본 발명은 평탄화 절연막의 갭필 특성을 확보하여 소자의 전기적 특성을 개선하는 효과가 있으며, 자기정렬 콘택 식각 공정시 질화막 스페이서 및 워드라인의 손실을 방지하여 소자의 페일을 줄이는 효과를 기대할 수 있다.The present invention has the effect of improving the electrical characteristics of the device by securing the gap fill characteristics of the planarization insulating film, it can be expected to reduce the device failure by preventing the loss of the nitride spacer and word line during the self-aligned contact etching process. .
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100717812B1 (en) * | 2005-02-28 | 2007-05-11 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
| KR100853477B1 (en) * | 2002-07-19 | 2008-08-21 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| US7436017B2 (en) | 2003-02-06 | 2008-10-14 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit using a selective disposable spacer |
| KR100924005B1 (en) * | 2002-12-26 | 2009-10-28 | 주식회사 하이닉스반도체 | Method for fabrication of semiconductor device with landing plug |
| KR101031459B1 (en) * | 2003-12-24 | 2011-04-26 | 주식회사 하이닉스반도체 | Method for manufacturing a semiconductor device |
-
2000
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100853477B1 (en) * | 2002-07-19 | 2008-08-21 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| KR100924005B1 (en) * | 2002-12-26 | 2009-10-28 | 주식회사 하이닉스반도체 | Method for fabrication of semiconductor device with landing plug |
| US7436017B2 (en) | 2003-02-06 | 2008-10-14 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit using a selective disposable spacer |
| US7588979B2 (en) | 2003-02-06 | 2009-09-15 | Samsung Electronics Co., Ltd. | Method of manufacturing a semiconductor integrated circuit using a selective disposable spacer technique and semiconductor integrated circuit manufactured thereby |
| US8222684B2 (en) | 2003-02-06 | 2012-07-17 | Samsung Electronics Co., Ltd. | Method of manufacturing a semiconductor integrated circuit using a selective disposal spacer technique and semiconductor integrated circuit manufactured thereby |
| KR101031459B1 (en) * | 2003-12-24 | 2011-04-26 | 주식회사 하이닉스반도체 | Method for manufacturing a semiconductor device |
| KR100717812B1 (en) * | 2005-02-28 | 2007-05-11 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
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