KR20020018279A - Method of manufacturing Memory Merged Logic semiconductor device having dual gate structure - Google Patents

Abstract

PURPOSE: A method for forming a memory-merged-with-logic(MML) of a dual gate structure wherein a gate structure is different in a memory region and a logic region is provided to prevent polysilicon from being left in an etch process, by forming a hard mask layer of a concave or convex stripe type having an inclined surface on the interface between the memory region and the logic region. CONSTITUTION: The memory region and the logic region are defined in a semiconductor substrate having a gate oxide layer. A polysilicon layer(201) is formed on the gate oxide layer. A predetermined thickness of the polysilicon layer in the memory region is etched to form a step between the memory region and the logic region while the stepped surface is inclined. A silicide layer(203) is formed on the polysilicon layer. The silicide layer in the logic region is etched to expose the polysilicon layer while the side surface of the remaining silicide layer is inclined. A hard mask layer pattern defining a predetermined gate electrode pattern is formed on the remaining silicide layer and the exposed polysilicon layer. The silicide layer and the polysilicon layer are anisotropically etched to form a gate electrode pattern(206) in the memory region and the logic region.

Description

Method of manufacturing memory Merged Logic semiconductor device having dual gate structure having different gate structures of memory region and logic region

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a method of manufacturing a memory Merged with Logic (MML) semiconductor device having a polyside gate electrode in a memory region and a salicyled gate electrode in a logic region. It is about.

Recently, the necessity of System On Chip has increased due to high integration of semiconductor devices, ultra miniaturization of various material patterns formed in semiconductor devices, high performance of semiconductor devices, large diameters of wafers, and various product demands of consumers. . Accordingly, a merged semiconductor device in which a memory circuit and a logic circuit are combined in one chip, such as an MML semiconductor device, has been proposed.

In the manufacture of the MML semiconductor device, in particular, the improvement of the integration degree of the memory circuit and the high performance of the logic circuit (for example, the improvement of the operation speed) are an important problem. Accordingly, in recent years, self-aligned contact processes, which are employed to improve the degree of integration of devices in the field of manufacturing semiconductor memory devices, and device characteristics such as operating speed of devices in the field of manufacturing logic devices. Many attempts have been made to fabricate MML semiconductor devices in a dual gate structure by organically combining salicide (salicide, self-aligned silicide) processes.

In particular, patent application 00-29302 discloses a process for fabricating an MML semiconductor device by simultaneously patterning a polyside (double layer of silicide / polysilicon) gate electrode and a salicided NMOS and PMOS gate electrode in a single etching process. have. 1 to 4 briefly illustrate a method of manufacturing a conventional MML semiconductor device based on the contents disclosed in the above application.

Referring to FIG. 1, a gate oxide layer (not shown) and a polysilicon layer 101, which is a gate conductive layer, are formed on a semiconductor substrate 100 in which a memory region M and a logic region L are defined. Subsequently, the photoresist pattern 102 is formed in the logic region by performing a photo process, and the polysilicon layer 101 of the memory region is etched by a predetermined thickness using the photoresist pattern 102 as an etching mask.

Referring to FIG. 2A, the photoresist pattern 102 is removed and the silicide layer 103 is formed on the entire surface of the semiconductor substrate. Subsequently, the photoresist pattern 104 is formed on the silicide layer 103 of the memory region, and the silicide layer 103 of the logic region is removed by anisotropic dry etching using the etching mask as an etching mask.

Referring to FIG. 3A, the photoresist pattern 104 is removed and a hard mask layer 105 is deposited on the entire surface of the substrate including the polysilicon layer 101 and the silicide layer 103.

Referring to FIG. 4, a photoresist pattern (not shown) defining a gate electrode pattern 106 is formed on the hard mask film 105, and the hard mask film 105 / polyside films 103 and 101 are formed. Alternatively, the gate electrode pattern 106 composed of the hard mask film 105 / polysilicon film 101 is formed.

By performing such a process, an MML semiconductor device having dual gate electrodes having different gate structures of a memory region and a logic region may be formed.

However, in the above method, as shown in FIG. 4, in the process of forming the gate electrode pattern, there is a problem in that the residual polysilicon 109 exists at the boundary portion 110 between the memory region and the logic region. The residual polysilicon 109 electrically connects the different gate electrodes, resulting in malfunction of the transistor.

The problem occurs during the etching process of the silicide layer 103. Looking at this in detail. When the photoresist pattern 104 for etching the silicide layer 103 of the logic region L is formed, misalignment between the photoresist pattern 104 and the boundary portion 110 of the memory region / logic region cannot be avoided. 2A and 2B show opposite examples in which the photoresist pattern 104 is misaligned, respectively.

2A illustrates a case in which the photoresist pattern 104 is formed to be biased toward the logic region L from the boundary 110, and FIG. 2B illustrates a case in which the photoresist pattern 104 is formed to be biased toward the memory region M. Referring to FIG. In each case, after the silicide film 103 is etched and the hard mask film 105 is formed, the hard mask film 105 of the boundary portion 110 is convex, as shown in FIGS. 3A and 3B. Or dents.

The hard mask layer 105 formed as described above has a thickness greater than that of the memory region and the logic region in the vicinity of the boundary portion 110, so that the etching depth (in the vicinity of the boundary region 110 of the memory region and the logic region during gate electrode patterning) and d _1, d ₂ of Figure 3a is increased) in FIG. 3b. Accordingly, the polysilicon 109 on the semiconductor substrate remains along the thick portion of the hard mask layer 105, causing shortening between the gate electrodes after the gate electrode pattern 106 is formed.

SUMMARY OF THE INVENTION The present invention provides a method of manufacturing an MML semiconductor device having a dual gate structure having a different gate structure between a memory region and a logic region, wherein the polysilicon is formed at a boundary between the memory region and the logic region in a gate electrode pattern forming step. It is an object of the present invention to provide a method for manufacturing an MML semiconductor device capable of preventing an electrical short due to residuals.

1 to 4 are perspective views illustrating a method of manufacturing an MML semiconductor device according to the prior art.

5 to 8 are perspective views illustrating a method of forming the gate electrode pattern according to the first embodiment of the present invention.

9 to 13 are cross-sectional views illustrating a method of manufacturing an MML semiconductor device according to Example 1 of the present invention.

14 is a perspective view illustrating a method of forming a gate electrode pattern according to a second embodiment of the present invention.

15 and 16 are cross-sectional views illustrating a method of manufacturing an MML semiconductor device according to a second embodiment of the present invention.

According to an aspect of the present invention, there is provided a semiconductor substrate having a memory region and a logic region defined therein and having a gate oxide on a surface thereof, forming a polysilicon layer on the gate oxide layer, and polysilicon of the memory region. Etching the film by a predetermined thickness to give a step to the thickness of the polysilicon film of the memory region and the logic region and to form a stepped surface, forming a silicide film on the polysilicon film, etching the silicide film of the logic region to Exposing a silicon film and simultaneously inclining a side surface of the remaining silicide film, forming a hard mask pattern defining a predetermined gate electrode pattern on the remaining silicide film and the exposed polysilicon film, and the hard mask pattern. As an etch mask A method of manufacturing an MML semiconductor device having a dual gate structure includes forming a memory region and a logic region gate electrode pattern by removing anisotropic etching of the silicide layer and the polysilicon layer.

In order to fabricate a dual gate structure MML semiconductor device having a polyside gate electrode in a memory region and a salicided gate electrode in a logic region, after the anisotropic etching step using the hard mask pattern as an etching mask, the logic region Removing the hard mask pattern and forming a spacer on sidewalls of the gate electrode pattern of the memory region and the logic region, and ion-implanting a predetermined region of the semiconductor substrate using the spacer as an ion implantation mask to form a source / drain region And salifying the polysilicon layer of the logic region gate electrode pattern and the source / drain regions of the logic region.

According to one embodiment of the present invention, the step of forming the stepped surface inclined may be made of an isotropic dry etching method or a gradient etching method. In addition, the step of forming the side surface of the silicide film inclined may be made of an isotropic dry etching method or a gradient etching method.

The present invention also provides a semiconductor substrate having a memory region and a logic region defined and having a gate oxide on a surface thereof, wherein the memory region of the semiconductor substrate includes a silicide / polysilicon / hard mask layer. Forming a triple layer, and forming a double layer of a polysilicon film / hard mask film in a logic region, and patterning the hard mask layer, the silicide layer, and the polysilicon layer to form a gate electrode pattern, wherein a boundary between the memory region and the logic region is formed. Removing the memory region from the logic region gate electrode pattern by forming the interlayer insulating layer on the entire surface of the semiconductor substrate on which the gate electrode pattern is formed; and etching the semiconductor substrate on which the interlayer insulating layer is formed. Cone Exposing Region Electrode Pattern It provides the steps and methods of making MML semiconductor device of the dual-gate structure including a step of forming a contact plug by filling the contact hole to form the hole.

In order to fabricate a dual gate structure MML semiconductor device having a polyside gate electrode in a memory region and a salicided gate electrode in a logic region, a hard mask of the logic region gate electrode pattern is formed after the gate electrode pattern forming step. Removing the film, forming a spacer on sidewalls of the memory region and the gate electrode pattern, ion-implanting a predetermined region of the semiconductor substrate using the spacer as an ion implantation mask, and forming a source / drain region; And salifying the polysilicon layer of the removed logic region gate electrode pattern and the source / drain regions of the logic region.

According to an embodiment of the present invention, after the forming of the contact plug, the method may further include forming a wiring pattern connecting the contact plug of the memory area and the logic area.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Example 1

This embodiment provides a method of manufacturing an MML element for suppressing formation of residual silicon on a semiconductor substrate.

5 to 8 are perspective views illustrating a process of forming a gate electrode pattern in the MML semiconductor device manufacturing method according to the present embodiment. Reference numerals M and L denote memory regions and logic regions on the semiconductor substrate, respectively.

Referring to FIG. 5, an isolation layer (not shown) is first formed on a semiconductor substrate 200 in which a memory region M and a logic region L are defined. The device isolation layer is formed to electrically separate the boundary 300 between the memory region and the logic region, as well as between other elements of the logic region, such as NMOS and PMOS. The device isolation film is formed of silicon oxide using a conventional device isolation method, for example, a trench device isolation method. Then, a gate oxide film (not shown) is formed on the semiconductor substrate 200 exposed in the memory region M and the logic region L using a conventional method, for example, thermal oxidation. Subsequently, a polysilicon film 201, which is a gate conductive film, is formed on the entire surface of the semiconductor substrate 200 using a conventional method such as chemical vapor deposition.

Subsequently, the photoresist pattern 202 is formed in the logic region L by performing a photolithography process, and then the polysilicon film 201 formed in the memory region M is etched using this as an etching mask, thereby forming a memory. The height of the upper surface of the polysilicon film in the region M is made lower than the height of the upper surface of the polysilicon film 201 formed in the logic region L. As the etching method, an isotropic etching method or a gradient etching method is applied. The isotropic etching is, for example, by reducing the mean free path of plasma ions to reduce the linearity of the ions, thereby reducing the anisotropic etching characteristic or by using a reactive ion etching process using a highly reactive gas such as SF ₆ . The method of etching by reducing the anisotropic etching characteristic can be used. Gradient etching is a method of forming an inclined etching surface on the side by using a characteristic that the non-volatile polymer, which is a byproduct of etching, is accumulated on the side of the side where the ions are incident, so that the accumulated portion is not etched. Accordingly, the surface of the isotropically or obliquely etched polysilicon film is shown in the portion indicated by reference numeral A in FIG. 5 at the boundary 300 between the memory region M and the logic region L. As shown in FIG. It will have a cross-sectional shape with a slope as shown. The polysilicon film 201 of the memory region M to be etched is about 500 kPa to 4000 kPa.

Subsequently, a conventional ion implantation process is performed to inject conductive impurities, such as n-type impurities, only into the polysilicon film 201 formed in the memory region M. FIG.

6A and 6B, after removing the photoresist pattern 204 formed in the logic region L, the silicide layer 203 is formed on the entire surface of the semiconductor substrate 200. The silicide layer 203 may be formed of a heat resistant alloy silicide material such as WSi _x or TiSi _x . The silicide layer 203 is formed to a thickness of about 300 kPa to about 2000 kPa using a conventional vapor deposition method, for example, a chemical vapor deposition method. Since the silicide film 203 is formed while maintaining the surface shape of the lower polysilicon film 201, the silicide film 203 has an inclined surface at the boundary portion 300. Subsequently, the photoresist pattern 204 is formed in the memory region M by the photolithography process to selectively expose the silicide layer 203 formed in the logic region L. FIG. The photoresist pattern 204 is formed to be spaced apart from the boundary between the memory region M and the logic region L by an appropriate distance so as to expose or shield the inclined surface A of the polysilicon film. Wherein the photoresist pattern 204 is formed to expose or shield the polysilicon film 201 inclined surface (A), the surface shape of the hard mask film formed on the silicide film 203 and the polysilicon film 201 later Will be different.

Subsequently, the silicide layer 203 exposed in the logic region L is etched and removed using the photoresist pattern 204 as an etch mask. As an etching method, an isotropic etching process or an inclined etching process is applied as in the polysilicon etching process, and thus the surface of the silicide layer has an inclined surface B after etching. FIG. 6A shows the result after the silicide film 203 etching process when the photoresist pattern 204 is formed to shield the inclined surface A of the polysilicon film, and FIG. 6B shows the photoresist pattern 204 of the polysilicon film. The result after the etching process is shown when formed to expose the inclined surface (A).

Referring to FIGS. 7A and 7B, after etching, the photoresist pattern 204 is removed, and then a hard mask layer is formed on the memory region M and the logic region L using a conventional deposition method, for example, a chemical vapor deposition method. 205 is formed. Since the hard mask layer 205 is used as an etching mask in a subsequent gate electrode pattern forming step, the hard mask layer 205 is formed of a material having a small etching selectivity with respect to the lower polysilicon layer 201 and the silicide layer 203, for example, a silicon nitride layer. . The surface shape of the formed hard mask film 205 is formed along the surface shapes of the silicide film 203 and the polysilicon film 201 after the photoresist pattern 204 is removed, and the interface between the memory area and the logic area as shown in FIG. 7A. 300 has a convex stripe shape with an inclined surface, or interface 300 has a concave stripe shape with an inclined surface.

In the present invention, by etching the polysilicon layer 201 and the silicide layer 203 through an isotropic etching or a gradient etching method, the etching depths d ₃ and d ₄ of the hard mask layer 205 are etch depths according to the prior art ( in Fig. 3a d _1, it is possible to suppress the difference between the hard mask film, an etching depth remaining polysilicon is formed is reduced in the vicinity of Figure 3b shorter than d ₂₎ the boundary (300 due to misalignment).

Referring to FIG. 8, the gate electrode pattern 206 is formed by patterning the multiple layers of the hard mask layer, the polysilicon layer, and / or the silicide layer. First, a photoresist pattern (not shown) defining the gate electrode pattern is formed, and the hard mask layer is etched using the etching mask to form a hard mask pattern. The etching is performed through a conventional anisotropic etching method, such as reactive ion etching method.

Subsequently, the polysilicon film and / or the silicide film are anisotropically etched using the hard mask pattern as an etch mask, and the hard mask film 205 / polyside films 203 and 201 in the memory region and the hard mask film in the logic region L. A gate electrode pattern 206 made of (205) / polysilicon film 201 is formed. The etching process may be performed to maintain a high selectivity between the polysilicon layer 201 and the silicide layer 203 and the gate oxide layer (not shown) such that the gate oxide layer is an etching end point. In the etching process, it is preferable to adjust the process conditions such that the etching rate of the double layer of silicide / polysilicon in the memory region and the polysilicon layer in the logic region are substantially the same.

Hereinafter, a process of forming a polyside gate electrode in a memory region and a salicide gate electrode in a logic region from the gate electrode pattern will be described with reference to FIGS. 9 through 13. 9 to 13, the left side of the drawing centered around the center of the drawing shows a cross section of a process of forming a gate electrode of a memory region viewed from a direction indicated by reference C of FIG. 8, and the right side is a reference C. FIG. Shows a cross section of a process of forming a gate electrode of a logic region viewed from the direction indicated by ''.

Referring to FIG. 9, a heat treatment process (hereinafter, referred to as a “pox process”) is performed under an oxygen atmosphere to heal damage caused to sidewalls of the gate electrode pattern in the process of forming the gate electrode pattern. The temperature suitable for the Zippox process is about 800 ° C. When the geox process is performed, an oxide film (not shown), which is an oxide film, is formed on the gate electrode pattern sidewall and the gate oxide film (not shown). After the geopox process is completed, although not shown in the drawing, the LDD structure 210 is implemented by implanting a low concentration of conductive impurities into the memory region and / or the logic region by an ion implantation process.

Subsequently, a nitride film 211 and a medium temperature oxide film 212 are sequentially formed on the entire surface of the semiconductor substrate 200 which has undergone the above process. Here, the middle temperature oxide film 212 refers to an oxide film formed in the temperature range between 300 ℃ to 600 ℃. Of course, a high temperature oxide film may be formed instead of the middle temperature oxide film 212. The nitride film 211 and the mesophilic oxide film 212 are formed to a thickness of about 50 kPa to about 150 kPa and about 100 kPa to about 200 kPa by a conventional method, for example, a chemical vapor deposition method.

Referring to FIG. 10, after the photoresist pattern 207 is formed in the memory region M by a photolithography process, the middle temperature oxide film 212 exposed in the logic region L is wet-etched using the photoresist pattern 207 as an etching mask. Remove In the wet etching, an etching solution may be a hydrofluoric acid solution or a BOE (Buffered Oxide Echant) solution.

Referring to FIG. 11, after the photoresist pattern 207 is removed, the nitride layer 211 and the logic region exposed to the logic region L using the mesophilic oxide film 212 formed in the memory region M as an etch mask. Of the hard mask film 205 is removed using a conventional wet etching solution such as phosphoric acid. At this time, the hard mask film 205 of the memory region M is protected by the intermediate temperature oxide film 212 and is not etched.

Next, the intermediate temperature oxide film 213 is formed on the entire surface of the semiconductor substrate 200, and the spacer 214 made of a nitride film is formed on the sidewalls of the gate electrode pattern 206 in the memory region and the logic region by a conventional spacer forming method. . The spacer is formed by depositing a nitride film on the entire surface of the memory region and the logic region, and then anisotropic dry etching the nitride film using the mesophilic oxide film 213 as an etch stop film. On the other hand, when the geopox film (not shown) formed in the logic region L is formed to a thickness sufficient to be used as an etch stop film in the etching step for forming the spacer 214, the spacer 214 forming step Before proceeding, the middle temperature oxide film 213 may not be formed on the entire surface of the semiconductor substrate 200.

Subsequently, impurities are ion implanted using the spacer 214 as an ion implantation mask to form source / drain regions 208 and 209 on the semiconductor substrate, and impurities are also implanted into the gate electrode pattern of the logic region. In the drawing of this embodiment, only one MOS transistor is formed in the logic region, but in most cases, since the PMOS transistor and the NMOS transistor are simultaneously formed in the logic region, the source / drain region is implanted by injecting the appropriate ions according to each conductivity type. Can be formed.

Referring to FIG. 12, by performing a wet etching process using a wet etching solution, such as a hydrofluoric acid solution or a BOE solution, to remove an oxide-based insulating material, the upper surface of the gate electrode pattern of the logic region and the source / drain region ( 209). Thereafter, a salicide process is performed to form a self-aligned silicide layer 215 such as a cobalt silicide layer on the top surface of the gate electrode pattern 206 of the logic region L and the source / drain region 209. This will be described in detail as follows. First, a high melting point metal film, such as a cobalt film, is formed on the entire surface of the semiconductor substrate 200 to a predetermined thickness. Then, a heat treatment process is performed to cause a silicide reaction at the contact interface between the cobalt layer and the gate electrode pattern 206 of the logic region and the contact interface between the cobalt layer and the source / drain region 209 of the logic region. . Then, the non-silicided high melting point metal film is removed.

Next, referring to FIG. 13, a process of forming a self-aligned contact in a memory region on the semiconductor substrate subjected to the above process will be described. First, an interlayer insulating film 220 made of silicon oxide is formed on the entire surface of the semiconductor substrate 200. A self-aligned contact forming process is then applied to the memory region M to form a self-aligned contact 230 that is electrically connected to the source / drain region 208. In detail, first, a photoresist pattern (not shown) defining a portion in which the contact hole 240 is to be formed is formed on the interlayer insulating layer 220. Thereafter, a dry etching process using the photoresist pattern (not shown), the hard mask layer 205 and the spacer 214 formed in the memory region M as an etching mask is performed, thereby performing self alignment contact 230. The contact hole 240 exposing the source / drain region 180 to be formed is formed. Then, when the conductive material such as polysilicon is buried in the contact hole 240 in a conventional manner and then the planarization process is performed, a self-aligned contact 230 is formed in the contact hole 240.

Example 2

The present embodiment provides a method for blocking contact between the gate electrode and the residual polysilicon as another method for preventing electrical short caused by residual polysilicon.

14 is a perspective view for explaining a process of forming a gate electrode pattern by the method according to the present embodiment. Referring to FIG. 14, a gate electrode pattern is formed on a semiconductor substrate on which a polysilicon film, a silicide film, and a hard mask film are formed. The process of forming the polysilicon film, the silicide film and the hard mask film on the semiconductor substrate is completely the same as described in the prior art. A process of forming the gate electrode pattern will be described in detail. First, a photoresist pattern (not shown) defining a gate electrode pattern is formed on the hard mask layer by a photo process. Unlike the first embodiment, the photoresist pattern is formed to completely open the boundary portion 300 of the memory region M and the logic region L, that is, the stripe portion on the surface of the hard mask layer. The hard mask layer 205 is etched using the photoresist pattern as an etch mask to form a hard mask pattern. Subsequently, the lower polyside layers 203 and 201 and / or the silicide layer 203 are etched using the hard mask layer 205 as an etch mask to form a gate electrode pattern 206. Since the boundary portion 300 between the memory region M and the logic region L is etched, the gate electrode pattern of the memory region and the gate electrode pattern of the logic region are isolated from each other on the semiconductor substrate 200. Therefore, the remaining polysilicon 109 formed at the boundary between the memory area and the logic area is blocked from contacting the gate electrode, and thus there is no room for electrical short.

The method of forming the MML semiconductor device having the silicide gate electrode in the memory region and the salicide gate electrode in the logic region from the gate electrode pattern formed through the above process is as described in Embodiment 1 (see FIGS. 9 to 13). .

As described above, the gate electrode pattern formed through the above process is disconnected between the memory region and the logic region. Therefore, when the gate electrode is to be connected between the memory region and the logic region to transmit a signal, the gate electrode may be connected through a separate wiring after the gate electrode is formed. This process is as follows.

For reference, FIGS. 15 and 16 illustrate cross-sectional views when the semiconductor substrate is cut in the C ″ direction with reference to the drawing of FIG. 14. Referring to FIGS. 15 and 16, the same reference numerals as those of FIGS. The symbols refer to the same element.

Referring to FIG. 15, a photoresist pattern (not shown) defining a contact hole 260 for connecting the gate electrodes is formed on the interlayer insulating layer 250 formed on the gate electrode by a normal photolithography process. The interlayer insulating film may be immediately adjacent to the gate electrode, or may be interposed between the gate electrode and another interlayer insulating film. Using the photoresist pattern as an etch mask, the interlayer insulating film 250, the nitride film 211, and the hard mask film 205 on the gate electrode are sequentially etched to contact the silicide film 203 and the salicide 215, respectively. The hole 260 is formed. In the logic region, since the nitride film and the hard mask film are already removed on the salicide layer 215, only the interlayer insulating layer 250 is etched. The etching process is performed by a dry etching process, for example, a reactive ion etching method, for the interlayer insulating film 250, the nitride film 211, and the hard mask film 205 such that the silicide film or the salicide film of the gate electrode pattern is the end point of etching. The etching selectivity is performed under higher etching conditions than the silicide films 203 and 205. For example, when the interlayer insulating film is a silicon oxide film and the nitride film and the hard mask film are silicon nitride films, the films to be etched may be performed under a condition where the etching selectivity is higher than that of the silicide film through reactive ion etching using plasma.

Referring to FIG. 16, the contact hole 260 is filled with a conductive metal material to form a contact plug 270. The contact plug is formed by depositing a conductive metal material on the entire surface of the semiconductor substrate on which the contact hole 260 is formed, and then planarizing it by chemical mechanical polishing.

Subsequently, a metal wiring 280 is formed on the interlayer insulating layer on which the contact plug 270 is formed. Specifically, first, a photoresist pattern (not shown) defining a metallization pattern is formed by applying a general photolithography process to the metallization layer formed on the interlayer insulating layer. Next, the metallization layer is patterned using the photoresist pattern as an etch mask to form a metallization 280 that connects the memory region and the logic region. The metal wiring may use an existing metal wiring. For example, when the contact plug is formed in contact with an existing metal wire for inputting a signal to the gate line, the separate metal wire mentioned above is not necessary.

According to the present invention, in a method of manufacturing an MML semiconductor device having a polyside gate electrode in a memory region and a salicide gate electrode in a logic region, an etch stop layer for simultaneously forming a gate electrode pattern of a memory region and a logic region The hard mask layer is formed in a convex or concave stripe shape having an inclined surface at the boundary between the memory region and the logic region, thereby reducing the difference in the etching depth of the hard mask layer for forming the gate electrode, thereby preventing the formation of residual polysilicon in the etching process. Can be facilitated. In addition, the present invention by patterning the boundary between the memory region and the logic region that the gate electrode line passes through the gate electrode pattern forming step to electrically block the gate electrode of the memory region and the gate electrode of the logic region to form a separate connection wiring, Contact between the gate electrode and the polysilicon remaining at the boundary between the memory area and the logic area may be blocked.

Claims (6)

Preparing a semiconductor substrate having a memory region and a logic region defined therein and having a gate oxide film on a surface thereof; Forming a polysilicon film on the gate oxide film; Etching the polysilicon film of the memory area by a predetermined thickness to give a step to the thickness of the polysilicon film of the memory area and the logic area and to form a stepped surface inclined; Forming a silicide film on the polysilicon film; Etching the silicide layer in the logic region to expose the polysilicon layer and at the same time forming a side surface of the remaining silicide layer to be inclined; Forming a hard mask pattern defining a predetermined gate electrode pattern on the remaining silicide layer and the exposed polysilicon layer; And And forming a memory region and a logic region gate electrode pattern by anisotropically removing the silicide layer and the polysilicon layer by using the hard mask pattern as an etch mask. The method of claim 1, further comprising an anisotropic etching step using the hard mask pattern as an etching mask. Removing the hard mask pattern of the logic region and forming a spacer on sidewalls of the memory region and the gate electrode pattern of the logic region; Ion-implanting a predetermined region of the semiconductor substrate using the spacer as an ion implantation mask to form a source / drain region; And Salicided the polysilicon layer of the logic region gate electrode pattern and the source / drain regions of the logic region, the dual gate structure having a polyside gate electrode in the memory region and a salicided gate electrode in the logic region Method for producing an MML semiconductor device. The method of claim 1, wherein the step of forming the stepped surface inclined and the step of forming the side surface of the silicide layer are inclined isotropic or oblique etching. Preparing a semiconductor substrate having a memory region and a logic region defined therein and having a gate oxide film on a surface thereof; Forming a triple layer of a silicide / polysilicon / hard mask layer in the memory region of the semiconductor substrate and forming a double layer of a polysilicon layer / hard mask layer in a logic region; Forming a gate electrode pattern by patterning the hard mask layer, the silicide layer, and the polysilicon layer, and separating the memory region from the logic region gate electrode pattern by removing a boundary between the memory region and the logic region; Forming an interlayer insulating film on an entire surface of the semiconductor substrate on which the gate electrode pattern is formed; Etching a semiconductor substrate on which the interlayer insulating layer is formed to form a contact hole exposing a memory region gate electrode pattern and a logic region electrode pattern; And A method of manufacturing an MML semiconductor device having a dual gate structure, the method comprising: filling a contact hole to form a contact plug. The method of claim 4, wherein after the forming of the gate electrode pattern, Removing the hard mask layer of the logic region gate electrode pattern and forming spacers on sidewalls of the memory region and the gate electrode pattern; Ion-implanting a predetermined region of the semiconductor substrate using the spacer as an ion implantation mask to form a source / drain region; And Salifying the polysilicon layer of the logic region gate electrode pattern from which the hard mask layer has been removed and the source / drain regions of the logic region, and having a polyside gate electrode in the memory region and salicide in the logic region. A method for manufacturing a dual gate structure MML semiconductor device having a gate electrode. 5. The method of claim 4, further comprising forming a wiring pattern connecting the contact plugs of the memory area and the logic area after the forming of the contact plug.