KR100481987B1 - (Method for fabricating MOS capacitor of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a MOS capacitor of a semiconductor device, which allows a capacitor formation area to be increased by using a two step etching process for STI rounding when forming a MOS capacitor applied to a system on chip (SoC). Selectively etching the STI region to form an STI primary trench and a MOS capacitor primary trench to reduce edge slope; Forming a secondary trench in the STI region and forming a device isolation layer; Forming a gate oxide film on the front surface, depositing polysilicon successively, and then selectively patterning to form a gate electrode and a MOS capacitor electrode; Forming spacers on the sides of the electrodes after LDD ion implantation; Forming a source / drain region by forming an oxide layer on the front surface and blocking the capacitor storage node portion; Forming an interlayer insulating film and forming contact holes to form a metal contact layer.

Description

Method for fabricating MOS capacitor of semiconductor device

The present invention relates to a MOS capacitor applied to a system on chip (SoC), and more particularly, to a method of forming a MOS capacitor of a semiconductor device capable of increasing a capacitor formation area by using a two-step etching process for STI rounding. .

Prior art system-on-chip device development has simply increased the poly gate area of the MOS capacitor portion to increase the capacitance using the MOS capacitor.

However, this results in a reversal of trends in the wiring and gate lengths of the devices being miniaturized and results in a reduction in the number of devices to be formed per unit wiper.

On the contrary, if the area of MOS capacitor is reduced, the capacitance becomes small, making it difficult to use as a capacitor.

Hereinafter, the structure of the conventional MOS capacitor will be described.

1 is a structural cross-sectional view of a prior art MOS capacitor.

First, the device isolation layer 12 formed in the device isolation region of the semiconductor substrate 11, the MOS capacitor polyelectrode 13, the gate poly electrode 14, the interlayer insulating film 15, It is composed of a metal contact layer 16.

Looking at the characteristics of such a prior art MOS capacitor as follows.

First, since the junction structure of the previous LDD and source drain (part (b) of FIG. 1) is used as a storage node portion between a capacitor and a driving transistor, a leakage current due to defects caused by ion implantation. The leakage occurs due to the occurrence and the uneven distribution of the electric field.

In leakage-sensitive memory merged logic (MML) devices, this leakage can further degrade the refresh characteristics.

Instead of using LOCOS as a method of isolation between devices, shallow trench isolation (STI), which is advantageous for forming a micro device, is used, which forms a moat and an angle at an upper corner of the STI, and is not rounded at the edge of the STI. Not part) The electric field is concentrated in part (a) of FIG. 1 and a hump phenomenon and a leakage phenomenon, which are turned on before the gate operating voltage, occur, which causes the device to stably operate.

Accordingly, many efforts have been made to form the rounding of the STI edge portion to improve the hump phenomenon and leakage characteristics, but the prior art has not solved this problem.

The problem in the MOS capacitor forming process of the semiconductor device of the prior art is as follows.

First, in order to increase the capacitance of the MOS capacitor, it is necessary to increase the poly gate area of the MOS capacitor portion, but it is difficult to implement due to the miniaturization of the device.

Second, since the junction structure of the previous LDD and the source drain is used as a storage node portion between the capacitor and the driving transistor, there is a problem of a defect caused by ion implantation.

Third, element isolation using shallow trench isolation (STI) causes humps and leakages due to electric field concentrations in the upper corners of the STI, which interferes with stable operation of the device.

The present invention has been made to solve the problem of the MOS capacitor forming process of the prior art semiconductor device, by using a two-step etching process for STI rounding when forming a MOS capacitor applied to a system on chip (SoC) It is an object of the present invention to provide a method for forming a MOS capacitor of a semiconductor device capable of increasing the capacitor formation area.

According to an aspect of the present invention, there is provided a method of forming a MOS capacitor in a semiconductor device, by selectively etching a silicon substrate to form an STI primary trench and a MOS capacitor primary trench for reducing edge inclination of the STI region; Forming a secondary trench in the STI region and forming a device isolation layer; Forming a gate oxide film on the entire surface, depositing polysilicon continuously, and selectively patterning the gate electrode and the MOS capacitor electrode; Forming spacers on the sides of the electrodes after LDD ion implantation; Forming a source / drain region by forming an oxide layer on the front surface and blocking the capacitor storage node portion; Forming an interlayer insulating film and forming contact holes to form a metal contact layer.

A preferred embodiment of the method for forming a MOS capacitor of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2A to 2S are cross-sectional views of a process for forming a MOS capacitor according to the present invention.

The present invention relates to a system on chip (SOC) device development and process using a MOS capacitor.

In detail, the present invention provides a process method of increasing the MOS capacitance by changing the structure of the MOS capacitor while simultaneously improving a hump characteristic generated in shallow trench isolation (STI).

First, as shown in FIG. 2A, the bare silicon substrate 21 is annealed at a temperature of about 1100 to 1200 ° C. for 30 minutes in an N ₂ atmosphere.

This is to remove the defect of the silicon substrate 21 which may exist even a little. Current losses due to substrate defects are very sensitive to memory merged devices.

Subsequently, as in 2b, the first trench 22a of the portion where the photoresist PR1 is to be applied and the shallow trench isolation (STI) is to be formed, and the first trench for the purpose of increasing the capacity of the MOS capacitor to be formed later ( 22b) Define the part.

Then, the silicon substrate 21 is etched by anisotropic plasma etching using the patterned photoresist PR1 to etch a thickness of 200˜300 μs.

At this time, the thickness of the photoresist PR1 is set to 8000 to 15000Å so that a slight polymer 23 is formed on the sidewalls of the photoresist PR1 when the silicon substrate 21 is etched, thereby slightly inclining the trenches 22a and 22b. To be etched.

This etching of the primary silicon substrate 21 for forming the STI is to facilitate the STI top corner rounding, and reduces the angle of the edge portion primarily through the etching process.

Subsequently, as shown in FIG. 2C, the photoresist PR1 is removed and the pad oxide layer 24 is deposited to a thickness of 100 to 150 Å.

This relieves stress with the silicon substrate during subsequent nitride deposition and serves as a buffer layer during ion implantation.

As shown in FIG. 2D, after depositing the nitride 25, an STI portion for inter-device insulation is defined using photoresist PR2, and as shown in FIG. 2E, the exposed nitride 25 is etched. do.

Subsequently, as illustrated in FIG. 2F, the exposed silicon substrate 21 is etched using the patterned nitride 25 as a hard mask to form the secondary trench 26.

During the secondary silicon etching to form the STI, the inclination of the silicon sidewall is etched to about 83 to 89 degrees.

Here, since the trench 22b below the MOS capacitor to be formed later is blocked by the nitride 25, there is no loss due to etching.

As shown in FIG. 2G, the secondary trench 26 is gap-filled with a thickness of 7000 to 9000 7000 by PE-CVD and HLD or HDP, and as shown in FIG. The ride 25 is used as a polishing stopping layer to planarize.

At this time, the insulating film filled in the trench is over polished at 200 to 300 Å.

After that, the nitride 25 is cleaned with HF to reliably remove the oxide film, and the thickness of the insulating film formed in the secondary trench 26 is about 3500 to 5000 mW and the loss of the nitride 25 is about 100 to 200 mW. Becomes

As illustrated in FIG. 2I, the nitride 25 is removed by wet etching with a high temperature phosphoric acid (H ₃ PO ₄ ) solution.

After the nitride 25 is removed, annealing is performed for the purpose of densification of the inter-element insulating film and the STI top corner rounding, and the conditions are about 1100 ° C. for 30 minutes.

The formation of the primary and secondary trenches that were previously formed will result in the edge angles of the top corner portions being rounded further by this thermal process.

Subsequently, as shown in FIG. 2J, ion implantation for N-well and P-well formation is performed by masking by a photolithography process.

As shown in FIG. 2K, the pad oxide film 24 is removed to form the gate oxide film after the N-well and P-well formation, and the gate oxide film is grown at a high temperature as shown in FIG. 2L.

At this time, as the silicon substrate 21 is bent, the gate oxide film 28 is uniformly grown by the thermal process.

Subsequently, as shown in FIG. 2M, after the gate oxide film 28 is formed and the polysilicon 29 is continuously deposited, the gate electrode and the MOS capacitor electrode are defined using the photoresist PR3.

As shown in FIG. 2N, the poly-electrode 29 is etched to form the poly-electrode 30a of the MOS capacitor and the gate poly-electrode 30b of the driving transistor.

Thereafter, as illustrated in FIG. 2O, an ion implantation process for forming the LDD region 31 is performed.

As illustrated in FIG. 2P, nitride is deposited, and nitride spacers 32 are formed on the side of the gate through an anisotropic nitride etching process, followed by RTP (Rapid Thermal Process) treatment.

This is to prevent the impurity ions implanted by the LDD ion implantation process from being excessively diffused by the thermal process.

As shown in Fig. 2q, an oxide film 33 is deposited on the entire surface with a thickness of 200 to 300 mW.

Here, the deposition thickness of the oxide film 33 may vary depending on the length of the storage node. If the length of the storage node is 400 ms, the thickness of the oxide layer may be 200 to 220 ms.

That is, the oxide film 33 is deposited to about 1/2 times the length of the storage node.

It acts as a buffer layer to reduce silicon lattice damage during source and drain ion implantation, and as a blocking layer to prevent source and drain ion implantation in the storage node region connecting the MOS capacitor and the unit MOS transistor with the driving transistor as the gate electrode. To be used.

As shown in FIG. 2R, an ion implantation process for forming the source / drain regions 34 is performed. In this case, a source / drain region 34 is formed on the right side of the driving transistor.

As such, the reason for avoiding source / drain formation in the storage node region is to reduce the lattice damage caused by ion implantation, thereby reducing defects caused by silicon damage and to receive a uniform electric field through the uniform doping of the LDD region so that the current generated in the MOS capacitor is reduced. This is to minimize the loss of the transfer to the driving transistor.

Subsequently, as shown in FIG. 2S, photolithography and etching processes for ILD and silicide formation, interlayer insulating film 35 and planarization of interlayer insulating film, and metal contact layer 36 connecting elements and wirings are performed.

In the MOS capacitor and the driving transistor formed in this manner, the STI rounding portion was formed through the formation of the first trench, the formation of the second trench, and the annealing of the insulating film between the elements, and formed in the lower portion of the MOS capacitor when forming the first trench. By increasing the capacitance is increased.

This is done in STI formation without any additional process to increase capacitance capacity, and also oxide film is deposited at the storage node to block source / drain formation ion implantation to prevent unnecessary junction formation to improve leakage current phenomenon. .

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

The MOS capacitor forming method of the semiconductor device according to the present invention described above has the following effects.

The present invention improves the hump characteristic that is turned on before the gate operating voltage through the STI rounding implementation through the first shallow trench process for corner rounding in the implementation of the STI.

In addition, since a shallow trench (primary shallow trench) is formed under the MOS capacitor, an increase in the capacitor capacity can be achieved.

Therefore, it is possible to omit the processes of photo, etching, and various deposition operations required for capacitor formation to increase the capacitor capacity, thereby simplifying the process.

1 is a structural cross-sectional view of a conventional MOS capacitor.

2A to 2S are cross-sectional views of a process for forming a MOS capacitor according to the present invention.

Explanation of symbols on main parts of drawing

21. Bare silicon substrate 22a.22b. 1st trench

23. Polymer 24. Pad oxide

25. Nitride 26. Secondary Trench

27. Insulation film 28. Gate oxide film

29. Polysilicon 30a. MOS capacitor polyelectrode

30b. Gate polyelectrode 31.LDD region

32. Nitride spacers 33. Oxides

34. Source / drain regions 35. Interlayer insulating film

36. Metal contact layer

Claims (6)

Selectively etching the silicon substrate to form an STI primary trench and a MOS capacitor primary trench in which the STI region reduces edge slope; Forming a secondary trench in the STI region and forming a device isolation layer; Forming a gate oxide film on the front surface, depositing polysilicon successively, and then selectively patterning to form a gate electrode and a MOS capacitor electrode; Forming spacers on the sides of the electrodes after LDD ion implantation; Forming a source / drain region by forming an oxide layer on the front surface and blocking the capacitor storage node portion; Forming an interlayer insulating film and forming contact holes to form a metal contact layer. The method of claim 1, wherein the exposed silicon substrate is etched using the secondary trench as the hard mask as a hard mask so that the inclination of the silicon sidewall is 83 to 89 degrees. The insulating film filled in the trench is formed by over-polishing the insulating film filled in the trench by using a device isolation layer in the secondary trench gap gap insulating film 7000 ~ 9000 ~ thickness and nitride as a polishing stop film A method of forming a MOS capacitor of a semiconductor device, characterized in that. 4. The semiconductor device according to claim 2 or 3, wherein the nitride is removed by wet etching with a phosphoric acid (H ₃ PO ₄ ) solution and then annealed for the purpose of top corner rounding of the device isolation layer. How to form a capacitor. The method of claim 1, wherein the oxide layer is formed to a thickness of 1/2 times the length of the storage node. The method of claim 1, wherein the silicon substrate is etched by anisotropic plasma etching using a photoresist patterned with a primary trench to a thickness of 200˜300 μs, and a polymer is formed on the side where the etching is performed. MOS capacitor formation method of semiconductor device.