KR20020015167A - Method for foming self aligned contact of semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a self-aligned contact of a semiconductor device is provided to increase a lower area of a contact hole and to reduce contact resistance between a contact pad and a lower conductive layer, by forming a spacer composed of a silicon oxide layer and a silicon nitride layer on both sidewalls of a gate pattern and by additionally etching the lower portion of the silicon oxide layer so that an undercut is formed. CONSTITUTION: A plurality of gate patterns(109) are formed on a semiconductor substrate(100). The first insulation layer is formed on the semiconductor substrate including the gate patterns. The second insulation layer is formed on the first insulation layer. An interlayer dielectric covering the gate patterns is formed on the second insulation layer. The interlayer dielectric is patterned to form an opening exposing the second insulation layer between the gate patterns. The second insulation layer is anisotropically etched until the first insulation layer on the bottom of the opening is exposed so that a spacer(115a) is formed on the sidewall of the gate patterns. The exposed first insulation layer is isotropically etched to form the undercut in the lower portion of the opening. A conductive layer filling the opening is formed on the resultant structure having the undercut.

Description

METHOD FOR FOMING SELF ALIGNED CONTACT OF SEMICONDUCTOR DEVICE}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a self-aligned contact of a semiconductor device.

Due to the reduction of the design rule due to the high integration of semiconductor devices, the size of unit devices is gradually decreasing. Accordingly, it is required to reduce the size of the gate pattern. However, when the gate pattern is formed to a predetermined size or less, a dynamic margin becomes weak. Therefore, when manufacturing a semiconductor device, the process is performed in a direction in which the size of the gate pattern is increased as much as possible.

As such, despite the reduction of design rules, the size of the gate pattern is maintained at a constant level, thereby reducing the spacing between the gate patterns in the self-aligned contact forming process. There is a decreasing problem.

Hereinafter, the problems of the prior art will be described with reference to FIG. 1.

1A to 1D are cross-sectional views illustrating a method for forming a self-aligned contact of a semiconductor device according to the prior art.

Referring to FIG. 1A, an isolation layer 12 is formed to define a predetermined region of the semiconductor substrate 10 as an active region. The gate oxide film 14, the polysilicon film 15, the tungsten silicide film 16, the silicon nitride film 17, and the high temperature oxide (HTO) film 18 are formed over the semiconductor substrate 10 on which the device isolation film 12 is formed. The gate patterns 19 stacked in this order are formed. Conductive impurity ions are implanted on both sides of the gate pattern 19 to form source / drain 20 regions.

1B and 1C, a silicon nitride film 22 is formed on the entire surface of the semiconductor substrate 10 including the gate pattern 19. An interlayer insulating film 26 covering the gate pattern 19 is formed on the silicon nitride film 22. The interlayer insulating layer 26 is patterned to form a contact hole 27 exposing the silicon nitride layer 22 between the gate patterns 19. At this time, the interlayer insulating layer pattern 26a remains on the gate patterns 19. The silicon nitride film 220 is anisotropically etched to expose the source / drain 20 region to form spacers 22b on both sidewalls of the gate pattern 19.

Referring to FIG. 1D, a polysilicon film filling the contact hole 27 is formed on the entire surface of the resultant in which the contact hole 27 is formed. The contact pad 30 is formed by planarizing etching the polysilicon layer so that the interlayer insulating layer pattern 26a is exposed.

According to the related art, as the design rule decreases, the gap between the gate patterns 19 becomes smaller, while the gate pattern 19 is prevented from being exposed in the etching process for forming the contact hole 27. Since the silicon nitride film 22 should be formed to a sufficient thickness, the open margin of the contact hole 27 is gradually reduced.

In addition, since the contact resistance of the contact pad 30 is increased due to a decrease in the contact area between the contact pad 30 and the source / drain region 20, a problem of deteriorating electrical characteristics of the device occurs.

The present invention has been proposed to solve the above-mentioned problems, and an object thereof is to provide a method for forming a self-aligned contact capable of maximizing a contact area between a contact pad and a lower conductive film.

1A to 1D are cross-sectional views illustrating a method for forming a self-aligned contact of a semiconductor device according to the prior art.

2A to 2F are cross-sectional views illustrating a method of forming a self-aligned contact of a semiconductor device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10, 100: semiconductor substrate 12, 102: device isolation film

14, 104: gate oxide film 15, 105: polysilicon film

16, 106: tungsten silicide film 17, 107: gate capping film

18 and 108 mask layers 19 and 109 gate patterns

22 silicon nitride film 115 first insulating film

116: second insulating film 26, 118: interlayer insulating film

22a, 115a, 116a: spacer 27, 123: contact hole

30, 126: contact pad

(Configuration)

In order to achieve the above object, the present invention forms a plurality of gate patterns on a semiconductor substrate. A conformal first insulating film is formed over the entire semiconductor substrate including the gate patterns, and a second insulating film having a high etching selectivity is formed on the first insulating film. An interlayer insulating film covering the gate patterns is formed on the second insulating film. The interlayer insulating film is patterned to form an opening that exposes the second insulating film between the gate patterns. The second insulating film is anisotropically etched until the first insulating film of the opening bottom is exposed to form a spacer. The exposed first insulating film is removed by isotropic etching to form an undercut at the bottom of the opening. After the conductive film is formed on the entire surface of the resulting undercut, the contact pad is formed by flattening etching.

The first insulating film may be formed of a silicon oxide film, and the second insulating film may be formed of a silicon nitride film.

(Example)

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 2.

2A to 2G are cross-sectional views illustrating a method of forming a self-aligned contact of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2A, an isolation layer 102 is formed to limit a predetermined region of the semiconductor substrate 100 to an active region. The device isolation film 102 is formed using a conventional local oxidation of silicon (LOCOS) process or a trench device isolation process. A gate oxide film 104 is formed on the entire surface of the semiconductor substrate 100 on which the device isolation film 102 is formed. The polysilicon film 105 and the tungsten silicide film 106 are sequentially stacked on the gate oxide film 104 to form a gate electrode film having a polycide structure. The gate capping film 107 and the mask layer 108 are sequentially formed on the gate electrode film. The gate capping layer 107 for preventing the gate electrode layer from being exposed is formed of a silicon nitride layer, and the mask layer 108 for use as an etching mask for forming a gate pattern is formed of a high temperature oxide (HTO) layer. After the mask layer 108 is patterned by a conventional photolithography process, the gate capping layer 107, the gate electrode layers 105 and 106, and the gate oxide layer 104 are sequentially etched using the patterned mask layer 108 as an etching mask. The gate pattern 109 is formed. The source / drain regions 112 are formed by implanting conductive type impurity ions into the active regions on both sides of the gate pattern 109.

Referring to FIG. 2B, the first insulating film 115 is conformally formed on the entire surface of the resultant source / drain region 112. The first insulating film 115 is preferably formed of a silicon oxide film, for example, a high temperature oxide (HTO) film. As a result, compared with the prior art of forming a silicon nitride film on the gate pattern, the stress applied to the gate pattern can be reduced. The second insulating film 116 is formed on the first insulating film 115. The second insulating layer 116 may be formed of a material having a high etching selectivity with the first insulating layer 115, for example, a silicon nitride layer. As such, the first insulating layer 115 and the second insulating layer 116 formed on the gate patterns 109 serve as an etch stop layer to prevent the gate electrode layer from being exposed in a subsequent etching process. An interlayer insulating film 118 covering the gate pattern 109 is formed on the second insulating film 116. The interlayer insulating film 118 is formed of, for example, a borophosphosilicate glass (BPSG) film, an undoped silicate glass (USG) film, or a plasma oxide film. The interlayer insulating film 118 is planarized etched using a chemical mechanical polishing (CMP) or etch-back process to facilitate subsequent processes such as a patterning process and a wiring forming process.

Referring to FIG. 2C, a photoresist film is formed on the planarized interlayer insulating film 118 and then patterned to form a photoresist pattern 120 defining contact holes. The interlayer insulating layer 118 is etched using the photoresist pattern 120 as an etching mask to form a contact hole 123 exposing the second insulating layer 116 between the gate patterns 109. In this case, an interlayer insulating layer pattern 118a is formed on the gate pattern 123 to electrically isolate the contact pads. Thereafter, the photoresist pattern 120 is removed by an oxygen plasma ashing process and a wet cleaning process is performed to remove residual contaminants.

Referring to FIG. 2D, the second insulating layer 116 is anisotropically etched until the first insulating layer 115 at the bottom of the contact hole 123 is exposed to form the second insulating layer spacer 116a on both sidewalls of the gate pattern 119. Form. Here, since the first insulating film 115 remains on the semiconductor substrate 100 during the etching process for forming the second insulating film spacer 116a, it is possible to prevent the etching damage from being applied to the semiconductor substrate 100. .

Referring to FIG. 2E, the first insulating layer 115 exposed on the bottom of the contact hole 123 is removed by isotropic etching to form the first insulating layer spacer 115a. At the same time, the first insulating film 115 under the second insulating film spacer 116a is further etched to form the undercut 124 at the bottom of the contact hole 123. Then, since the area of the source / drain area 112 exposed to the bottom of the contact hole 123 is enlarged, the contact area with the contact pad may be increased. In this case, the isotropic etching process is performed using dry etching or wet etching.

Referring to FIG. 2F, a conductive film, for example, a polysilicon film, is formed on the entire surface of the resultant undercut 124 to fill the contact hole 123. The conductive layer is planarized and etched to expose the interlayer insulating layer pattern 118a to form a contact pad 126 electrically connected to the source / drain regions 112. At this time, the planarization etching is performed using a CMP process or an etch back process.

According to an embodiment of the present invention, a spacer in which a silicon oxide film and a silicon nitride film are stacked on both sidewalls of a gate pattern is formed, and then the bottom portion of the silicon oxide film is additionally etched to form an undercut. Has the effect of reducing

In addition, by using the silicon oxide film as the insulating film formed on the gate pattern, there is an effect of reducing the stress applied to the gate pattern.

In addition, since the silicon oxide film remains on the semiconductor substrate during the etching process for forming the silicon nitride film spacer, there is an effect of reducing the etching damage to the semiconductor substrate.

Claims (8)

Forming a plurality of gate patterns on the semiconductor substrate; Forming a first insulating film on an entire surface of the semiconductor substrate including the gate patterns; Forming a second insulating film on the first insulating film; Forming an interlayer insulating film covering the gate patterns on the second insulating film; Patterning the interlayer insulating film to form an opening exposing the second insulating film between the gate patterns; Forming an spacer on both sidewalls of the gate patterns by anisotropically etching the second insulating layer until the first insulating layer of the opening bottom is exposed; Removing the exposed first insulating layer by isotropic etching to form an undercut at the bottom of the opening; And And forming a conductive film filling the opening on the entire surface of the resultant product in which the undercut is formed. The method of claim 1, And the first insulating film is formed of a silicon oxide film. The method of claim 2, And the silicon oxide layer is a high temperature oxide (HTO) layer. The method of claim 1, And the second insulating layer is formed of a material having a high etching selectivity with respect to the first insulating layer. The method of claim 4, wherein And the second insulating film is formed of a silicon nitride film. The method of claim 1, The interlayer insulating layer is formed of any one of a borophosphosilicate glass (BPSG), an undoped silicate glass (USG) film and a plasma oxide film. The method of claim 1, And the isotropic etching is performed using wet etching or dry etching. The method of claim 1, And the conductive film is formed of a polysilicon film.