KR20020048618A - Semiconductor device with self aligned silicide layer and method for forming the same - Google Patents

Abstract

PURPOSE: A fabrication method of semiconductor device is provided to prevent a short between a semiconductor substrate and a contact plug due to an over-etch of an active region by forming etch stop layers. CONSTITUTION: A plurality of gate patterns(106) are formed on a substrate(100). A first etch stop layer(112) is formed on the resultant structure. After forming a material layer on the first etch stop layer(112), the material layer and the first etch stop layer(112) are sequentially etched to expose the upper surfaces of the gate patterns(106). After removing the material layer, metal silicide layers(116) are formed on the upper surfaces of the exposed gate patterns(106), thereby reducing a leakage current. Then, a second etch stop layer(118) is formed on the resultant structure.

Description

A semiconductor device having a salicide film and a method for manufacturing the same {SEMICONDUCTOR DEVICE WITH SELF ALIGNED SILICIDE LAYER AND METHOD FOR FORMING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device in which a salicide film is formed locally only on a gate electrode, and a manufacturing method thereof.

As semiconductor devices have been highly integrated, a salicide (self-aligned silicide) technique has been applied to reduce contact resistance and resistance of the source / drain regions and reduce the resistance of the gate electrode.

The conventional salicide process is a method of forming a silicide film by forming a metal film such as Ti, Co, and Pt on the entire surface of a semiconductor substrate on which a gate pattern is formed, and then reacting the gate electrode with silicon and a metal film in a source / drain region. At this time, since the insulating film spacer is formed on the sidewall of the gate pattern, the silicide film is locally formed only on the gate pattern and the source / drain regions.

However, when the silicide film is formed in the source / drain regions, there is an advantage of reducing the contact resistance, while having a problem that a junction leakage current may be generated when the silicide film has a poor profile. In addition, in the case of an ESD transistor for preventing chip destruction by electrostatic discharge (ESD), the resistance of the drain terminal must be high to maximize the protection against static electricity. However, when the low resistance silicide film is formed in the drain region, there is a problem that it is difficult to obtain a high resistance capable of overcoming static electricity by a physical method of increasing the length of the drain.

On the other hand, as the cell size of the semiconductor device is reduced, various process limitations are exposed throughout the semiconductor manufacturing process, and in particular, difficulties due to the miniaturization of the pattern size are emerging from the viewpoint of photographic technology. Various approaches have been attempted to overcome these limitations, and a borderless contact formation method for forming a contact on the active region and the isolation region by using an etch selectivity between an oxide layer and a nitride layer in an oxide layer etching process which is an interlayer insulating layer is performed. One such method is that.

However, when the conventional local salicide process is used, the device isolation film is excessively etched during the etching process for forming the borderless contact hole because the nitride film serving as the etch stop film cannot be formed during the subsequent interlayer insulating film etching process. . This causes a problem that the borderless contact and the substrate are electrically shorted.

Hereinafter, with reference to the accompanying drawings will be described in detail the problems of the prior art.

1A to 1E are cross-sectional views illustrating a method of forming a semiconductor device according to the prior art.

Referring to FIG. 1A, an isolation layer 12 is formed on a semiconductor substrate 10. A gate pattern 16 in which the gate oxide film 14 and the gate electrode 15 are stacked is formed in a predetermined region of the semiconductor substrate 10 on which the device isolation film 12 is formed. At this time, the gate electrode 15 is formed of a polysilicon film. Source / drain regions 17 are formed in active regions on both sides of the gate pattern 16, and spacers 19 are formed on both side walls of the gate pattern 16.

Referring to FIG. 1B, a first interlayer insulating film 23 is formed on the entire surface of the resultant product on which the spacers 19 are formed. The first interlayer insulating layer 23 is planarized by a chemical mechanical polish (CMP) process until the upper surface of the gate pattern 16, that is, the gate electrode 15 is exposed.

Referring to FIG. 1C, a high melting point metal film 25 for forming a silicide film is formed on the first interlayer insulating film 23 including the exposed gate electrode 15. The resultant in which the metal film 25 is formed is heat-treated to form a metal silicide film 26 on the gate electrode 15.

1D and 1E, the unreacted metal film 25 remaining on the first interlayer insulating film 23 is removed. A second interlayer insulating film 28 is formed on the metal silicide film 26 and the first interlayer insulating film 23. The second interlayer insulating layer 28 is patterned by a conventional photolithography process to form contact holes exposing the gate electrode 15 and the device isolation layer 12. A conductive film (not shown) is formed on the entire surface of the resultant where the contact holes are formed. The conductive film is flattened and etched until the second interlayer insulating film 28 is exposed to form a contact plug 30 in the contact hole.

In this case, since the etch stop layer for forming the contact hole is not formed, the phenomenon that the etch stop layer 12 and the device isolation layer 12 formed of the oxide film having a low etching selectivity is excessively etched may occur. As a result, an electric short circuit may occur between the contact plug 30 formed in the contact hole and the semiconductor substrate 12.

As described above, in the case of applying the salicide process according to the related art, since the borderless contact plug cannot be formed, it is difficult to increase the degree of integration of the semiconductor device.

The present invention has been proposed to solve the above-mentioned problems, and the active region is excessively recessed at the time of forming the contact hole at the time of forming the borderless contact plug while simultaneously applying the local salicide process to short-circuit the semiconductor substrate and the contact plug. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can be prevented.

Another object of the present invention is to provide a semiconductor device including a locally formed salicide film and having a structure capable of preventing excessive etching of the device isolation film in a contact hole forming process.

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

3 is a cross-sectional view for explaining the structure of a semiconductor device manufactured by an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10, 100: semiconductor substrate 12, 102: device isolation film

16, 106: gate pattern 19, 109: spacer

23, 28, 120: interlayer insulating film 113: material layer

112: first etch stop film 25, 115: metal film

26, 116 metal silicide film 118 second etch stop film

30, 123: contact plug

(Configuration)

In order to achieve the above object, the semiconductor device manufacturing method according to the present invention forms a plurality of gate patterns on a semiconductor substrate. A conformal first etch stop layer is formed on the entire surface of the semiconductor substrate including the gate patterns. A material layer is formed on the first etch stop layer. The material layer is planarized etched until the first etch stop layer is exposed on the gate patterns. The exposed first etch stop layer is patterned to expose the top surfaces of the gate patterns. The material layer is removed, and a metal silicide layer is formed on upper surfaces of the exposed gate patterns. A conformal second etch stop layer is formed on the metal silicide layer and the first etch stop layer.

In the present invention, it is preferable that the gate pattern is formed by sequentially stacking a gate oxide film and a gate electrode, and the gate electrode is formed of a polysilicon film. The first and second etch stop layers may be formed of a silicon nitride layer, and the material layer may be formed of a photoresist layer.

The forming of the metal silicide layer may include forming a metal layer on the exposed gate patterns and the first etch stop layer, heat treating an entire surface of the resultant product on which the metal layer is formed, and forming a metal silicide layer on the first etch stop layer. It is preferable to include the step of removing the reacted metal film. At this time, the metal film is preferably formed of any one of Co, Ti, Ni and Pt.

In order to achieve the above object, a semiconductor device according to an embodiment of the present invention includes a semiconductor substrate, a plurality of gate patterns formed on the semiconductor substrate, in which a gate oxide film, a polysilicon film, and a metal execution film are sequentially stacked, And a second etch stop layer formed on sidewalls and the semiconductor substrate, and a second etch stop layer formed on the first etch stop layer and the metal silicide layer.

In the present invention, the first and second etch stop films are preferably silicon nitride films.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 2A, an isolation layer 102 for defining an active region is formed on the semiconductor substrate 100. The device isolation film 102 is formed by a conventional trench device isolation process. A plurality of gate patterns 106 in which the gate oxide film 104 and the gate electrode 105 are sequentially stacked are formed on the semiconductor substrate 100 on which the device isolation film 102 is formed. The gate electrode 105 is preferably formed of a polysilicon film. In some cases, a gate capping film (not shown) may be further formed on the gate electrode 105 to insulate the gate electrode 105. The gate capping film is formed of, for example, a silicon oxide film or a silicon nitride film.

The source / drain regions 107 are formed by implanting conductive type impurity ions onto the active regions on both sides of the gate pattern 106. Subsequently, a silicon nitride film is formed on the entire surface of the semiconductor substrate 100 including the gate pattern 106 and then dry-etched to form spacers 109 on both sidewalls of the gate pattern 106. Thereafter, in some cases, a high concentration of impurity ions may be further implanted into active regions on both sides of the gate pattern 106 to form a lightly doped drain (LDD) region.

Referring to FIG. 2B, a conformal first etch stop layer 112 is formed on the entire surface of the resultant formed spacer 109. The first etch stop layer 112 serves to prevent the metal silicide layer from being formed in the source / drain regions 107 in a subsequent salicide process. The first etch stop film 112 is preferably formed of a silicon nitride film. A material layer 113, preferably a photoresist layer, is formed on the first etch stop layer 112. After the photoresist film 113 is formed, a conventional bake process for curing the photoresist film 113 is performed.

Referring to FIG. 2C, the material layer 113 is planarized etched until the first etch stop layer 112 formed on the gate pattern 106 is exposed. The planarization etching process may be performed by a dry etching process or a wet etching process having an excellent etching selectivity between the material layer 113 and the first etching stop layer 112.

Referring to FIG. 2D, a photoresist pattern is formed on the planarized material layer 113 and the exposed first etch stop layer 112 and then patterned to expose the first etch stop layer 112. (Not shown). The upper surface of the gate electrode 105 is exposed by removing the exposed first etch stop layer 112 using the photoresist pattern as an etch mask. Here, the process of removing the first etch stop layer 112 may be performed by dry etching or wet etching, which has excellent etching selectivity between the gate electrode 105 and the etch stop layer 112.

Referring to FIG. 2E, the material layer 113 remaining on the first etch stop layer 112 is removed. The high melting point metal layer 115 is formed on the first etch stop layer 112 and the exposed gate electrode 105. The metal film 115 is formed of any one of Co, Ti, Ni, and Pt, for example. The resulting metal film 115 is heat-treated to form a metal silicide film 116. At this time, silicon particles in the polysilicon film exposed on the gate electrode 105 react with the metal film 116 to form the metal silicide film 116. On the other hand, the metal film 115 formed on the first etch stop film 112 remains unreacted. Therefore, the metal silicide film 116 is selectively formed only on the gate electrode 105.

Referring to FIG. 2F, the unreacted metal film 115 remaining on the first etch stop film 112 is removed. Then, the gate electrode 105 in which the polysilicon film and the metal silicide film 116 are sequentially stacked is formed. Preferably, the entire surface of the semiconductor substrate 100 on which the metal silicide film 116 is formed is removed after the metal film 115 is removed. The heat treatment step proceeds, for example, at a temperature of 700 ° C or higher. This subsequent heat treatment process is for stabilizing and lowering the metal silicide film 116.

The second etch stop layer 118 is formed on the metal silicide layer 116 and the first etch stop layer 112. The second etch stop layer 118 prevents the underlying layer (eg, the silicon substrate) from being excessively etched in the subsequent etching process of forming the contact hole. The second etch stop film 118 is preferably formed of a silicon nitride film.

Referring to FIG. 2G, an interlayer insulating layer 120 is formed on the second etch stop layer 118. The interlayer insulating layer 120 is formed of any one of a silicon oxide film, for example, an undoped silicate (USG) film, a borophosphosilicate glass (BPSG) film, or a high temperature oxide (HTO) film. The interlayer insulating layer 120 is planarized by a CMP process or a dry etching process. The planarized interlayer insulating layer 120 is patterned to form contact holes exposing a predetermined region of the second etch stop layer 102, that is, the gate pattern 106, the device isolation layer 102, and an upper portion of the active region. Subsequently, the first and second etch stop layers 112 and 118 exposed to the bottom of the contact holes are selectively removed to expose the gate electrode, that is, the metal silicide layer 116, the device isolation layer 102, and the active region. .

Thereafter, a barrier film (not shown) is formed on the entire surface of the resultant contact hole. A conductive film, such as a tungsten film, is formed on the barrier film to fill the contact holes. The conductive plug and the barrier film are planarized by a CMP process or a dry etching process until the interlayer insulating layer is exposed to form contact plugs 123 filling the contact holes.

Next, the structure of the semiconductor device according to the embodiment of the present invention will be described in detail with reference to FIG. 3.

Referring to FIG. 3, the gate pattern 106 crosses an upper portion of the active region of the semiconductor substrate 100, and source / drain regions 107 are formed on both sides of the gate pattern 106. Here, the gate pattern 106 includes a gate oxide film 104 and a gate electrode stacked in turn, and the gate electrode includes a polysilicon film 105 and a metal silicide film 116 stacked in turn. Both sidewalls of the gate pattern 106 may be covered by the nitride film spacer 109. Both sidewalls of the gate pattern 106, that is, the spacer 109 and the semiconductor substrate 100, are covered with the first etch stop layer 112, and top surfaces of the first etch stop layer 112 and the gate pattern 106. That is, the metal silicide layer 116 is covered with the second etch stop layer 118. Here, the first and second etch stop films 112 and 118 are preferably silicon nitride films. When the semiconductor device having the salicide layer having such a structure is formed, the lower layer is prevented from being excessively etched by the first and second etch stop layers 112 and 118 during the etching process for forming the contact hole, which proceeds to a subsequent process. do.

The present invention applies a local salicide process that forms a silicide layer only on the gate electrode by the first etch stop layer, and then forms a second etch stop layer to prevent the underlying layer from being excessively etched in the subsequent borderless contact plug formation process. . Accordingly, since the salicide layer is not formed in the active region, the junction leakage current can be minimized, thereby enabling stable use even in low power devices, and maximizing the protection performance of the electrostatic protection transistor. In addition, since it is possible to apply a borderless contact forming process, it is possible to reduce the cell size to improve the integration of the device.

Claims (10)

Forming a plurality of gate patterns on the semiconductor substrate; Forming a conformal first etch stop layer on an entire surface of the semiconductor substrate including the gate patterns; Forming a material layer on the first etch stop layer; Planar etching the material layer until the first etch stop layer is exposed on the gate patterns; Patterning the exposed first etch stop layer to expose upper surfaces of the gate patterns; Removing the material layer; Forming a metal silicide layer on upper surfaces of the exposed gate patterns; And And forming a conformal second etch stop layer on the metal silicide layer and the material layer. The method of claim 1, And the gate pattern is formed by sequentially laminating a gate oxide film and a gate electrode. The method of claim 2, The gate electrode is formed of a polysilicon film. The method of claim 1, And the first and second etch stop films are silicon nitride films. The method of claim 1, And the material layer is formed of a photoresist film. The method of claim 1, Forming the metal silicide film, Forming a metal layer on the exposed gate patterns and the first etch stop layer; Heat-treating the entire surface of the resultant product on which the metal film is formed; And And removing an unreacted metal film on the first etch stop film. The method of claim 6, The metal film is formed of any one of Co, Ti, Ni and Pt. The method of claim 1, And forming a metal silicide film, and then heat treating the entire surface of the semiconductor substrate to 700 ° C. or higher. Semiconductor substrates; A plurality of gate patterns formed on the semiconductor substrate and sequentially stacked with a gate oxide film, a polysilicon film, and a metal silicide film; A first etch stop layer formed on sidewalls of the gate patterns and the semiconductor substrate; And And a second etch stop layer formed on the first etch stop layer and the metal silicide layer. The method of claim 9, And the first and second etch stop layers are silicon nitride layers.