KR20040060402A - A method for forming a contact of a semiconductor device - Google Patents

A method for forming a contact of a semiconductor device Download PDF

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KR20040060402A
KR20040060402A KR1020020087192A KR20020087192A KR20040060402A KR 20040060402 A KR20040060402 A KR 20040060402A KR 1020020087192 A KR1020020087192 A KR 1020020087192A KR 20020087192 A KR20020087192 A KR 20020087192A KR 20040060402 A KR20040060402 A KR 20040060402A
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contact
forming
nitride film
hard mask
etching
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KR1020020087192A
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Korean (ko)
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김형균
정승훈
박동수
우상호
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Abstract

PURPOSE: A method for forming a contact of a semiconductor device is provided to improve contact process margin by forming a nitride layer with bad step coverage on a conductive line. CONSTITUTION: A conductive line(13) with a hard mask(15) thereon and an insulating spacer(17) is formed on a substrate(11). An interlayer dielectric is formed on the resultant structure. A contact hole is formed by etching the interlayer dielectric using SAC(Self Aligned Contact). A nitride layer(25) with bad step coverage is formed on the resultant structure to cause overhang on the conductive line. The nitride layer on the bottom of the contact hole is selectively etched together with the overhang. Then, a contact plug is formed in the contact hole.

Description

반도체소자의 콘택 형성방법{A method for forming a contact of a semiconductor device}A method for forming a contact of a semiconductor device

본 발명은 반도체소자의 콘택 형성방법에 관한 것으로, 특히 저장전극을 하부에 콘택시킬 때 워드라인이나 비트라인을 상에 형성되는 하드마스크층의 손상으로 인한 소자의 특성 열화를 방지할 수 있도록 하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact of a semiconductor device, and in particular, to prevent deterioration of device characteristics due to damage to a hard mask layer formed on a word line or a bit line when a storage electrode is contacted to a lower portion. It is about.

종래기술에 따른 저장전극 콘택 노드의 형성 기술은 다음의 두 가지 방법이있다.There are two methods for forming a storage electrode contact node according to the prior art.

첫째, 비트라인이 형성된 전체표면상부에 절연막을 형성하고 저장전극 콘택 영역을 식각하고 이를 매립하는 것이다.First, an insulating film is formed on the entire surface where the bit lines are formed, and the storage electrode contact region is etched and buried.

둘째, 비트라인이 형성된 전체표면상부에 절연막을 형성하고 이를 평탄화식각한 다음, 비트라인과 교차하는 라인 타입 패터닝을 실시하여 콘택영역의 절연막을 식각하는 것으로서, 콘택 마진을 증가시킬 수 있다.Second, by forming an insulating film on the entire surface where the bit lines are formed and flattening the etching, and then etching the insulating film of the contact region by performing line type patterning that intersects the bit lines, the contact margin can be increased.

도시되지 않았으나, 종래기술에 따른 반도체소자의 콘택 형성방법 중에서 라인 타입으로 콘택홀을 형성하는 방법을 설명하면 다음과 같다.Although not shown, a method of forming a contact hole in a line type in the method for forming a contact of a semiconductor device according to the related art is as follows.

먼저, 활성영역에 워드라인이나 비트라인과 같은 도전배선이 형성된 반도체기판 상부에 하부절연층을 형성한다.First, a lower insulating layer is formed on the semiconductor substrate on which conductive lines such as word lines and bit lines are formed in the active region.

이때, 상기 도전배선은 측벽에 절연막 스페이서가 구비되고, 상부에 하드마스크층이 형성된 것이다. 여기서, 상기 하드마스크층과 절연막 스페이서는 질화막으로 형성된다.In this case, the conductive wiring is provided with an insulating film spacer on the side wall, the hard mask layer is formed on the top. Here, the hard mask layer and the insulating film spacer are formed of a nitride film.

그 다음, 전체표면상부를 평탄화시키는 층간절연막을 형성한다.Then, an interlayer insulating film is formed to planarize the entire upper surface portion.

상기 층간절연막을 평탄화식각하여 상기 하드마스크층을 노출시킨다. 이때, 상기 평탄화식각공정으로 인하여 상기 하드마스크층의 상측 일부가 손상되거나 전부가 손상된다.The interlayer insulating layer is planarized and etched to expose the hard mask layer. At this time, the upper portion of the hard mask layer is damaged or the entire damage due to the planarization etching process.

라인 타입의 저장전극 콘택마스크를 이용한 사진식각공정으로 저장전극의 콘택영역으로 예정된 부분의 층간절연막을 식각하여 자기정렬적으로 저장전극 콘택홀을 형성한다.A photolithography process using a line type storage electrode contact mask is used to etch the interlayer insulating film, which is intended as a contact region of the storage electrode, to form storage electrode contact holes in a self-aligned manner.

이때, 상기 저장전극 콘택홀은 폭이 너무 적어 저장전극용 도전층의 증착이 어렵다.At this time, the storage electrode contact hole is too small to deposit the conductive layer for the storage electrode.

상기한 바와 같이 종래기술에 따른 반도체소자의 콘택 형성방법은,As described above, the method for forming a contact of a semiconductor device according to the prior art,

반도체소자가 고집적화 됨에 따라 도전배선간의 콘택홀 폭이 좁아져 후속 공정으로 상기 콘택홀을 매립하는 도전층 증착공정이 어려우며, 평탄화 식각공정시 상기 도전배선 상측의 하드마스크층이 손상되어 상기 도전배선의 절연특성을 저하시켜 반도체소자의 특성 및 신뢰성을 저하시키고 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.As the semiconductor device becomes highly integrated, the contact hole width between the conductive wirings is narrowed, so that a conductive layer deposition process for filling the contact holes is difficult in a subsequent process, and the hard mask layer on the upper side of the conductive wiring is damaged during the planarization etching process, so that There is a problem in that the insulation characteristics are lowered, thereby deteriorating the characteristics and reliability of the semiconductor device and making it difficult to integrate the semiconductor device.

본 발명은 이러한 종래기술의 문제점을 해결하기 위하여, 도전배선의 측벽에 절연막 스페이서를 형성할 때 단차피복성이 나쁜 질화막을 증착하여 상기 도전배선 상측의 하드마스크층 상에 두꺼운 질화막을 남김으로써 소자의 특성 열화를 방지하는 동시에 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 콘택 형성방법을 제공하는데 그 목적이 있다.In order to solve the problems of the prior art, when forming an insulating film spacer on the sidewall of the conductive wiring, a nitride film having poor step coverage is deposited to leave a thick nitride film on the hard mask layer on the upper side of the conductive wiring. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a contact for a semiconductor device which prevents deterioration of the property and at the same time improves the characteristics and reliability of the semiconductor device and thereby enables high integration of the semiconductor device.

도 1a 내지 도 1g 는 본 발명의 실시예에 따른 반도체소자의 콘택 형성방법을 도시한 단면도.1A to 1G are cross-sectional views illustrating a method for forming a contact in a semiconductor device according to an embodiment of the present invention.

<도면의 주요부분에 대한 부호 설명><Description of Signs of Major Parts of Drawings>

11 : 반도체기판 13 : 도전배선11: semiconductor substrate 13: conductive wiring

15 : 하드마스크층 17 : 절연막 스페이서15 hard mask layer 17 insulating film spacer

19 : 층간절연막 21 : 콘택홀19: interlayer insulating film 21: contact hole

23 : 질화막 ( 단차피복성이 나쁜 ) 25 : 측면식각된 질화막23: nitride film (bad step coverage) 25: side etched nitride film

27 : 콘택플러그용 도전층 29 : 콘택플러그27: conductive layer for contact plug 29: contact plug

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 콘택 형성방법은,In order to achieve the above object, the contact forming method of a semiconductor device according to the present invention,

상측에 하드마스크층이 구비되고 측벽에 절연막 스페이서가 구비되는 도전배선을 형성하는 공정과,Forming a conductive wiring having a hard mask layer on an upper side thereof and an insulating layer spacer on a sidewall thereof;

전체표면상부에 층간절연막을 형성하고 상기 하드마스크층을 식각장벽으로 하여 평탄화시키는 공정과,Forming an interlayer insulating film over the entire surface and flattening the hard mask layer as an etch barrier;

자기정렬적인 콘택 공정으로 상기 층간절연막을 식각하여 상기 도전배선간을 노출시키는 콘택홀을 형성하는 공정과,Forming a contact hole exposing the conductive wiring by etching the interlayer insulating film by a self-aligned contact process;

상기 콘택홀을 포함한 전체표면상부에 단차피복성이 나쁜 질화막을 증착하되, 상기 도전배선 상측에 오버행이 유발되는 공정과,Depositing a nitride film having a poor step coverage on the entire surface including the contact hole, but causing an overhang on the conductive wiring;

측면식각 특성을 갖는 에천트를 이용한 식각공정으로 상기 오버행을 제거하며, 상기 콘택홀 저부의 질화막을 제거하는 공정과,Removing the overhang by an etching process using an etchant having a side etching property, and removing a nitride film at the bottom of the contact hole;

상기 콘택홀을 콘택플러그용 도전층으로 매립하고 이를 평탄화식각하여 콘택플러그를 형성하는 공정을 포함하는 것과,Embedding the contact hole into a conductive layer for contact plug and flattening-etching the contact hole to form a contact plug;

상기 하드마스크층은 2000 ∼ 3500 Å 두께의 질화막을 PECVD 또는 LPCVD 방법으로 형성하는 것과,The hard mask layer is formed by forming a nitride film of 2000 to 3500 mm thick by PECVD or LPCVD method,

상기 층간절연막의 평탄화 공정은 상기 하드마스크층과의 식각선택비 차이를 이용하여 CMP 또는 에치백 공정으로 실시하는 것과,The planarization process of the interlayer dielectric layer may be performed by a CMP or etch back process using a difference in etching selectivity from the hard mask layer.

상기 질화막은 650∼900 ℃ 의 온도, 1∼0.1 Torr 의 압력 하에서 DCS : NH3 = 1 : 1∼10 의 가스 비율을 갖는 조건에서 LPCVD 방법으로 형성하는 것과,The nitride film is formed by the LPCVD method under a condition having a gas ratio of DCS: NH 3 = 1: 1 to 10 at a temperature of 650 to 900 ° C. and a pressure of 1 to 0.1 Torr,

상기 질화막은 700∼900 ℃ 의 온도, 500∼1000 Torr 의 압력 하에서 SiH4 : NH3 = 1 : 1∼1000 의 가스 비율을 갖는 조건에서 싱글 챔버를 이용하여 LPCVD 방법으로 형성하는 것과,The nitride film is formed by the LPCVD method using a single chamber under a condition having a gas ratio of SiH 4: NH 3 = 1: 1 to 1000 at a temperature of 700 to 900 ° C. and a pressure of 500 to 1000 Torr,

상기 질화막은 450∼800 ℃ 의 온도에서 SiH4 : NH3 = 10∼1 : 1 의 가스비율을 갖는 조건에서 LPCVD 또는 PECVD 방법으로 형성하는 것과,The nitride film is formed by the LPCVD or PECVD method under a condition having a gas ratio of SiH 4: NH 3 = 10 to 1: 1 at a temperature of 450 to 800 ° C.,

상기 콘택플러그용 도전층의 평탄화식각공정은 CMP 또는 에치백 공정으로 실시하는 것을 특징으로 한다.The planar etching process of the contact plug conductive layer may be performed by a CMP or an etch back process.

한편, 본 발명의 원리는,On the other hand, the principle of the present invention,

워드라인이나 비트라인과 같은 도전배선 사이로 콘택홀을 형성하는 공정에 있어서,In the process of forming contact holes between conductive lines such as word lines and bit lines,

상기 도전배선 상측에 구비되는 하드마스크층의 상측에 다량 증착되어 오버행이 유발되고 그 측벽에 소량 증착되도록 단차피복비가 낮은 절연물질로 증착하고 후속 식각공정으로 상기 하드마스크층 상부에 증착된 오버행된 부분을 제거할 수 있도록 함으로써 비트라인 상부의 하드마스크층 손상을 최소화하고 상기 콘택홀의 매립 공정을 용이하게 실시할 수 있도록 하여 반도체소자의 특성 열화를 감소시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 것이다.An overhang portion deposited on top of the hard mask layer by depositing an insulating material having a low step coverage ratio so that a large amount is deposited on an upper side of the hard mask layer provided on the conductive wiring to cause an overhang and a small amount is deposited on the sidewall. By minimizing the damage, the damage of the hard mask layer on the bit line can be minimized, and the contact hole filling process can be easily performed, thereby reducing the deterioration of characteristics of the semiconductor device and consequently enabling high integration of the semiconductor device.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1g 는 본 발명의 실시예에 따른 반도체소자의 콘택 형성방법을 도시한 단면도이다.1A to 1G are cross-sectional views illustrating a method for forming a contact in a semiconductor device according to an embodiment of the present invention.

도 1a 를 참조하면, 반도체기판(11)의 활성영역 상에 워드라인이나 비트라인과 같은 도전배선용 도전층을 증착하고 그 상부에 하드마스크층용 질화막을 증착한다. 여기서, 상기 하드마스크층용 질화막은 PECVD 또는 LPCVD 방법으로 형성한다.Referring to FIG. 1A, a conductive layer for conductive wiring, such as a word line or a bit line, is deposited on an active region of the semiconductor substrate 11, and a nitride layer for a hard mask layer is deposited thereon. The nitride layer for the hard mask layer is formed by PECVD or LPCVD.

도전배선 마스크(도시안됨)를 이용한 사진식각공정으로 상기 하드마스크층용질화막과 도전배선용 도전층을 식각하여 상측에 하드마스크층(15)이 구비되는 도전배선(13)을 형성한다.In the photolithography process using a conductive wiring mask (not shown), the hard mask layer nitride film and the conductive wiring conductive layer are etched to form a conductive wiring 13 having a hard mask layer 15 thereon.

상기 도전배선(13) 측벽에 절연막 스페이서(17)를 형성한다. 이때, 상기 절연막 스페이서(17)는 질화막을 일정두께 증착하고 이를 이방성식각하여 형성한 것이다.An insulating film spacer 17 is formed on the sidewalls of the conductive wiring 13. In this case, the insulating film spacer 17 is formed by depositing a nitride film to a predetermined thickness and anisotropically etching it.

도 1b 및 도 1c 를 참조하면, 전체표면상부에 층간절연막(19)을 형성하고 상기 하드마스크층(15)이 노출되도록 평탄화식각한다. 이때, 상기 평탄화식각공정은 CMP 또는 에치백 공정으로 실시한다.1B and 1C, an interlayer insulating film 19 is formed over the entire surface and planarized etched to expose the hard mask layer 15. In this case, the planarization etching process is performed by a CMP or etch back process.

라인 타입의 콘택마스크(도시안됨), 예를 들면 저장전극용 콘택마스크를 이용한 사진식각공정으로 상기 도전배선(13) 사이를 노출시키는 콘택홀(21)을 형성한다.A contact hole 21 exposing the conductive wires 13 is formed by a photolithography process using a line type contact mask (not shown), for example, a storage electrode contact mask.

도 1d 를 참조하면, 전체표면상부에 단차피복성이 나쁜 질화막(23)을 증착하여 상기 도전배선(13) 상측에 오버행이 유발시킨다. 이때, 상기 질화막(23)은 상기 도전배선(13)의 측벽, 즉 콘택홀(21)의 측벽에 예정된 두께만큼만 증착하고 상기 도전배선(13) 상측에는 두껍게 증착한다.Referring to FIG. 1D, a nitride film 23 having poor step coverage is deposited on the entire surface to cause an overhang on the conductive wiring 13. In this case, the nitride film 23 is deposited only on the sidewall of the conductive wiring 13, that is, the sidewall of the contact hole 21, and is thickly deposited on the conductive wiring 13.

상기 질화막(23)은 다음과 같은 세가지 방법으로 형성한다.The nitride film 23 is formed in three ways as follows.

첫째, 650∼900 ℃ 의 온도, 1∼0.1 Torr 의 압력 하에서 DCS : NH3 = 1 : 1∼10 의 가스 비율을 갖는 조건에서 LPCVD 방법으로 형성한다.First, it forms by LPCVD method on the conditions which have a gas ratio of DCS: NH3 = 1: 1-10 under the temperature of 650-900 degreeC and the pressure of 1-0.1 Torr.

둘째, 700∼900 ℃ 의 온도, 500∼1000 torr 의 압력 하에서 SiH4 : NH3 = 1 : 1∼1000 의 가스 비율을 갖는 조건에서 싱글 챔버를 이용하여 LPCVD 방법으로 형성한다.Second, it is formed by the LPCVD method using a single chamber under the conditions of a gas ratio of SiH 4: NH 3 = 1: 1 to 1000 at a temperature of 700 to 900 ° C. and a pressure of 500 to 1000 torr.

셋째, 450∼800 ℃ 의 온도에서 SiH4 : NH3 = 10∼1 : 1 의 가스 비율을 갖는 조건에서 LPCVD 또는 PECVD 방법으로 형성한다.Third, it is formed by the LPCVD or PECVD method under the condition of having a gas ratio of SiH 4: NH 3 = 10 to 1: 1 at a temperature of 450 to 800 ° C.

도 1e 를 참조하면, 측면식각 특성을 갖는 에천트 ( etchant ) 를 이용하여 상기 도전배선(13)의 상측에 형성된 오버행 부분이 측면식각되도록 식각함으로써 상기 콘택홀(21)의 저부를 노출시키며 상기 하드마스크층(15) 상부의 질화막(23)을 측면 식각한 질화막(25)이 두껍게 형성된다.Referring to FIG. 1E, an overhang portion formed on the upper side of the conductive line 13 is etched side by using an etchant having a side etch characteristic to expose the bottom of the contact hole 21 to expose the hard portion. The nitride film 25 obtained by side etching the nitride film 23 on the mask layer 15 is thickly formed.

도 1f 를 참조하면, 전체표면상부에 상기 콘택홀(21)을 매립하는 콘택플러그용 도전층(27)을 형성한다.Referring to FIG. 1F, a contact plug conductive layer 27 filling the contact hole 21 is formed on the entire surface.

상기 도 1f 의 점선은 상기 콘택플러그용 도전층(27)을 평탄화 식각 정도를 도시한 것으로, 상기 하드마스크층(15)일 상측 일부가 식각된다.The dotted line in FIG. 1F illustrates a degree of planarization etching of the contact plug conductive layer 27, and a portion of an upper side of the hard mask layer 15 is etched.

도 1g 를 참조하면, 상기 도 1f 의 점선을 타겟으로 하는 평탄화식각공정으로 상기 콘택플러그용 도전층(27) 및 하드마스크층(15)의 상측 일부를 식각하여 콘택플러그(29)를 형성한다.Referring to FIG. 1G, a contact plug 29 may be formed by etching a portion of the upper surface of the contact plug conductive layer 27 and the hard mask layer 15 by a planarization etching process using the dotted line of FIG. 1F.

이때, 상기 평탄화식각공정은 상기 콘택플러그용 도전층(27), 상기 하드마스크층(15) 및 층간절연막(19)의 식각선택비 차이를 이용하여 실시한다.In this case, the planarization etching process is performed by using an etching selectivity difference between the contact plug conductive layer 27, the hard mask layer 15, and the interlayer insulating layer 19.

상기 평탄화식각공정은 CMP 또는 에치백 공정으로 실시한다.The planarization etching process is performed by a CMP or etch back process.

이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자의 콘택 형성방법은,As described above, the method for forming a contact of a semiconductor device according to the present invention,

도전배선의 측벽에 예정된 두께의 질화막을 증착하는 동시에 상기 도전배선의 상측에 두껍게 질화막을 증착할 수 있도록 단차피복성이 나쁜 증착방법으로 질화막을 전체표면상부에 형성하고 측면식각 특성을 갖는 식각공정으로 실시하여 소자의 특성 열화없이 후속 콘택 형성 공정을 용이하게 실시할 수 있도록 함으로써 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 효과를 제공한다.In order to deposit a nitride film having a predetermined thickness on the sidewall of the conductive wiring and to deposit the nitride film on the upper side of the conductive wiring, the nitride film is formed on the entire surface by a deposition method having poor step coverage and has an etch property having a side etching characteristic. In this way, the subsequent contact forming process can be easily performed without deteriorating the characteristics of the device, thereby improving the characteristics and reliability of the semiconductor device and thereby providing a high integration of the semiconductor device.

Claims (7)

상측에 하드마스크층이 구비되고 측벽에 절연막 스페이서가 구비되는 도전배선을 형성하는 공정과,Forming a conductive wiring having a hard mask layer on an upper side thereof and an insulating layer spacer on a sidewall thereof; 전체표면상부에 층간절연막을 형성하고 상기 하드마스크층을 식각장벽으로 하여 평탄화시키는 공정과,Forming an interlayer insulating film over the entire surface and flattening the hard mask layer as an etch barrier; 자기정렬적인 콘택 공정으로 상기 층간절연막을 식각하여 상기 도전배선간을 노출시키는 콘택홀을 형성하는 공정과,Forming a contact hole exposing the conductive wiring by etching the interlayer insulating film by a self-aligned contact process; 상기 콘택홀을 포함한 전체표면상부에 단차피복성이 나쁜 질화막을 증착하되, 상기 도전배선 상측에 오버행이 유발되는 공정과,Depositing a nitride film having a poor step coverage on the entire surface including the contact hole, but causing an overhang on the conductive wiring; 측면 식각 특성을 갖는 에천트를 이용한 식각공정으로 상기 오버행을 제거하며, 상기 콘택홀 저부의 질화막을 제거하는 공정과,Removing the overhang by an etching process using an etchant having a side etching property, and removing a nitride film at the bottom of the contact hole; 상기 콘택홀을 콘택플러그용 도전층으로 매립하고 이를 평탄화식각하여 콘택플러그를 형성하는 공정을 포함하는 반도체소자의 콘택 형성방법.And forming a contact plug by filling the contact hole with a conductive layer for contact plug and flattening-etching the contact hole. 제 1 항에 있어서,The method of claim 1, 상기 하드마스크층은 2000 ∼ 3500 Å 두께의 질화막을 PECVD 또는 LPCVD 방법으로 형성하는 것을 특징으로 하는 반도체소자의 콘택 형성방법.The hard mask layer is a contact forming method of a semiconductor device, characterized in that to form a nitride film of 2000 ~ 3500 Å thickness by PECVD or LPCVD method. 제 1 항에 있어서,The method of claim 1, 상기 층간절연막의 평탄화 공정은 상기 하드마스크층과의 식각선택비 차이를 이용하여 CMP 또는 에치백 공정으로 실시하는 것을 특징으로 하는 반도체소자의 콘택 형성방법.The planarization process of the interlayer dielectric layer is performed by a CMP or an etch back process using a difference in etching selectivity from the hard mask layer. 제 1 항에 있어서,The method of claim 1, 상기 질화막은 650∼900 ℃ 의 온도, 1∼0.1 torr 의 압력 하에서 DCS : NH3 = 1 : 1∼10 의 가스 비율을 갖는 조건에서 LPCVD 방법으로 형성하는 것을 특징으로 하는 반도체소자의 콘택 형성방법.The nitride film is formed by the LPCVD method under a condition having a gas ratio of DCS: NH3 = 1: 1 to 10 at a temperature of 650 to 900 ° C. and a pressure of 1 to 0.1 torr. 제 1 항에 있어서,The method of claim 1, 상기 질화막은 700∼900 ℃ 의 온도, 500∼1000 Torr 의 압력 하에서 SiH4 : NH3 = 1 : 1∼1000 의 가스 비율을 갖는 조건에서 싱글 챔버를 이용하여 LPCVD 방법으로 형성하는 것을 특징으로 하는 반도체소자의 콘택 형성방법.The nitride film is formed by the LPCVD method using a single chamber under a condition having a gas ratio of SiH 4: NH 3 = 1: 1 to 1000 at a temperature of 700 to 900 ° C. and a pressure of 500 to 1000 Torr. Contact formation method. 제 1 항에 있어서,The method of claim 1, 상기 질화막은 450∼800 ℃ 의 온도에서 SiH4 : NH3 = 10∼1 : 1 의 가스 비율을 갖는 조건에서 LPCVD 또는 PECVD 방법으로 형성하는 것을 특징으로 하는 반도체소자의 콘택 형성방법.The nitride film is a contact forming method of a semiconductor device, characterized in that formed by the LPCVD or PECVD method under a gas ratio of SiH4: NH3 = 10 to 1: 1 at a temperature of 450 ~ 800 ℃. 제 1 항에 있어서,The method of claim 1, 상기 콘택플러그용 도전층의 평탄화식각공정은 CMP 또는 에치백 공정으로 실시하는 것을 특징으로 하는 반도체소자의 콘택 형성방법.The planarization etching process of the conductive layer for contact plugs is performed by a CMP or etch back process.
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