KR100780614B1 - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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KR100780614B1
KR100780614B1 KR1020060096513A KR20060096513A KR100780614B1 KR 100780614 B1 KR100780614 B1 KR 100780614B1 KR 1020060096513 A KR1020060096513 A KR 1020060096513A KR 20060096513 A KR20060096513 A KR 20060096513A KR 100780614 B1 KR100780614 B1 KR 100780614B1
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nitride film
semiconductor device
forming
nitride
device manufacturing
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KR1020060096513A
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Korean (ko)
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남기원
한기현
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for fabricating a semiconductor device is provided to enhance reliability by reducing a parasitic capacitance value between a bit line pattern and a storage node contact plug. A plurality of conductive patterns are formed on a substrate(11). An insulating layer(12) is formed on the conductive patterns. An opening part is formed between the conductive patterns by etching the insulating layer. A sidewall insulating layer including a first nitride layer having boron and a second nitride layer having silicon is formed on a sidewall of the opening part. A contact plug is formed to bury the opening part. The process for forming the sidewall insulating layer includes a process for forming the first nitride layer on the entire surface having the opening part, a process for forming the second nitride layer on the first nitride layer, and a process for performing an etch-back operation.

Description

반도체 소자 제조방법{METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}Semiconductor device manufacturing method {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

도 1a 내지 도 1f는 본 발명의 바람직한 실시예에 따른 반도체 소자 제조방법을 설명하기 위한 공정 단면도.1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

11 : 반도체 기판 12 : 제1절연층11 semiconductor substrate 12 first insulating layer

13 : 폴리실리콘전극 14 : 금속전극13 polysilicon electrode 14 metal electrode

15 : 비트라인하드마스크 16 : 측벽보호막15 bit line hard mask 16 sidewall protective film

17 : 제2절연층 18 : 하드마스크패턴17: second insulating layer 18: hard mask pattern

19 : 스토리지 노드 콘택홀 20A : 제1질화막19: storage node contact hole 20A: first nitride film

21A : 제2질화막 100 : 측벽절연막21A: second nitride film 100: sidewall insulating film

본 발명은 반도체 제조 기술에 관한 것으로, 특히 기생캐패시터 감소를 위한 반도체 소자의 절연막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for forming an insulating film of a semiconductor device for reducing parasitic capacitors.

반도체 소자의 고집적화에 따라 라인(Line) 간 공간(Spacing)의 감소 및 워드라인(Word Ling)과 비트라인(Bit Line) 또는 캐패시터(Cpatpcitor)의 사이를 분리시키는 각각의 절연막 두께가 지속적으로 감소하고 있다. As semiconductor devices become more integrated, the thickness of each insulating layer that reduces the spacing between lines and separates between word lines and bit lines or capacitors is continuously reduced. have.

위와 같이, 절연막의 두께 감소는 원하지 않는 기생 캐패시턴스(Capacitance) 값을 증가시키고 이로 인해 소자 특성이 열화되는 문제점이 있다. As described above, there is a problem in that the thickness reduction of the insulating layer increases the parasitic capacitance value, which causes deterioration of device characteristics.

기생 캐패시턴스 값이 증가되는 문제점을 해결하기 위해 절연막의 두께를 증가시키거나 낮은 유전율을 가지는 막을 층간절연막 및 측벽절연막으로 사용하고 있다. 그러나, 단순히 절연막의 두께만을 증가시킬 경우 각 라인 간의 공간 감소와 이에 따른 갭필(Gap Fill) 마진 감소를 유발할 수 있고, 낮은 유전율을 가지는 막은 소자 측면에서 완전하게 검증되지 않은 문제점과 낮은 증착 스텝 커버리지(Step Coverage)에 의한 갭필 마진 감소를 유발하는 문제점이 있다.In order to solve the problem of increasing parasitic capacitance, an increase in the thickness of the insulating film or a film having a low dielectric constant is used as the interlayer insulating film and the sidewall insulating film. However, simply increasing the thickness of the insulating film can cause a decrease in the space between lines and thus a gap fill margin, and a film having a low dielectric constant has not been fully verified in terms of device and low deposition step coverage. There is a problem that causes a gap fill margin decrease by step coverage.

특히, 스토리지 노드 콘택홀 형성시를 살펴보면 스토리지 노드 콘택홀을 형성한 후 스토리지 노드 콘택 플러그와 비트라인 간의 절연을 위하여 질화막(Nitride) 계열의 막을 전면 증착하고 전면 식각을 이용하여 스토리지 노드 콘택홀의 측벽에 측벽절연막을 형성하게 된다. In particular, when forming a storage node contact hole, after forming the storage node contact hole, a nitride-based film is deposited on the entire surface of the nitride layer to insulate the storage node contact plug from the bit line and is formed on the sidewall of the storage node contact hole by using front etching. A sidewall insulating film is formed.

그러나, 스텝 커버리지가 좋은 질화막 계열의 측벽절연막은 유전 상수 k ~ 6 정도의 높은 유전율 값을 가진다. 이로 인해, 비트라인과 스토리지 노드 콘택 플러그 간에 불필요한 기생 캐패시턴스가 발생하게 된다.However, the nitride film-based sidewall insulating film having good step coverage has a high dielectric constant value of about k to 6 dielectric constant. This causes unnecessary parasitic capacitance between the bitline and the storage node contact plugs.

기생 캐패시턴스 값을 낮추기 위하여 질화막 계열의 측벽절연막보다 낮은 유 전율을 가지는 LPCVD(Low Pressuer Chemical Vapor Deposition) 또는 PECVD(Plasma Enhanced Chemical Vapor Deposition)로 형성된 산화막을 측벽절연막으로 사용할 수 있다.In order to reduce the parasitic capacitance value, an oxide film formed by LPCVD (Low Pressuer Chemical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition) having a lower dielectric constant than that of the nitride-based sidewall insulating layer may be used as the sidewall insulating layer.

그러나, 산화막은 측벽절연막을 형성하기 위한 전면 식각 후 진행하는 세정공정에서 일정 부분 손실이 발생하여 충분한 두께를 확보하지 못하며, 손실이 발생하는 부분을 감안하여 두껍게 형성하면 산화막의 스텝 커버리지(Step Coverage) 한계로 인해 스토리지 노드 콘택홀이 막힐 수 있다. 또한, 세정공정을 감소시킬 경우 스토리지 노드 콘택홀 내부의 하부 랜딩 플러그 상에 불순물층(예컨대, 자연산화막(Native Oxide))을 완벽하게 제거하지 못하기 때문에 스토리지 노드 콘택과 랜딩 플러그 콘택 간의 저항을 증가시킬 우려가 있다.However, the oxide film does not secure sufficient thickness due to a certain part loss in the cleaning process that is performed after the entire surface etching to form the sidewall insulating film.If the oxide film is thickly formed in consideration of the loss part, the step coverage of the oxide film is Limitations can clog storage node contact holes. In addition, if the cleaning process is reduced, the impurity layer (for example, native oxide) cannot be completely removed from the lower landing plug inside the storage node contact hole, thereby increasing the resistance between the storage node contact and the landing plug contact. There is a risk of making.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 스텝커버리지의 악화를 방지하면서 기생 캐패시턴스 값을 낮출 수 있는 반도체 소자 제조방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device capable of lowering a parasitic capacitance value while preventing deterioration of step coverage.

본 발명에 의한 반도체 소자 제조방법은 기판 상에 복수개의 도전패턴을 형성하는 단계, 상기 도전패턴 상에 절연층을 형성하는 단계, 상기 도전패턴 사이의 절연층을 식각하여 오픈부를 형성하는 단계, 상기 오픈부의 측벽에 이중층의 측벽 절연막을 형성하는 단계, 상기 오픈부를 매립하는 콘택플러그를 형성하는 단계를 포함하는 것을 특징으로 한다.The method of manufacturing a semiconductor device according to the present invention includes the steps of forming a plurality of conductive patterns on a substrate, forming an insulating layer on the conductive pattern, forming an open part by etching the insulating layer between the conductive patterns, and And forming a sidewall insulating film of a double layer on the sidewall of the open portion, and forming a contact plug filling the open portion.

특히, 측벽절연막은 보론이 함유된 제1질화막과 실리콘이 함유된 제2질화막의 적층구조로 형성하고, 제1질화막은 제1 및 제2질화막의 총 두께에 20％∼25％의 두께로 형성하는 것을 특징으로 한다.In particular, the sidewall insulating film is formed by a lamination structure of the first nitride film containing boron and the second nitride film containing silicon, and the first nitride film is formed to have a thickness of 20% to 25% to the total thickness of the first and second nitride films. Characterized in that.

또한, 제1질화막의 유전상수는 2∼5의 값을 갖도록 형성하는 것을 특징으로 한다.In addition, the dielectric constant of the first nitride film is characterized in that it is formed to have a value of 2 to 5.

이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

도 1a 내지 도 1f는 본 발명의 바람직한 실시예에 따른 반도체 소자 제조방법에 관한 것이다.1A to 1F are directed to a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

도 1a에 도시된 바와 같이, 반도체 기판(11) 상에 제1절연층(12)을 형성한다. 여기서, 제1절연층(12)은 예컨대 산화막(Oxide)으로 형성하고 단층 또는 다층으로 형성될수 있다. 또한, 제1절연층(12) 형성 전에 게이트패턴 및 랜딩 플러그 콘택(Landing Plug Contact;LPC)이 형성될 수 있다.As shown in FIG. 1A, a first insulating layer 12 is formed on the semiconductor substrate 11. Here, the first insulating layer 12 may be formed of, for example, an oxide and may be formed in a single layer or multiple layers. In addition, a gate pattern and a landing plug contact (LPC) may be formed before the first insulating layer 12 is formed.

이어서, 제1절연층(12) 상에 복수개의 비트라인패턴(Bit Line Pattern)을 형성한다. 여기서, 비트라인패턴은 폴리실리콘전극(13), 금속전극(14)과 비트라인하드마스크(15)의 적층구조로 형성된다. 특히, 금속전극(14)은 예컨대 텅스텐(Ｗ) 또 는 텅스텐실리사이드(ＷSix)로 형성하고, 비트라인하드마스크(15)는 예컨대 질화막(Nitride)으로 형성할 수 있다.Subsequently, a plurality of bit line patterns are formed on the first insulating layer 12. Here, the bit line pattern is formed in a stacked structure of the polysilicon electrode 13, the metal electrode 14, and the bit line hard mask 15. In particular, the metal electrode 14 may be formed of, for example, tungsten or tungsten silicide (Six), and the bit line hard mask 15 may be formed of, for example, a nitride film.

이어서, 비트라인패턴의 측벽에 측벽보호막(16)을 형성한다. 여기서, 측벽보호막(16)은 비트라인패턴 특히, 금속전극(14)의 측벽을 보호하기 위한 것으로 예컨대 질화막으로 형성한다.Next, the sidewall protection film 16 is formed on the sidewall of the bit line pattern. Here, the sidewall protection film 16 is for protecting the bit line pattern, especially the sidewall of the metal electrode 14, and is formed of, for example, a nitride film.

이어서, 비트라인패턴 사이를 채우면서 비트라인패턴 상에 제2절연층(17)을 형성한다. 여기서, 제2절연층(17)은 제1절연층(12)과 동일한 물질로 형성할 수 있고 예컨대 산화막으로 형성한다.Subsequently, the second insulating layer 17 is formed on the bit line patterns while filling the bit line patterns. Here, the second insulating layer 17 may be formed of the same material as the first insulating layer 12 and formed of, for example, an oxide film.

이어서, 제2절연층(17) 상에 하드마스크패턴(18)을 형성한다. 여기서, 하드마스크패턴(18)은 스토리지 노드 콘택을 위한 오픈부 예정지역이 오픈되어 제2절연층(17) 식각시 식각마스크역할을 하기 위한 것이다. 하드마스크패턴(18)은 제2절연층(17) 상에 하드마스크층을 형성하고, 하드마스크층 상에 감광막을 코팅한 후 노광 및 현상으로 감광막패턴을 형성하고, 감광막패턴을 식각마스크로 하드마스크층을 식각하여 형성한다. Subsequently, a hard mask pattern 18 is formed on the second insulating layer 17. In this case, the hard mask pattern 18 serves as an etch mask during the etching of the second insulating layer 17 by opening a predetermined opening area for the storage node contact. The hard mask pattern 18 forms a hard mask layer on the second insulating layer 17, coats the photoresist film on the hard mask layer, forms a photoresist pattern by exposure and development, and hardens the photoresist pattern as an etch mask. The mask layer is formed by etching.

도 1b에 도시된 바와 같이, 하드마스크패턴(18)을 식각마스크로 제2 및 제1절연층(17, 12)을 식각하여 스토리지 노드 콘택(Storage Node Contact;SNC)을 위한 오픈부(19)를 형성한다.As illustrated in FIG. 1B, the second and first insulating layers 17 and 12 are etched using the hard mask pattern 18 as an etch mask to open the opening 19 for a storage node contact (SNC). To form.

도 1c에 도시된 바와 같이, 오픈부(19)를 포함하는 결과물의 전면에 보론이 함유된 제1질화막(20)을 형성한다. As illustrated in FIG. 1C, the first nitride layer 20 containing boron is formed on the entire surface of the resultant including the open portion 19.

제1질화막(20)은 500℃∼1000℃의 온도, 0.2Torr∼0.6Torr의 압력을 유지하 고 N2, NH3 및 BCl3의 혼합가스를 사용하여 형성한다. 이때, 혼합가스는 N2:NH3:BCl3를 1∼2:10:1∼2의 유량비율로 혼합하여 사용하고, 전체 혼합가스의 총 유량은 300sccm∼1000sccm을 사용한다.The first nitride film 20 is formed using a mixed gas of N 2 , NH 3 and BCl 3 while maintaining a temperature of 500 ° C. to 1000 ° C. and a pressure of 0.2 Torr to 0.6 Torr. At this time, the mixed gas is used by mixing N 2 : NH 3 : BCl 3 at a flow rate ratio of 1 to 2: 10: 1 to 2, and the total flow rate of all the mixed gases is 300 sccm to 1000 sccm.

제1질화막(20)의 유전율은 유전상수가 2∼5의 값을 갖는다. The dielectric constant of the first nitride film 20 has a dielectric constant of 2-5.

또한, 제1질화막(20)의 두께는 후속 제2질화막을 포함하는 전체 질화막 총 두께의 20％∼25％가 되도록 형성한다. 예컨대, 전체 질화막의 총 두께가 100Å∼400Å일 경우 제1질화막(20)의 두께는 그의 20％∼25％인 20Å∼100Å으로 형성한다.Further, the thickness of the first nitride film 20 is formed to be 20% to 25% of the total thickness of the entire nitride film including the subsequent second nitride film. For example, when the total thickness of the entire nitride film is 100 kPa to 400 kPa, the thickness of the first nitride film 20 is formed to be 20 kPa to 100 kPa, which is 20% to 25%.

도 1d에 도시된 바와 같이, 제1질화막(20) 상에 제2질화막(21)을 형성한다. 여기서, 제2질화막(21)은 실리콘이 함유된 질화막으로 형성하여 스텝 커버리지를 확보하면서 비트라인패턴과 후속 스토리지 노드 콘택 플러그 간의 분리역할을 한다.As shown in FIG. 1D, a second nitride film 21 is formed on the first nitride film 20. In this case, the second nitride layer 21 is formed of a nitride layer containing silicon to secure step coverage while separating the bit line pattern and the subsequent storage node contact plug.

제2질화막(21)은 제1질화막(20)과 동일한 조건 즉, 500℃∼1000℃의 온도, 0.2Torr∼0.6Torr의 압력에서 형성한다. 그리고, N2, NH3 및 SiH2Cl2(디클로로실란, DCS:Dichloro silane)의 혼합가스를 사용하여 형성한다. 이때, 혼합가스는 N2:NH3:SiH2Cl2를 1∼2:10:1∼2의 유량비율로 혼합하여 사용하고, 전체 혼합가스의 총 유량은 300sccm∼1000sccm을 사용한다.The second nitride film 21 is formed under the same conditions as the first nitride film 20, that is, at a temperature of 500 ° C. to 1000 ° C. and at a pressure of 0.2 Torr to 0.6 Torr. And, it is formed using a mixed gas of N 2 , NH 3 and SiH 2 Cl 2 (dichlorosilane, DCS: Dichloro silane). In this case, the mixed gas is mixed with N 2 : NH 3 : SiH 2 Cl 2 at a flow rate ratio of 1 to 2: 10: 1 to 2, and the total flow rate of the entire mixed gas is 300 sccm to 1000 sccm.

제1 및 제2질화막(20, 21)의 전체 질화막 총 두께는 100Å∼400Å으로 형성한다. 이와 같이, 보론이 함유된 제1질화막(20)과 실리콘이 함유된 제2질화막(21) 을 적층하여 형성함으로써 절연을 위한 충분한 두께를 유지하면서 동시에 낮은 기생 캐패시턴스(Capacitance) 값을 가질 수 있다.The total thickness of the entire nitride film of the first and second nitride films 20 and 21 is formed to be 100 kPa to 400 kPa. In this way, the first nitride film 20 containing boron and the second nitride film 21 containing silicon are formed by laminating to maintain a sufficient thickness for insulation and at the same time have a low parasitic capacitance value.

도 1e에 도시된 바와 같이, 제1 및 제2질화막(20A, 21A)에 전면식각(Etch back)을 실시한다. 여기서, 전면식각은 하드마스크패턴(18) 상부 및 오픈부(19) 바닥의 제1 및 제2질화막(20A, 21A)을 식각하여 오픈부(19)의 측벽에만 잔류시키기 위한 것으로, 잔류된 제1 및 제2질화막(20A, 21A)은 측벽절연막 역할을 한다.As shown in FIG. 1E, etching back is performed on the first and second nitride films 20A and 21A. In this case, the front surface etching is performed to etch the first and second nitride films 20A and 21A on the top of the hard mask pattern 18 and the bottom of the open portion 19 so as to remain only on the sidewall of the open portion 19. The first and second nitride films 20A and 21A serve as sidewall insulating films.

따라서, 오픈부(19)의 측벽에 잔류하는 제1 및 제2질화막(20A, 21A)을 이하 '측벽절연막(100)'이라고 한다.Accordingly, the first and second nitride films 20A and 21A remaining on the sidewalls of the open portion 19 are referred to as `` side wall insulating film 100 ''.

도 1f에 도시된 바와 같이, 오픈부(19)를 매립하는 스토리지 노드 콘택 플러그(SNC Plug:Storage Node Contact Plug)(22)를 형성한다. 여기서, 스토리지 노드 콘택 플러그(22)는 오픈부(19)를 채우도록 도전물질을 형성하고 물리적식각을 실시하여 오픈부(19) 내부에만 잔류시킴으로써 형성한다. As illustrated in FIG. 1F, a storage node contact plug (SNC Plug) 22 filling the open portion 19 is formed. Here, the storage node contact plug 22 is formed by forming a conductive material to fill the open portion 19 and performing physical etching to remain only in the open portion 19.

물리적식각은 평탄화 공정으로 예컨대 전면식각(Etch Back) 또는 화학적기계적연마(Chemical Mechanical Polishing;CMP) 공정으로 실시한다.Physical etching may be performed by a planarization process, for example, by etching back or chemical mechanical polishing (CMP).

또한, 도전물질은 예컨대 폴리실리콘(Poly Silicon)으로 형성할 수 있다.In addition, the conductive material may be formed of, for example, polysilicon.

상기한 본 발명은 측벽절연막(100)을 보론이 함유된 제1질화막(20A)과 실리콘이 함유된 제2질화막(21A)의 적층구조로 형성함으로써 기생 캐패시턴스의 값을 낮추면서 동시에 스텝 커버리지의 악화를 방지할 수 있는 장점이 있다.According to the present invention, the sidewall insulating film 100 is formed as a laminated structure of the first nitride film 20A containing boron and the second nitride film 21A containing silicon, thereby lowering the value of parasitic capacitance and deteriorating step coverage. There is an advantage to prevent.

한편, 본 실시예는 스토리지 노드 콘택 플러그(22) 전에 형성되는 측벽절연 막(100)에서의 응용을 설명한 것으로, 본 발명의 기술적 사상은 스토리지 노드 콘택 플러그(22) 이외의 절연을 목적으로 하는 다른 측벽절연막에도 응용될 수 있다.On the other hand, the present embodiment has described the application in the sidewall insulating film 100 formed before the storage node contact plug 22, the technical idea of the present invention is another object for the purpose of insulation other than the storage node contact plug 22 It can also be applied to sidewall insulating films.

이렇듯, 본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.As such, although the technical idea of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상기한 본 발명은 비트라인패턴과 스토리지 노드 콘택 플러그 간의 기생 캐패시턴스 값의 감소와 동시에 측벽절연막의 스텝 커버리지 악화를 방지하여 소자 신뢰성을 향상시키는 효과가 있다.As described above, the parasitic capacitance value between the bit line pattern and the storage node contact plug is reduced, and the step coverage of the sidewall insulating layer is prevented from deteriorating, thereby improving device reliability.

Claims (12)

기판 상에 복수개의 도전패턴을 형성하는 단계; Forming a plurality of conductive patterns on the substrate; 상기 도전패턴 상에 절연층을 형성하는 단계;Forming an insulating layer on the conductive pattern; 상기 절연층을 식각하여 상기 도전패턴 사이에 오픈부를 형성하는 단계;Etching the insulating layer to form an open portion between the conductive patterns; 상기 오픈부의 측벽에 보론이 함유된 제1질화막과 실리콘이 함유된 제2질화막이 적층된 측벽절연막을 형성하는 단계; 및Forming a sidewall insulating film in which a first nitride film containing boron and a second nitride film containing silicon are stacked on sidewalls of the open portion; And 상기 오픈부를 매립하는 콘택 플러그를 형성하는 단계Forming a contact plug to bury the open portion 를 포함하는 반도체 소자 제조방법.Semiconductor device manufacturing method comprising a. 삭제delete 제1항에 있어서,The method of claim 1, 상기 측벽절연막을 형성하는 단계는,Forming the sidewall insulating film, 상기 오픈부를 포함하는 결과물의 전면에 제1질화막을 형성하는 단계;Forming a first nitride film on the entire surface of the resultant including the open part; 상기 제1질화막 상에 제2질화막을 형성하는 단계; 및Forming a second nitride film on the first nitride film; And 전면식각을 실시하여 상기 제1 및 제2질화막의 오픈부 측벽에만 잔류시키는 단계Performing surface etching and leaving only the sidewalls of the open portions of the first and second nitride layers. 를 포함하는 것을 특징으로 하는 반도체 소자 제조방법.Semiconductor device manufacturing method comprising a. 제3항에 있어서,The method of claim 3, 상기 제1질화막은 제1 및 제2질화막의 총 두께에 20％∼25％의 두께로 형성하는 것을 특징으로 하는 반도체 소자 제조방법.The first nitride film is a semiconductor device manufacturing method, characterized in that formed in the total thickness of the first and second nitride film with a thickness of 20% to 25%. 제4항에 있어서,The method of claim 4, wherein 상기 제1 및 제2질화막의 총 두께는 100Å∼400Å, 상기 제1질화막의 두께는 20Å∼100Å, 상기 제2질화막의 두께는 80Å∼300Å으로 형성하는 것을 특징으로 하는 반도체 소자 제조방법.Wherein the total thickness of the first and second nitride films is 100 kPa to 400 kPa, the thickness of the first nitride film is 20 kPa to 100 kPa, and the thickness of the second nitride film is 80 kPa to 300 kPa. 제3항에 있어서,The method of claim 3, 상기 제1질화막의 유전율은 유전상수가 2∼5의 값을 갖는 것을 특징으로 하는 반도체 소자 제조방법.The dielectric constant of the first nitride film has a dielectric constant of 2 to 5, characterized in that the semiconductor device manufacturing method. 제6항에 있어서,The method of claim 6, 상기 제1질화막은 N2, NH3 및 BCl3의 혼합가스를 이용하여 형성하는 것을 특징으로 하는 반도체 소자 제조방법.The first nitride film is a semiconductor device manufacturing method characterized in that formed using a mixed gas of N 2 , NH 3 and BCl 3 . 제7항에 있어서,The method of claim 7, wherein 상기 혼합가스는 N2:NH3:BCl3를 1∼2:10:1∼2의 유량비율로 혼합하되 전체 혼합가스는 300sccm∼1000sccm의 유량을 사용하는 것을 특징으로 하는 반도체 소자 제조방법.The mixed gas is mixed with N 2 : NH 3 : BCl 3 at a flow rate ratio of 1 to 2: 10: 1 to 2, the total mixed gas is a semiconductor device manufacturing method characterized in that using a flow rate of 300sccm to 1000sccm. 제3항에 있어서,The method of claim 3, 상기 제2질화막은 N2, NH3 및 SiH2Cl2의 혼합가스를 이용하여 형성하는 것을 특징으로 하는 반도체 소자 제조방법.The second nitride film is a semiconductor device manufacturing method, characterized in that formed using a mixed gas of N 2 , NH 3 and SiH 2 Cl 2 . 제9항에 있어서,The method of claim 9, 상기 혼합가스는 N2:NH3:SiH2Cl2를 1∼2:10:1∼2의 유량비율로 혼합하되 전체 혼합가스는 300sccm∼1000sccm의 유량을 사용하는 것을 특징으로 하는 반도체 소자 제조방법.The mixed gas is mixed with N 2 : NH 3 : SiH 2 Cl 2 at a flow rate ratio of 1 to 2: 10: 1 to 2, but the total mixed gas is a flow rate of 300sccm to 1000sccm . 제3항에 있어서,The method of claim 3, 상기 제1 및 제2질화막은 500℃∼1000℃의 온도에서 0.2Torr∼0.6Torr의 압력을 인가하여 형성하는 것을 특징으로 하는 반도체 소자 제조방법.The first and second nitride films are formed by applying a pressure of 0.2 Torr to 0.6 Torr at a temperature of 500 ℃ to 1000 ℃. 제1항에 있어서,The method of claim 1, 상기 도전패턴은 비트라인패턴인 것을 특징으로 하는 반도체 소자 제조방법.The conductive pattern is a semiconductor device manufacturing method, characterized in that the bit line pattern.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000027444A (en) * 1998-10-28 2000-05-15 윤종용 Method for forming contact hole of semiconductor device
KR20040003168A (en) * 2002-06-29 2004-01-13 삼성전자주식회사 Method for forming contact plug of semiconductor device
KR20040079171A (en) * 2003-03-06 2004-09-14 주식회사 하이닉스반도체 Method for manufacturing semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000027444A (en) * 1998-10-28 2000-05-15 윤종용 Method for forming contact hole of semiconductor device
KR20040003168A (en) * 2002-06-29 2004-01-13 삼성전자주식회사 Method for forming contact plug of semiconductor device
KR20040079171A (en) * 2003-03-06 2004-09-14 주식회사 하이닉스반도체 Method for manufacturing semiconductor device

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