TWI588973B - Memory device and method of manufacturing the same - Google Patents

Description

Memory element and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a memory device and a method of fabricating the same.

With the rapid development of technology, it has become a trend to increase the accumulation of memory components and reduce the critical size. Under this trend, memory components often suffer from problems of WL leakage, BL short, and high-temperature data retention (HTDR).

For example, as shown in FIG. 1, when the source structure 34 is formed between the word lines 12, since the top critical dimension of the source structure 34 is larger than its bottom critical dimension, it causes the sidewalls of the source structure 34 to be easily formed. Corner 10. The tip end of the sharp corner 10 protrudes toward the word line 12, which is prone to leakage current, which causes a word line leakage problem. In addition, titanium metal residues or metal oxide particles on the dielectric layer between the bit lines are also liable to cause a short circuit of the bit lines.

The invention provides a memory element having a concave structure and a manufacturing method thereof, which can solve the problem that the word line leakage, the bit line short circuit and the high temperature data are not maintained well.

The present invention provides a memory element having a recessed structure and a method of manufacturing the same, which can reduce process cost and improve product yield.

The present invention provides a memory element comprising: a substrate, at least two stacked structures, a conductor structure, and a recessed structure. The stacked structure is on the substrate. The conductor structure is located between the stacked structures. The recessed structure is located on the conductor structure. The bottom surface of the recessed structure is at least lower than the top surface of the stacked structure.

In an embodiment of the invention, the thickness of the top surface to the bottom surface of the recess structure is between 80 nm and 120 nm.

In an embodiment of the invention, the memory component further includes: two cap layers and a spacer. The top cover layers are respectively located on the stacked structure. The spacer is located between the stacked structure and the conductor structure. .

In an embodiment of the invention, the top surface of the recessed structure and the top surface of the cap layer are coplanar.

In an embodiment of the invention, the recessed structure exposes at least a surface of the spacer.

In an embodiment of the invention, each of the cap layers has a thickness between 30 nm and 70 nm.

In an embodiment of the invention, each of the stacked structures includes a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer, a control gate, and a dielectric layer.

In an embodiment of the invention, the bottom surface of the recessed structure is higher than the top surface of the control gate.

In an embodiment of the invention, the shape of the recessed structure is semicircular, rectangular or a combination thereof.

In an embodiment of the invention, the recessed structure comprises a single layer structure, a two layer structure or a multilayer structure.

In an embodiment of the invention, the material of the recess structure comprises tantalum nitride, tantalum oxide or a combination thereof.

In an embodiment of the invention, the conductor structure is a source structure.

In an embodiment of the invention, the memory element further includes a metal interconnect on the recessed structure.

The present invention provides a method of manufacturing a memory element, the steps of which are as follows. At least two stacked structures are formed on the substrate. Two cap layers are respectively formed on the stack structure. A conductor structure is formed between the stacked structures. A spacer is formed between the stacked structure and the conductor structure. A recessed structure is formed on the conductor structure. The bottom surface of the recessed structure is at least lower than the top surface of the stacked structure.

In an embodiment of the invention, the step of forming the conductor structure is as follows. A layer of conductive material is formed on the substrate. A layer of conductive material fills the space between the stacked structures and covers the surface of the cap layer. A planarization process is performed to remove a portion of the layer of conductor material and a portion of the cap layer.

In an embodiment of the invention, the planarization process includes a chemical mechanical polishing (CMP) process, an etch back process, or a combination thereof.

In an embodiment of the invention, the step of forming the recessed structure is as follows. A patterned mask layer is formed on the substrate. The patterned mask layer has an opening. The opening exposes at least the top surface of the conductor structure. An etching process is performed to remove a portion of the conductor structure and a portion of the cap layer to form a recessed opening. The recessed opening exposes at least the surface of the spacer. At least one layer of dielectric material is formed and filled into the recessed opening.

The present invention further provides a method of manufacturing a memory element, the steps of which are as follows. A plurality of conductor structures are formed on the substrate. A plurality of dielectric layers are formed between the conductor structures. A metal layer is formed on the conductor structure and the dielectric layer. A patterned mask layer is formed on the metal layer. The patterned mask layer has a plurality of openings. The openings respectively correspond to the top surface of the dielectric layer. With the patterned mask layer as the curtain layer, a portion of the dielectric layer is removed such that the top surface of the dielectric layer is lower than the top surface of the conductor structure.

In an embodiment of the invention, the distance between the top surface of the dielectric layer and the top surface of the conductor structure is between 10 nm and 40 nm.

In an embodiment of the invention, the conductor structure is a bit line.

Based on the above, the present invention solves the problem of word line leakage by the recessed structure on the source structure, which can remove the sharp corners of the prior art. In addition, in the present invention, the recess structure on the source structure and the cap layer on the word line can increase the high temperature data retention (HTDR) capability and thereby increase the yield. In addition, the present invention removes the process steps of the prior art contact window, which not only solves the problem of short-circuiting of the bit line caused by the residual titanium metal on the dielectric layer between the bit lines, but also reduces the process cost.

The above described features and advantages of the invention will be apparent from the following description.

The invention will be more fully described with reference to the drawings of the embodiments. However, the invention may be embodied in a variety of different forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings will be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not be repeated.

2A through 2J are schematic cross-sectional views showing a manufacturing process of a memory element in accordance with a first embodiment of the present invention.

Referring to FIG. 2A, a first embodiment of the present invention provides a method of fabricating a memory device, the steps of which are as follows. First, a substrate 100 is provided. In the present embodiment, the substrate 100 may be, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor substrate (SOI) on the insulating layer.

Next, a plurality of stacked structures 102 are formed on the substrate 100. In detail, the stacked structure 102 is sequentially formed by the tunneling dielectric layer 104, the floating gate 106, the inter-gate dielectric layer 108, the first control gate 110, the second control gate 112, and the dielectric layers 114, 116. Stacked. In the present embodiment, the material of the tunneling dielectric layer 104 may be, for example, cerium oxide, and the forming method may be a chemical vapor deposition method, a thermal oxidation method, or the like. The material of the floating gate 106 may be, for example, a doped polysilicon, an undoped polysilicon or a combination thereof, which may be formed by chemical vapor deposition. The inter-gate dielectric layer 108 can be, for example, a composite layer composed of an oxide layer/nitride layer/oxide layer (Oxide/Nitride/Oxide, ONO), and the composite layer can be three or more layers, and the present invention does not To be limited thereto, the formation method thereof may be, for example, a chemical vapor deposition method. The material of the first control gate 110 may be, for example, doped polysilicon, undoped polysilicon or a combination thereof, and the formation method may be chemical vapor deposition. A second control gate material 112 may be, for example, a metal silicide, the metal silicide may be, for example, tungsten silicide (WSi _x), which may be a method of forming a chemical vapor deposition method. The dielectric layers 114, 116 can be, for example, a single layer structure, a two layer structure, or a multilayer structure. In this embodiment, the material of the dielectric layer 114 may be, for example, tantalum nitride; the material of the dielectric layer 116 may be, for example, ruthenium oxide, tetraethoxy decane (TEOS) oxide, or a combination thereof. The method of forming the dielectric layers 114, 116 may be a chemical vapor deposition method.

Thereafter, spacers 118 are formed on both sides of the stacked structure 102. In detail, the spacers 118 may be, for example, a single layer structure, a two layer structure, or a multilayer structure. In the present embodiment, the spacers 118 may be, for example, a three-layer structure, and the oxide layer 120, the nitride layer 122, and the oxide layer 124 may be sequentially extended from the inner side of the stacked structure 102. The material of the oxide layer 120 may be, for example, a high temperature oxide (HTO); the material of the nitride layer 122 may be, for example, tantalum nitride; the material of the oxide layer 124 may be, for example, a tetraethoxy decane (TEOS) oxide. Methods of forming oxide layer 120, nitride layer 122, and oxide layer 124 are well known to those of ordinary skill in the art and will not be described in detail herein.

Then, a cap layer 126 is formed on the stacked structure 102, respectively. The material of the cap layer 126 may be, for example, tantalum nitride, an oxide, or a combination thereof, which may be formed by chemical vapor deposition.

Next, a barrier layer 128 is conformally formed on the stacked structure 102 and the cap layer 126. The material of the barrier layer 128 may be, for example, titanium (Ti), titanium nitride (TiN), or a combination thereof, which may be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition (ALD).

Thereafter, a conductive material layer 130 is formed on the substrate 100. The layer of conductive material 130 fills the space between the stacked structures 102 and covers the surfaces of the stacked structures 102 and the cap layer 126. The material of the conductor material layer 130 may be, for example, tungsten (W), which may be formed by physical vapor deposition.

Referring to FIG. 2A and FIG. 2B, a planarization process is performed to remove a portion of the conductive material layer 130, a portion of the barrier layer 128, and a portion of the cap layer 126 to form conductor structures 132, 134 between the stacked structures 102, respectively. In an embodiment, the planarization process can be, for example, a chemical mechanical polishing process, an etch back process, or a combination thereof. In this embodiment, the thickness of the cap layer 126a can be controlled by adjusting the overetching step of the CMP process. When the thickness of the cap layer 126a composed of tantalum nitride is thicker, the high temperature data retention capability of the memory element is better. In an embodiment, the thickness T1 of the cap layer 126a may be between 30 nm and 70 nm.

It should be noted that in the present embodiment, the conductor structure 132 can be regarded as a drain structure (hereinafter referred to as a drain structure 132); and the conductor structure 134 can be regarded as a source structure (hereinafter referred to as a source structure 134). Although FIG. 2A does not illustrate the layout of the drain structure 132 and the source structure 134, the drain structure 132 may be, for example, a plurality of columnar structures arranged in a direction perpendicular to the plane of the paper, as viewed from above. From the top view, the source structure 134 can be, for example, a sheet-like structure extending in a direction perpendicular to the plane of the paper, wherein the source structure 134 and the drain structure 132 are aligned with each other in a direction parallel to the plane of the paper. In the present embodiment, the gate structure 132 of every 128 columnar structures corresponds to the source structure 134 of one sheet structure. A source structure 134 having a columnar structure between the source structures 134 of each two sheet structures is electrically connected to the subsequent metal interconnects. On the other hand, the conductor structure 132 can be regarded as a bit line; and the stacked structure 102 can be regarded as a word line.

Referring to FIG. 2B and FIG. 2C, an oxide layer 136 and a patterned mask layer 138 are sequentially formed on the substrate 100. The patterned mask layer 138 has an opening 140. The opening 140 exposes at least the top surface of the source structure 134. In one embodiment, the width W of the opening 140 can be adjusted by the critical dimension exposure capability of the lithography exposure station. As can be seen from FIG. 2C, the width W can also be greater than the top surface width of the source structure 134. In one embodiment, the material of the patterned mask layer 138 can be, for example, a photoresist material or a material having a high etching selectivity compared to the oxide layer 136. The method of forming the patterned mask layer 138 may be, for example, a spin coating method or a chemical vapor deposition method.

Referring to FIG. 2C and FIG. 2D , an etching process is performed by patterning the mask layer 138 as a mask to remove a portion of the oxide layer 136 , a portion of the source structure 134 and a portion of the cap layer 126 a to form the recess opening 142 . In an embodiment, the etching process may be, for example, a dry etching process, which may be Reactive Ion Etching (RIE). In detail, the recessed opening 142 is located below the opening 140, and the recessed opening 142 exposes at least the surface of the spacer 118a (or the nitrided layer 122a). The bottom surface of the recessed opening 142 may be at least lower than the top surface of the stacked structure 102; on the other hand, the bottom surface of the recessed opening 142 may also be higher than the top surface of the second control gate 112. In an embodiment, the depth D of the recessed opening 142 (ie, the distance from the top surface of the cap layer 126b to the bottom surface of the recessed opening 142) may be between 80 nm and 120 nm. In an embodiment, the shape of the recessed opening 142 can be, for example, a semicircle, a rectangle, or a combination thereof. It should be noted that in the present embodiment, the recessed opening 142 can remove the sharp corners 10 of the prior art (as shown in FIG. 1) to solve the word line leakage problem.

Referring to FIG. 2E and FIG. 2F, after the patterned mask layer 138 is removed, a dielectric material layer 144 is conformally formed on the substrate 100 and covers the surface of the recess opening 142 and the oxide layer 136a. In an embodiment, the dielectric material layer 144 may be, for example, tantalum nitride, and may have a thickness of, for example, between 100 Å and 400 Å. The method of forming the dielectric material layer 144 may be chemical vapor deposition or atomic layer deposition (ALD). Thereafter, a layer of dielectric material 146 is formed over dielectric material layer 144. In one embodiment, the dielectric material layer 146 can be, for example, hafnium oxide, TEOS antimony oxide, spin-on silicon oxide, tantalum nitride, or a combination thereof, and the thickness can be, for example, 1000 Å to 1500. Between Å. The method of forming the dielectric material layer 146 may be a chemical vapor deposition method. Incidentally, since the dielectric material layer 146 is filled in the recessed opening 142, the dielectric material layer 146 has a recess 148 corresponding to the surface above the recessed opening 142.

Referring to FIG. 2F and FIG. 2G, a planarization process is performed to remove a portion of the dielectric material layer 146 to expose the surface of the dielectric material layer 144. In an embodiment, the planarization process can be, for example, a chemical mechanical polishing process, an etch back process, or a combination thereof.

Referring to FIG. 2H and FIG. 2I, a first etching step is performed to remove portions of the dielectric material layers 144, 146a to expose the surface of the oxide layer 136a. In one embodiment, the first etch step can be, for example, a dry etch process with an oxide to nitride etch selectivity ratio of about 1:1. Next, a second etching step is performed to remove the oxide layer 136a to expose the surface of the cap layer 126b. In one embodiment, the second etch step can be, for example, a dry etch process with an oxide to nitride etch selectivity ratio of about 3:1.

It should be noted that the dielectric material layers 144a, 146b filled in the recess openings 142 can be considered as recess structures 145. Although FIG. 2I does not illustrate the layout of the source structure 134a, the recess structure 145 is similar to the source structure 134a from the top view direction, which may be, for example, a strip structure located at the source structure of the sheet structure. On 134a, and extending in a direction perpendicular to the plane of the paper. Since the recess structures 145 are located on the source structures 134a between adjacent stacked structures 102, they can electrically insulate adjacent stack structures 102 to account for word line leakage problems. Additionally, the dielectric material layer 144a of the recess structure 145 can be, for example, tantalum nitride, which can increase high temperature data retention (HTDR) capability and thereby increase yield.

Referring to FIG. 2I and FIG. 2J, the conductor layer 150, the metal layer 152, the conductor layer 154, and the mask layers 156, 158 are sequentially formed on the recess structure 145. In an embodiment, conductor layer 150, metal layer 152, and conductor layer 154 may be, for example, metal interconnects. In detail, the material of the conductor layer 150 may be, for example, titanium (Ti), which may be formed by physical vapor deposition. The material of the metal layer 152 may be, for example, aluminum, copper, or a combination thereof, and the forming method may be physical vapor deposition. The material of the conductor layer 154 may be, for example, titanium (Ti), titanium nitride (TiN), or a combination thereof, which may be formed by physical vapor deposition or chemical vapor deposition. The material of the mask layers 156, 158 may be, for example, bismuth oxynitride, a photoresist material, or a combination thereof, which may be formed by chemical vapor deposition.

Referring back to FIG. 2J, a first embodiment of the present invention provides a memory device including: a substrate 100, a plurality of stacked structures 102, a spacers 118a, a cap layer 126b, a drain structure 132, a source structure 134a, and a recess structure 145. The stack structure 102 is located on the substrate 100. The drain structure 132 and the source structure 134a are respectively located between the stacked structures 102. In other words, there is a stacked structure 102 between the drain structure 132 and the source structure 134a. The recessed structure 145 is located on the source structure 134a. The bottom surface of the recessed structure 145 is at least lower than the top surface of the stacked structure 102, and the bottom surface of the recessed structure 145 may also be higher than the top surface of the second control gate 112. In an embodiment, the thickness T2 of the recess structure 145 may be between 80 nm and 120 nm, wherein the top surface of the recess structure 145 is coplanar with the top surface of the cap layer 126b. In addition, the memory element of the present embodiment further includes a conductor layer 150, a metal layer 152, and a conductor layer 154 (which may be, for example, a metal interconnect) on the recess structure 145.

3A to 3B are schematic cross-sectional views showing a manufacturing process of a memory element in accordance with a second embodiment of the present invention.

Referring to Figures 3A and 3B, the method according to the above embodiment proceeds to form the mask layers 156, 158 of Figure 2J. In order to simplify the drawing, in FIGS. 3A to 3B, only a schematic cross-sectional view of the gate structure 132 of FIG. 2J along a direction perpendicular to the plane of the paper is illustrated, and the stack structure 102 and the source structure of FIG. 2J are not illustrated. 134a. In this cross section, the substrate 100 has a plurality of isolation structures 101 therein. The substrate 100 between adjacent isolation structures 101 can be considered as the active area AA. In an embodiment, the material of the isolation structure 101 can be, for example, doped or undoped cerium oxide, high density plasma oxide, cerium oxynitride, spin-on silicon oxide, low dielectric. Electrically constant dielectric material (Low-k dielectric) or a combination thereof. The isolation structure 101 can be, for example, a shallow trench isolation structure.

The drain structures 132 are respectively located on the active area AA. There is a dielectric layer 126c between the drain structures 132. In the present embodiment, the dielectric layer 126c is formed simultaneously with the cap layer 126 of FIG. 2A. Since the materials and formation methods of the drain structure 132 and the dielectric layer 126c have been described in the above paragraphs, they will not be described again.

The conductor layer 150, the metal layer 152, the conductor layer 154, and the mask layer 156 are sequentially formed on the dielectric layer 126c and the gate structure 132 from bottom to top. Next, the mask layer 158 is patterned to form a plurality of openings 160. Opening 160 corresponds to the top surface of dielectric layer 126c.

It should be noted that the particles or metal oxide particles remaining in the polishing liquid in the CMP process of FIG. 2F to FIG. 2I are easily accumulated on the top surface of the dielectric layer 126c, so after the subsequent deposition process, A portion of the dielectric layer 126c, a portion of the conductor layer 150, a portion of the metal layer 152, a portion of the conductor layer 154, and a portion of the mask layer 156 are caused to protrude, thereby forming a projection 162 (shown in FIG. 3A).

3A and FIG. 3B, an etching process is performed to pattern a mask layer 158a as a curtain layer to remove a portion of the mask layer 156, a portion of the conductor layer 154, a portion of the metal layer 152, a portion of the conductor layer 150, and portions. The dielectric layer 126c is such that the top surface of the dielectric layer 126d is lower than the top surface of the drain structure 132. In an embodiment, the distance (or height difference) H between the top surface of the dielectric layer 126d and the top surface of the drain structure 132 may be between 10 nm and 40 nm. In an embodiment, the etching process can be, for example, a dry etching process. As shown in FIG. 3B, the conductor layer 150a, the metal layer 152a, and the conductor layer 154a may be, for example, a metal interconnect line M1. In other words, the gate structure 132 of the present embodiment is in direct contact with the metal interconnection M1, and the gate structure 132 and the metal interconnection M1 do not have a contact window or the like.

In this embodiment, the protrusions 162 can be removed by an over etching step in the etching process. As a result, in the present embodiment, the problem of short-circuiting the drain structure 132 (bit line) caused by the residual of the conductor layer 150 (titanium metal) can be solved by the above-described over-etching step.

In addition, this embodiment can remove the process steps of the contact window CT in the prior art, which can not only solve the residual layer of the conductor layer 150 (titanium metal) on the dielectric layer 126d between the drain structures 132 (bit lines). The problem of shorting the bit line can also reduce process cost and increase yield.

In summary, the present invention solves the problem of word line leakage by the recessed structure on the source structure, which can remove the sharp corners of the prior art. In addition, in the present invention, the recess structure on the source structure and the cap layer on the word line can increase the high temperature data retention capability and thereby increase the yield. In addition, the present invention removes the process steps of the prior art contact window, which not only solves the problem of short-circuiting of the bit line caused by the residual titanium metal on the dielectric layer between the bit lines, but also reduces the process cost.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧ sharp corner

12‧‧‧ character line

34‧‧‧Source structure

100‧‧‧Base

102‧‧‧Stack structure, word line

104‧‧‧Tunnel dielectric layer

106‧‧‧Floating gate

108‧‧‧Interruptor dielectric layer

110‧‧‧First control gate

112‧‧‧Second control gate

114, 116, 126c, 126d‧‧‧ dielectric layer

118, 118a‧‧ ‧ spacer

120, 120a, 124, 124a, 136‧‧ ‧ oxide layer

122, 122a‧‧‧ nitride layer

126, 126a, 126b‧‧‧ top cover

128, 128a‧‧‧ barrier layer

130‧‧‧Conductor layer

132‧‧‧汲pole structure, conductor structure, bit line

134, 134a‧‧‧ source structure, conductor structure, bit line

138, 158a‧‧‧ patterned mask layer

140‧‧‧ openings

142‧‧‧ recessed opening

144, 144a, 146, 146b‧‧‧ dielectric material layer

145‧‧‧ recessed structure

148‧‧‧ dent

150, 154‧‧‧ conductor layer

152‧‧‧metal layer

156, 158‧‧ ‧ cover layer

162‧‧‧protrusion

CT‧‧‧Contact Window

D‧‧‧Deep

H‧‧‧ distance

M1‧‧‧Metal interconnection

T1, T2‧‧‧ thickness

W‧‧‧Width

1 is a schematic cross-sectional view of a conventional memory element. 2A through 2J are schematic cross-sectional views showing a manufacturing process of a memory element in accordance with a first embodiment of the present invention. 3A to 3B are schematic cross-sectional views showing a manufacturing process of a memory element in accordance with a second embodiment of the present invention.

100‧‧‧Base

102‧‧‧Stack structure

104‧‧‧Tunnel dielectric layer

106‧‧‧Floating gate

108‧‧‧Interruptor dielectric layer

110‧‧‧First control gate

112‧‧‧Second control gate

114, 116‧‧‧ dielectric layer

118a‧‧‧ clearance

120a, 124a‧‧‧ oxide layer

122a‧‧‧ nitride layer

126b‧‧‧Top cover

128a‧‧‧Barrier layer

132‧‧‧汲polar structure

134a‧‧‧ source structure

144a, 146b‧‧‧ dielectric material layer

145‧‧‧ recessed structure

150, 154‧‧‧ conductor layer

152‧‧‧metal layer

156, 158‧‧ ‧ cover layer

T2‧‧‧ thickness

Claims (19)

A memory device comprising: at least two stacked structures on a substrate, wherein each of the stacked structures comprises a floating gate, an inter-gate dielectric layer and a control gate; a conductor structure located on the stack Between the structures; and a recessed structure on the conductor structure, wherein the bottom surface of the recessed structure is at least lower than the top surface of the stacked structures. The memory device of claim 1, wherein a thickness from a top surface to a bottom surface of the recess structure is between 80 nm and 120 nm. The memory device of claim 1, further comprising: two top cover layers respectively located on the stacked structures; a spacer wall between the stacked structures and the conductive structure. The memory element of claim 3, wherein the top surface of the recessed structure and the top surface of the cap layers are coplanar. The memory element of claim 3, wherein the recessed structure exposes at least a surface of the spacer. The memory element of claim 3, wherein each of the cap layers has a thickness of between 30 nm and 70 nm. The memory device of claim 1, wherein each of the stacked structures further comprises a tunneling dielectric layer and a dielectric layer. The memory device of claim 1, wherein the bottom surface of the recessed structure is higher than a top surface of the control gate. The memory element of claim 1, wherein the recessed structure has a semicircular shape, a rectangular shape, or a combination thereof. The memory element of claim 1, wherein the recessed structure comprises a single layer structure, a two layer structure or a multilayer structure. The memory element of claim 1, wherein the material of the recessed structure comprises tantalum nitride, tantalum oxide or a combination thereof. The memory element of claim 1, wherein the conductor structure is a source structure. The memory component of claim 1, further comprising a metal interconnect on the recessed structure. A method of fabricating a memory device, comprising: forming at least two stacked structures on a substrate, wherein each of the stacked structures comprises a floating gate, an inter-gate dielectric layer, and a control gate; and the stacked structures Forming two top cover layers respectively; forming a conductor structure between the stacked structures; forming a gap between the stacked structures and the conductor structure; and forming a recessed structure on the conductor structure, wherein the The bottom surface of the recessed structure is at least lower than the top surface of the stacked structures. The method of manufacturing a memory device according to claim 14, wherein the step of forming the conductor structure comprises: forming a layer of a conductor material on the substrate, the layer of conductor material filling a space between the stacked structures and Covering the surfaces of the cap layers; and performing a planarization process to remove portions of the layer of conductive material and portions of the cap layers. The method of manufacturing a memory device according to claim 15, wherein the planarization process comprises a chemical mechanical polishing process, an etch back process, or a combination thereof. The method of manufacturing the memory device of claim 14, wherein the forming the recessed structure comprises: forming a patterned mask layer on the substrate, the patterned mask layer having an opening, the opening being at least Exposing a top surface of the conductor structure; performing an etching process to remove a portion of the conductor structure and a portion of the cap layers to form a recess opening, the recess opening exposing at least a surface of the spacer; and forming at least one A layer of electrically material is filled into the recessed opening. A method for manufacturing a memory device, comprising: forming a plurality of conductor structures on a substrate; forming a plurality of dielectric layers between the conductor structures; forming a metal layer on the conductor structures and the dielectric layers; Forming a patterned mask layer on the metal layer, the patterned mask layer having a plurality of openings respectively corresponding to the top surfaces of the dielectric layers; and the patterned mask layer as a curtain layer Removing a portion of the dielectric layers such that a top surface of the dielectric layers is lower than a top surface of the conductor structures, wherein between the top surface of the dielectric layers and the top surface of the conductor structures The distance is between 10 nm and 40 nm. The method of manufacturing a memory device according to claim 18, wherein the conductor structures are bit lines.