CN104795396B - Flash memory and its manufacturing method - Google Patents
Flash memory and its manufacturing method Download PDFInfo
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- CN104795396B CN104795396B CN201410026977.0A CN201410026977A CN104795396B CN 104795396 B CN104795396 B CN 104795396B CN 201410026977 A CN201410026977 A CN 201410026977A CN 104795396 B CN104795396 B CN 104795396B
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Abstract
The invention discloses a kind of flash memory, including substrate, first grid structure, source area and drain region, self-aligning contact window, the first dielectric layer and the second dielectric layer.First grid structure is located on the cell region of substrate.Source area is located in the interstructural substrate of first grid of cell region respectively with drain region.Self-aligning contact window is located between first grid structure on source area and drain region.First dielectric layer surrounds self-aligning contact window, and has recess at corresponding first grid structure.Second dielectric layer is located in the first dielectric layer, and fills up recess, and the dielectric constant of the second dielectric layer is less than the dielectric constant of the first dielectric layer.
Description
Technical field
The present invention relates to a kind of memory component and its manufacturing method, and more particularly to a kind of flash memory and its manufacture
Method.
Background technology
In flash memory（flash memory）Manufacturing process in, the dielectric constant of interlayer dielectric layer is excessively high easily to be made
Into Drain Disturbance（drain disturb）, and occur reading failure（read fail）And bit line reciprocal effect（BL-BL
coupling effect）The problem of.
Invention content
The embodiment of the present invention proposes that a kind of flash memory and its manufacturing method, the dielectric that can reduce interlayer dielectric layer are normal
Number, declines parasitic capacitance, and then the problem of reading failure caused by reduction Drain Disturbance and bit line reciprocal effect.
The embodiment of the present invention proposes a kind of flash memory, including：Substrate, multiple first grid structures, plurality of source regions
With drain region, multiple self-aligning contact windows, the first dielectric layer and the second dielectric layer.First grid structure is located at the crystalline substance of substrate
In born of the same parents area.Source area and drain region are located at respectively in the substrate between the first grid structure of cell region.Self-aligning contact window
Between first grid structure, and on source area and drain region.First dielectric layer surround self-aligning contact window, and
There is recess at corresponding first grid structure.Second dielectric layer is located in the first dielectric layer, and fills up recess, the second dielectric layer
Dielectric constant is less than the dielectric constant of the first dielectric layer.
The bright Real of this Hair of Yi Zhao are applied described in example, and the top surface of second dielectric layer is higher than the top surface of first dielectric layer.
The bright Real of this Hair of Yi Zhao are applied described in example, and first dielectric layer includes silicon nitride.
The bright Real of this Hair of Yi Zhao are applied described in example, and second dielectric layer includes silica.
The bright Real of this Hair of Yi Zhao are applied described in example, and the silica includes spin-on glasses.
The embodiment of the present invention also proposes a kind of manufacturing method of flash memory, and including providing substrate, substrate includes structure cell
Area.Multiple first grid structures are formed on the cell region of substrate.Source area is formed in substrate between first grid structure
With drain region.Form patterned conductor layer on substrate, cover first grid structure and at least fill up first grid structure it
Between gap.Multiple virtual self-aligning contact window plugs are formed on substrate between first grid structure, it is virtually voluntarily right
Quasi- contact window plug is located on source area and drain region, and forms multiple open around virtual self-aligning contact window plug
Mouthful.The first dielectric layer is formed in virtual self-aligning contact window plug and open surfaces.Second is formed on the first dielectric layer
Dielectric layer, the second dielectric layer fills up opening, and the dielectric constant of the second dielectric layer is less than the dielectric constant of the first dielectric layer.It removes
Virtual self-aligning contact window plug, forms multiple self-aligning contact windows.
It is applied described in example according to according to the bright Real of this Hair, the manufacturing method of the flash memory further includes shape over the substrate
Into a stop-layer, the patterned conductor layer and the second grid structure are covered.
It is applied described in example according to according to the bright Real of this Hair, the manufacturing method of the flash memory, wherein the first dielectric layer packet
Include silicon nitride.
It is applied described in example according to according to the bright Real of this Hair, the manufacturing method of the flash memory, wherein the second dielectric layer packet
Include silica.
It is applied described in example according to according to the bright Real of this Hair, the manufacturing method of the flash memory, wherein the silica includes rotation
Painting formula glass, high-density electric slurry oxide silicon use what high depth was formed than filling out the chemical vapour deposition technique of ditch manufacturing process system
Silica.
The flash memory and its manufacturing method of the embodiment of the present invention, can reduce the dielectric constant of interlayer dielectric layer, make
Parasitic capacitance declines, and then the problem of reading failure caused by reduction Drain Disturbance and bit line reciprocal effect.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed that attached drawing is coordinated to make
Carefully it is described as follows.
Description of the drawings
Figure 1A to 1H is the diagrammatic cross-section of the manufacturing process of the flash memory according to depicted in the embodiment of the present invention.
Wherein, the reference numerals are as follows：
100：Substrate
100a：Cell region
100b：Peripheral region
102、110：Gate structure
103：Tunnel oxide
104、106、112：Conductor layer
105：Dielectric layer between grid
107、113：Metal silicide layer
108、114：Lower mask layer
109、115：Upper mask layer
111：Gate dielectric layer
116：Stop-layer
117：Lining
116a、117a、118、119：Clearance wall
120：Stop-layer
122、132、132a、132b、136、136a：Dielectric layer
124：Conductor layer
125：Mask layer
126：Cap layer
127：Virtual self-aligning contact window plug
128：Opening
133、137：Source area
134：Recess
135、139：Drain region
143、145：Self-aligning contact window is open
148：Grid contact window is open
153、155、158：Contact window plug
Specific embodiment
Figure 1A to 1H is the diagrammatic cross-section of the manufacturing process of the flash memory according to depicted in the embodiment of the present invention.
Figure 1A is please referred to, substrate 100 is provided.Substrate 100 can be semiconductor or semiconducting compound, such as N-type or P
Silicon substrate, three-five Semiconductor substrate or the germanium silicide of type.Substrate 100 can also be silicon-on-insulator（silicon on
Insulator, SOI）.Substrate 100 has cell region 100a and peripheral region 100b.It is formed on the substrate 100 of cell region 100a
Most gate structures 102, and in forming an at least gate structure 110 on the substrate 100 of peripheral region 100b.
Gate structure 102 can be the grid of the gate structure of non-volatile memory device, e.g. flash memory devices
Structure, for example be to include sequentially stacking dielectric layer 105 between tunnel oxide 103 on the substrate 100, conductor layer 104, grid and lead
Body layer 106.The material of tunnel oxide 103 is, for example, silica.Conductor layer 104 is used as floating grid, and material is, for example, to mix
Miscellaneous polysilicon.Dielectric layer 105 is, for example, silica, silicon nitride and silica composite bed between grid（ONO）.106 conduct of conductor layer
Grid is controlled, material is, for example, DOPOS doped polycrystalline silicon.Gate structure 110 includes sequentially stacking gate dielectric layer on the substrate 100
111 and conductor layer 112.The material of gate dielectric layer 111 is, for example, silica.Grid of the conductor layer 112 as logic element, material
Material e.g. DOPOS doped polycrystalline silicon.
It forms gate structure 102 and the method for gate structure 110 includes the following steps.First, respectively at cell region 100a
And form different stacked material layers on the substrate 100 of peripheral region 100b（It is not painted）.In specific words, in the structure cell of substrate 100
Dielectric materials layer and the second conductor material layer between tunneling layer of oxidized material, the first conductor material layer, grid are sequentially stacked on area 100a,
And in sequentially stacking lock layer of oxidized material and the second conductor material layer, wherein cell region 100a on the peripheral region 100b of substrate 100
It is formed simultaneously with the second conductor material layer on the 100b of peripheral region.Then, to the second conductor material on cell region 100a
Layer carries out ion implanting manufacturing process.Later, an at least patterning step is carried out to above-mentioned material layer, in cell region 100a's
Gate structure 102 is formed on substrate 100 and in formation gate structure 110 on the substrate 100 of peripheral region 100b.
In one embodiment, gate structure 102 further include the metal silicide layer 107 being sequentially stacked in conductor layer 106,
Lower mask layer 108 and upper mask layer 109.Gate structure 110 further includes the metal silicide layer being sequentially stacked in conductor layer 112
113rd, lower mask layer 114 and upper mask layer 115.
Metal silicide layer 107 and metal silicide layer 113 are to reduce conductor layer 106 and conductor layer 112 respectively
Resistance value, and the part as control grid and a part for grid respectively.Metal silicide layer 107 and metal silicide layer
113 material identical, such as be tungsten silicide.Lower mask layer 108 and upper mask layer 109 are to increase word-line（By conductor
Layer 106 and metal silicide layer 107 thereon are formed）With the shortest distance between the bit line that is subsequently formed.Lower mask layer 108 with
The material identical of lower mask layer 114, such as be silicon nitride.The material identical of upper mask layer 109 and upper mask layer 115, such as
It is the silica that tetraethoxy silica alkane is formed（TEOS-SiO2）.In this embodiment, be using bilayer mask layer structure as
Example illustrates, but the present invention is not limited thereto.In other examples, individual layer or covering more than two layers can also be used
Mold layer structure.
In figure 1A to illustrate for a gate structure 110 is formed on the 100b of peripheral region, but the present invention is simultaneously
It is not limited.In other examples, most gate structures 110 can be formed on the 100b of peripheral region, peripheral region 100b can
With high voltage device area and low voltage component area（It is not painted）, and the gate dielectric layer being formed in high voltage device area and low voltage component area
With different thickness.
In addition, in figure 1A, cell region 100a is illustrated with the gate structure 102 of flash memory, however, of the invention
It is not limited thereto, the gate structure 102 on cell region 100a can also be the gate structure of other nonvolatile memories, example
As conductor layer 104 can be substituted by the electric charge storage layer made with dielectric layer.
Then, please continue to refer to Figure 1B, in being conformally formed lining 117 on substrate 100, to cover gate structure 102
And gate structure 110.The material of lining 117 is, for example, high-temperature oxide（High-temperature oxide, HTO）, and its
Forming method is, for example, to carry out chemical gaseous phase depositing manufacturing process.In one embodiment, in formation gate structure 102 and grid knot
After the step of structure 110 and before the step of forming lining 117, a few ion implanting step is also proceeded to, in crystalline substance
Most shallow doped regions are formed in the substrate 100 of born of the same parents area 100a（It is not painted）, and in the lining in the high voltage device area of peripheral region 100b
Most shallow doped regions are formed in bottom 100（It is not painted）.
Then, in formation clearance wall 118 on the side wall of each gate structure 102 and gate structure 110.Clearance wall 118
Material be, for example, silicon nitride.The method for forming clearance wall 118 is included in depositing spacer material layer on substrate 100（It does not paint
Show）.Then, anisotropic etching manufacturing process is carried out, to remove the portion gap wall material bed of material.In one embodiment（It does not paint
Show）, the step of above-mentioned removal portion gap wall material bed of material can also remove the part lining 117 between gate structure simultaneously.
Later, please continue to refer to Figure 1B, in being conformally formed stop-layer 116 on substrate 100, to cover gate structure
102 and gate structure 110.The material of stop-layer 116 is, for example, the silica that tetraethoxy silica alkane is formed, and its formation side
Rule carries out chemical gaseous phase depositing manufacturing process in this way.In one embodiment, in form clearance wall 118 the step of after and in
Before the step of forming stop-layer 116, ion implanting step can also be carried out, source is formed in the substrate 100 of cell region 100a
Polar region 133 and drain region 135, and source area 137 and drain region are formed in the substrate 100 in the low voltage component area of peripheral region 100b
139.Later, clearance wall 119 can be formed in the side wall of the stop-layer 116 on 110 side wall of gate structure.The material of clearance wall 119
Material e.g. silicon nitride.
Thereafter, please continue to refer to Figure 1B, in forming conductor layer 124 on substrate 100, to cover gate structure 110 and at least
Fill up the gap between gate structure 102.The material of conductor layer 124 is, for example, polysilicon, and the method formed is, for example, to carry out
Chemical vapor deposition manufacturing process, thickness are, for example, about 60 nanometers.Later, selectively conductor layer 124 can be planarized
Manufacturing process makes conductor layer 124 have flat surface.Later, mask layer 125 is formed on cell region 100a, exposes week
Conductor layer 124 on the 100b of border area.Mask layer 125 is, for example, photoresist layer.
Fig. 1 C are please referred to, are etching mask with mask layer 125, patterning conductor layer 124 removes leading on the 100b of peripheral region
Body layer 124 exposes stop-layer 116.Later, mask layer 125 is removed.Then, stop-layer 120, covering are formed on the substrate 100
The conductor layer 124 of cell region 100a and the stop-layer 116 of peripheral region 100b.The material of stop-layer 120 is, for example, silicon nitride, shape
Into method be, for example, chemical vapour deposition technique.Later, dielectric layer 122 is formed on the stop-layer 120 of peripheral region 100b.Dielectric
The material of layer 122 is, for example, spin-on glasses, and forming method is, for example, spin-coating method.In another embodiment, dielectric layer 122
Material can also be, for example, silica, and forming method is, for example, chemical vapour deposition technique.Later, to stop on cell region 100a
Only layer 120 is grinding stop layer, and planarization manufacturing process is carried out to dielectric layer 122 using chemical mechanical grinding manufacturing process.
Later, Fig. 1 D, removal stop layer 120 are please referred to.Then, cap layer 126 is formed on the substrate 100, covers structure cell
The dielectric layer 122 in conductor layer 124 and peripheral region 100b on area 100a.The material of cap layer 126 is, for example, silicon nitride, shape
Into method be, for example, plasma enhanced type chemical vapour deposition technique, thickness can be 100nm to 300nm.
Thereafter, using lithographic and etching manufacturing process, it is stop layer with stop-layer 116, patterns cap layer 126 and conductor
Layer 124, so that the conductor layer 124 left forms virtual self-aligning contact window plug 127 on cell region 100a, and virtual
127 surrounding of self-aligning contact window plug forms opening 128.
Thereafter, Fig. 1 E are please referred to, on cap layer 126 and opening 128 in insert dielectric layer 132.The material of dielectric layer 132
Silicon nitride may be used in material, and the method for formation is, for example, chemical vapour deposition technique.Dielectric layer 132 can be conforma layer, surface
There is height to rise and fall due to the structure or material layer on substrate 100, there are multiple recess 134 in 128 part of corresponding opening.Then,
Dielectric layer 136 is formed on the substrate 100.The material of dielectric layer 136 is different from the material of dielectric layer 132.The dielectric of dielectric layer 136
Constant is less than the dielectric constant of dielectric layer 132, and to reduce parasitic capacitance, failure and bit line are read caused by reducing Drain Disturbance
The problem of reciprocal effect.In addition, the ditch of dielectric layer 136 fills out ability more than dielectric layer 132, it is possible to reduce the height on 100 surface of substrate
Low fluctuating.The dielectric constant of dielectric layer 136 is, for example, less than 4.The material of dielectric layer 136 includes silica or doped silicon oxide.
Silica is, for example, spin-on glasses, high-density electric slurry oxide silicon（HDP oxide）Or high depth-width ratio ditch fills out manufacturing process（High
Aspect Ratio Process, HARP）The silica of formation.Doped silicon oxide is, for example, phosphorosilicate glass（PSG）, boron phosphorus silicon glass
Glass（BPSG）Or XX.Rubbing method, such as method of spin coating or chemical vapor deposition may be used in the forming method of dielectric layer 136
Method.Chemical vapour deposition technique is, for example, that high density plasma enhanced chemical vapor deposition method or high depth-width ratio ditch fill out manufacturing process.It is real one
It applies in example, the thickness of dielectric layer 132 is, for example, 10 angstroms to 100 angstroms.The depth of recess 134 is, for example, 2000 angstroms.Dielectric layer 136
Thickness is, for example, 5000 angstroms to 10000 angstroms.After dielectric layer 136 is formed, can selectivity carry out anneal
（annealing）, anneal processes are, for example, rapid thermal annealing or furnace anneal.
Thereafter, Fig. 1 F are please referred to, carry out planarization manufacturing process, remove dielectric layer 136 and head cover other than recess 134
Dielectric layer 132 on 126 surface of layer, leaves dielectric layer 136a and 132a.Planarization manufacturing process may be used chemical machinery and grind
Manufacturing process is ground to implement.
Later, Fig. 1 G are please referred to, remove the conductor layer of cap layer 126 and virtual self-aligning contact window plug 127
124, and be etched back stop-layer 116 and lining 117, to form clearance wall 116a and 117a, be formed simultaneously expose source electrode 133 from
Row is directed at contact window 143, the self-aligning contact window opening 145 for exposing drain region 135 and exposes connection Vss's
Self-aligning contact window is open（It is not painted）.And it is formed and 113 electricity of the metal silicide layer of gate structure 110 in peripheral region 100b
Property connection grid contact window opening 148.Dielectric layer 132a understands some and is also disappeared during cap layer 126 is removed
Consumption, and the top surface of left next dielectric layer 132b is caused to be less than the top surface of dielectric layer 136a.
Later, Fig. 1 H are please referred to, are filled out in self-aligning contact window opening 143,145 and grid contact window opening 148
Enter barrier layer metal layer（It is not painted）With conductor metal layer（It is not painted）, to form the contact hole being electrically connected with source area 133
Plug 153, with the contact window plug 155 being electrically connected of drain region 135, the contact window plug that is connect with Vss（It is not painted）And
The grid contact window plug 158 being electrically connected with the metal silicide layer 113 of gate structure 110.The material of barrier layer metal layer
E.g. tungsten nitride, titanium nitride or tantalum nitride, the method for formation are, for example, chemical vapour deposition technique, thickness be, for example, 5nm extremely
30nm.The material of conductor metal layer is, for example, tungsten, and the method for formation is, for example, chemical vapour deposition technique, and thickness is, for example, 100nm
To 300nm.
Fig. 1 H are please referred to, the flash memory that the embodiment of the present invention proposes includes：Substrate 100, multiple gate structures 102,
Source area 133 and drain region 135, multiple self-aligning contact windows 143,145, dielectric layer 132b and dielectric layer 136a.Substrate
100 include cell region 100a and peripheral region 100b.Gate structure 102 is located on the cell region 100a of substrate 100.Source area 133
It is located at respectively in the substrate 100 between the gate structure 102 of cell region 100a with drain region 135.Self-aligning contact window 143,
145 between gate structure 102, and on source area 133 and drain region 135.Dielectric layer 132b connects around voluntarily alignment
Window 143,145 is touched, and there is recess 134 at corresponding gate structure 102.Dielectric layer 136a is located in dielectric layer 132b, and fills out
Completely it is recessed 134, the dielectric constant of dielectric layer 136a is less than the dielectric constant of dielectric layer 132b.The material of dielectric layer 136a is, for example,
Spin-on glasses, high-density electric slurry oxide silicon are formed using high depth than filling out the chemical vapour deposition technique of ditch manufacturing process system
Silica.The material of dielectric layer 132b is, for example, silicon nitride.In one embodiment, the top surface of dielectric layer 136a is higher than dielectric layer
The top surface of 132b.Above-mentioned flash memory further includes gate structure 110, is located on the peripheral region 100b of substrate 100.In addition,
It is also covered on gate structure 110 by dielectric layer 122.The material of dielectric layer 122 is, for example, spin-on glasses, high-density electric slurry oxide
Silicon or the silica formed using high depth than filling out the chemical vapour deposition technique of ditch manufacturing process system.
In conclusion flash memory proposed by the present invention and its manufacturing method, manufacturing process is simple, and can reduce layer
Between dielectric layer dielectric constant, decline parasitic capacitance, so reduce Drain Disturbance caused by read failure and bit line interaction
The problem of influence.
Although the present invention has been disclosed by way of example above, it is not intended to limit the present invention., any technical field
In technical staff, without departing from the spirit and scope of the present invention, when can make some changes and embellishment, therefore the guarantor of the present invention
Range is protected when subject to appended as defined in claim.
Claims (10)
1. a kind of flash memory, including：
Substrate, the substrate include cell region；
Multiple first grid structures, on the cell region of the substrate；
Plurality of source regions and multiple drain regions, the respectively substrate between the first grid structure of the cell region
On；
Multiple self-aligning contact windows, between the first grid structure, and positioned at the source area and the drain region
On；
First dielectric layer around the self-aligning contact window, and has multiple recess at the correspondence first grid structure；
And
Second dielectric layer in first dielectric layer, and fills up the recess, and the dielectric constant of second dielectric layer is low
In the dielectric constant of first dielectric layer, second dielectric layer exposes first dielectric other than the recess
Layer.
2. flash memory as described in claim 1, wherein the top surface of second dielectric layer is higher than first dielectric layer
Top surface.
3. flash memory as claimed in claim 2, wherein first dielectric layer includes silicon nitride.
4. flash memory as claimed in claim 2, wherein second dielectric layer includes silica.
5. flash memory as claimed in claim 4, wherein the silica includes spin-on glasses.
6. a kind of manufacturing method of flash memory, including：
Substrate is provided, the substrate includes cell region；
Multiple first grid structures are formed on the cell region of the substrate；
Source area and drain region are formed in the substrate between the first grid structure；
A patterned conductor layer is formed over the substrate, is covered the first grid structure and is at least filled up the first grid
Gap between the structure of pole；
Multiple virtual self-aligning contact window plugs are formed on the substrate between the first grid structure, it is described virtual
Self-aligning contact window plug is located on the source area and the drain region, and is inserted in the virtual self-aligning contact window
Multiple openings are formed around plug；
The first dielectric layer, first dielectric layer are formed in the virtual self-aligning contact window plug and the open surfaces
There are multiple recess in place of the correspondence opening；
The second dielectric layer is formed on first dielectric layer, second dielectric layer fills up the opening, and described second is situated between
The dielectric constant of electric layer is less than the dielectric constant of first dielectric layer；
Planarization manufacturing process is carried out, to remove the institute other than second dielectric layer and the opening other than the recess
State the first dielectric layer；And
The virtual self-aligning contact window plug is removed, forms multiple self-aligning contact windows.
7. the manufacturing method of flash memory as claimed in claim 6 further includes and forms stop-layer over the substrate, covering
The patterned conductor layer and the first grid structure.
8. the manufacturing method of flash memory as claimed in claim 6, wherein first dielectric layer includes silicon nitride.
9. the manufacturing method of flash memory as claimed in claim 6, wherein second dielectric layer includes silica.
10. the manufacturing method of flash memory as claimed in claim 9, wherein the silica includes spin-on glasses, height
Density electric slurry oxide silicon or the silica formed using high depth than filling out the chemical vapour deposition technique of ditch manufacturing process system.
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|---|---|---|---|---|
| US6383878B1 (en) * | 2001-02-15 | 2002-05-07 | Winbond Electronics Corp. | Method of integrating a salicide process and a self-aligned contact process |
| CN1378271A (en) * | 2001-03-29 | 2002-11-06 | 华邦电子股份有限公司 | Overlapped grid flash memory unit and its producing method |
| CN102254867A (en) * | 2010-05-21 | 2011-11-23 | 华邦电子股份有限公司 | Flash memory manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6383878B1 (en) * | 2001-02-15 | 2002-05-07 | Winbond Electronics Corp. | Method of integrating a salicide process and a self-aligned contact process |
| CN1378271A (en) * | 2001-03-29 | 2002-11-06 | 华邦电子股份有限公司 | Overlapped grid flash memory unit and its producing method |
| CN102254867A (en) * | 2010-05-21 | 2011-11-23 | 华邦电子股份有限公司 | Flash memory manufacturing method |
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