CN104795396A - Quick-flash memory and manufacture method thereof - Google Patents
Quick-flash memory and manufacture method thereof Download PDFInfo
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- CN104795396A CN104795396A CN201410026977.0A CN201410026977A CN104795396A CN 104795396 A CN104795396 A CN 104795396A CN 201410026977 A CN201410026977 A CN 201410026977A CN 104795396 A CN104795396 A CN 104795396A
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Abstract
The invention discloses a quick-flash memory and a manufacture method thereof. The quick-flash memory comprises a substrate, first grid structures, source areas, drain areas, self-aligning contact windows, a first dielectric layer and a second dielectric layer, wherein the first grid structures are placed on a cell region of the substrate, the source and drain areas are placed on the substrate among the first grid structures respectively, the self-aligning windows are placed among the first grid structures and on the source and drain areas, the first dielectric layer surrounds the self-aligning windows and includes recesses corresponding to the first grid structures, the second dielectric layer is placed in the first dielectric layer and fills the recesses, and the dielectric layer of the second dielectric layer is lower than that of the first dielectric layer.
Description
Technical field
The present invention relates to a kind of memory component and manufacture method thereof, and in particular to a kind of flash memory and manufacture method thereof.
Background technology
In the manufacturing process of flash memory (flash memory), the dielectric constant of interlayer dielectric layer is too high easily causes Drain Disturbance (drain disturb), and occurs the problem reading unsuccessfully (read fail) and bit line reciprocal effect (BL-BL coupling effect).
Summary of the invention
The embodiment of the present invention proposes a kind of flash memory and manufacture method thereof, can reduce the dielectric constant of interlayer dielectric layer, and parasitic capacitance is declined, and then reduces the problem of the reading failure that causes of Drain Disturbance and bit line reciprocal effect.
The embodiment of the present invention proposes a kind of flash memory, comprising: substrate, multiple first grid structure, plurality of source regions and drain region, multiple self-aligning contact window, the first dielectric layer and the second dielectric layer.First grid structure is positioned on the cell region of substrate.In substrate between the first grid structure that source area and drain region lay respectively at cell region.Self-aligning contact window between first grid structure, and is positioned on source area and drain region.First dielectric layer around self-aligning contact window, and has depression at corresponding first grid structure place.Second dielectric layer is arranged in the first dielectric layer, and fills up depression, and the dielectric constant of the second dielectric layer is lower than the dielectric constant of the first dielectric layer.
The bright Real of this Hair of Yi Zhao executes described in example, and the end face of described second dielectric layer is higher than the end face of described first dielectric layer.
The bright Real of this Hair of Yi Zhao executes described in example, and described first dielectric layer comprises silicon nitride.
The bright Real of this Hair of Yi Zhao executes described in example, and described second dielectric layer comprises silica.
The bright Real of this Hair of Yi Zhao executes described in example, and described silica comprises spin-on glasses.
The embodiment of the present invention also proposes a kind of manufacture method of flash memory, comprises and provides substrate, and substrate comprises cell region.The cell region of substrate is formed multiple first grid structure.Source area and drain region is formed in substrate between first grid structure.Substrate is formed the conductor layer of patterning, covers first grid structure and the gap at least filled up between first grid structure.Substrate between first grid structure is formed multiple virtual self-aligning contact window connector, virtual self-aligning contact window connector is positioned on source area and drain region, and forms multiple opening around virtual self-aligning contact window connector.The first dielectric layer is formed at virtual self-aligning contact window connector and open surfaces.First dielectric layer is formed the second dielectric layer, and the second dielectric layer fills up opening, and the dielectric constant of the second dielectric layer is lower than the dielectric constant of the first dielectric layer.Remove virtual self-aligning contact window connector, form multiple self-aligning contact window.
According to executing described in example according to the bright Real of this Hair, the manufacture method of described flash memory, also comprises and forms a stop-layer over the substrate, covers the conductor layer of described patterning and described second grid structure.
The bright Real of this Hair of Yi Zhao executes described in example, the manufacture method of described flash memory, and wherein said first dielectric layer comprises silicon nitride.
The bright Real of this Hair of Yi Zhao executes described in example, the manufacture method of described flash memory, and wherein said second dielectric layer comprises silica.
The bright Real of this Hair of Yi Zhao executes described in example, the manufacture method of described flash memory, and wherein said silica comprises spin-on glasses, high-density electric slurry oxide silicon or adopt high depth the silica formed than the chemical vapour deposition technique filling out ditch manufacturing process system.
The flash memory of the embodiment of the present invention and manufacture method thereof, can reduce the dielectric constant of interlayer dielectric layer, and parasitic capacitance is declined, and then reduce the problem of the reading failure that causes of Drain Disturbance and bit line reciprocal effect.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
The generalized section of the manufacturing process of flash memory of Figure 1A to 1H for illustrating according to the embodiment of the present invention.
Wherein, description of reference numerals is as follows:
100: substrate
100a: cell region
100b: surrounding zone
102,110: grid structure
103: tunnel oxide
104,106,112: conductor layer
105: dielectric layer between grid
107,113: metal silicide layer
108,114: lower mask layer
109,115: upper mask layer
111: gate dielectric layer
116: stop-layer
117: lining
116a, 117a, 118,119: clearance wall
120: stop-layer
122,132,132a, 132b, 136,136a: dielectric layer
124: conductor layer
125: mask layer
126: cap layer
127: virtual self-aligning contact window connector
128: opening
133,137: source area
134: depression
135,139: drain region
143,145: self-aligning contact window opening
148: grid contact window opening
153,155,158: contact window plug
Embodiment
The generalized section of the manufacturing process of flash memory of Figure 1A to 1H for illustrating according to the embodiment of the present invention.
Please refer to Figure 1A, substrate 100 is provided.Substrate 100 can be semiconductor or semiconducting compound, the silicon substrate of such as N-type or P type, three or five race's Semiconductor substrate or germanium silicides.Substrate 100 also can be silicon-on-insulator (silicon on insulator, SOI).Substrate 100 has cell region 100a and surrounding zone 100b.On the substrate 100 of cell region 100a, form most grid structures 102, and on the substrate 100 of surrounding zone 100b, form at least one grid structure 110.
Grid structure 102 can be the grid structure of non-volatile memory device, such as, be the grid structure of flash memory devices, is such as to comprise sequentially dielectric layer 105 and conductor layer 106 between stacking tunnel oxide 103 on the substrate 100, conductor layer 104, grid.The material of tunnel oxide 103 is such as silica.Conductor layer 104 is as floating grid, and its material is such as doped polycrystalline silicon.Between grid, dielectric layer 105 is such as silica, silicon nitride and silica composite bed (ONO).Conductor layer 106 is as control gate, and its material is such as doped polycrystalline silicon.Grid structure 110 comprises sequentially stacking gate dielectric layer 111 on the substrate 100 and conductor layer 112.The material of gate dielectric layer 111 is such as silica.Conductor layer 112 is as the grid of logic element, and its material is such as doped polycrystalline silicon.
Form grid structure 102 to comprise the following steps with the method for grid structure 110.First, the substrate 100 respectively at cell region 100a and surrounding zone 100b is formed different stacked material layers (not illustrating).In specific words, sequentially dielectric materials layer and the second conductor material layer between stacking tunneling layer of oxidized material, the first conductor material layer, grid on the cell region 100a of substrate 100, and on the surrounding zone 100b of substrate 100 sequentially stacking lock layer of oxidized material and the second conductor material layer, the second conductor material layer wherein on cell region 100a and surrounding zone 100b is what formed simultaneously.Then, ion implantation manufacturing process is carried out to the second conductor material layer on cell region 100a.Afterwards, at least one patterning step is carried out to above-mentioned material layer, to form grid structure 102 and form grid structure 110 on the substrate 100 of cell region 100a on the substrate 100 of surrounding zone 100b.
In one embodiment, grid structure 102 also comprises the metal silicide layer 107 be sequentially stacked on conductor layer 106, lower mask layer 108 and upper mask layer 109.Grid structure 110 also comprises the metal silicide layer 113 be sequentially stacked on conductor layer 112, lower mask layer 114 and upper mask layer 115.
Metal silicide layer 107 and metal silicide layer 113 are the resistances in order to reduce conductor layer 106 and conductor layer 112 respectively, and respectively as a part for control gate and a part for grid.Metal silicide layer 107 is identical with the material of metal silicide layer 113, such as, be tungsten silicide.Lower mask layer 108 and upper mask layer 109 be in order to increase character line (by conductor layer 106 and on metal silicide layer 107 form) and the follow-up bit line formed between beeline.Lower mask layer 108 is identical with the material of lower mask layer 114, such as, be silicon nitride.Upper mask layer 109 is identical with the material of upper mask layer 115, such as, be the silicon dioxide (TEOS-SiO that tetraethoxy silica alkane is formed
2).In this embodiment, illustrate for bilayer mask Rotating fields, but the present invention is not as limit.In other examples, also can use individual layer or be greater than two-layer mask layer structure.
Illustrate for grid structure of formation on the 100b of surrounding zone 110 in figure ia, but the present invention is not as limit.In other examples, surrounding zone 100b can be formed most grid structures 110, surrounding zone 100b can have high voltage device district and low voltage component district (not illustrating), and the gate dielectric layer be formed in high voltage device district and low voltage component district has different thickness.
In addition, in figure ia, cell region 100a illustrates with the grid structure 102 of flash memory, but, the present invention is not as limit, grid structure 102 on cell region 100a also can be the grid structure of other nonvolatile memories, and such as conductor layer 104 can be substituted by the electric charge storage layer made with dielectric layer.
Then, continue referring to Figure 1B, on substrate 100, form lining 117 to compliance, with overlies gate structure 102 and grid structure 110.The material of lining 117 is such as high-temperature oxide (high-temperature oxide, HTO), and its formation method is such as carry out chemical gaseous phase Shen to amass manufacturing process.In one embodiment, after the step forming grid structure 102 and grid structure 110 and before the step forming lining 117, also at least one ion implantation step can be carried out, to form most shallow doped regions (not illustrating) in the substrate 100 of cell region 100a, and in the substrate 100 in the high voltage device district of surrounding zone 100b, form most shallow doped regions (not illustrating).
Then, on the sidewall of each grid structure 102 and grid structure 110, clearance wall 118 is formed.The material of clearance wall 118 is such as silicon nitride.The method forming clearance wall 118 is included in Shen on substrate 100 and amasss spacer material layer (not illustrating).Then, carry out anisotropic etching manufacturing process, to remove portion gap wall material layer.(do not illustrate) in one embodiment, the above-mentioned step removing portion gap wall material layer also can remove the part lining 117 between grid structure simultaneously.
Afterwards, continue referring to Figure 1B, on substrate 100, form stop-layer 116 to compliance, with overlies gate structure 102 and grid structure 110.The material of stop-layer 116 is such as the silicon dioxide that tetraethoxy silica alkane is formed, and its formation method is such as carry out chemical gaseous phase Shen to amass manufacturing process.In one embodiment, after the step forming clearance wall 118 and before the step forming stop-layer 116, also ion implantation step can be carried out, in the substrate 100 of cell region 100a, form source area 133 and drain region 135, and in the substrate 100 in the low voltage component district of surrounding zone 100b, form source area 137 and drain region 139.Afterwards, the sidewall of stop-layer 116 on grid structure 110 sidewall clearance wall 119 can be formed.The material of clearance wall 119 is such as silicon nitride.
Thereafter, continue referring to Figure 1B, on substrate 100, form conductor layer 124, also at least fill up the gap between grid structure 102 with overlies gate structure 110.The material of conductor layer 124 is such as polysilicon, and its method formed is such as carry out chemical vapour deposition (CVD) manufacturing process, and thickness is such as about 60 how rice.Afterwards, selectivity can carry out planarization manufacturing process to conductor layer 124, make conductor layer 124 have smooth surface.Afterwards, cell region 100a forms mask layer 125, expose the conductor layer 124 on the 100b of surrounding zone.Mask layer 125 is such as photoresist layer.
Please refer to Fig. 1 C, with mask layer 125 for etching mask, patterning conductor layer 124, removes the conductor layer 124 on the 100b of surrounding zone, exposes stop-layer 116.Afterwards, mask layer 125 is removed.Then, form stop-layer 120 on the substrate 100, cover the conductor layer 124 of cell region 100a and the stop-layer 116 of surrounding zone 100b.The material of stop-layer 120 is such as silicon nitride, and the method for formation is such as chemical vapour deposition technique.Afterwards, the stop-layer 120 of surrounding zone 100b forms dielectric layer 122.The material of dielectric layer 122 is such as spin-on glasses, and its formation method is such as spin-coating method.In another embodiment, the material of dielectric layer 122 can be also such as silica, and its formation method is such as chemical vapour deposition technique.Afterwards, with the stop-layer 120 on cell region 100a for grinding stop layer, cmp manufacturing process is utilized to carry out planarization manufacturing process to dielectric layer 122.
Afterwards, please refer to Fig. 1 D, removal stop layer 120.Then, form cap layer 126 on the substrate 100, cover the conductor layer 124 on cell region 100a and the dielectric layer 122 on the 100b of surrounding zone.The material of cap layer 126 is such as silicon nitride, and the method for formation is such as electricity slurry enhanced chemical vapor deposition method, and thickness can be 100nm to 300nm.
Thereafter, utilize micro-shadow and etching manufacturing process, with stop-layer 116 for stop layer, patterning cap layer 126 and conductor layer 124, to make the conductor layer 124 stayed form virtual self-aligning contact window connector 127 on cell region 100a, and form opening 128 around virtual self-aligning contact window connector 127.
Thereafter, please refer to Fig. 1 E, on cap layer 126 and in opening 128, insert dielectric layer 132.The material of dielectric layer 132 can adopt silicon nitride, and the method for formation is such as chemical vapour deposition technique.Dielectric layer 132 can be conforma layer, and its surface has height to rise and fall because of the structure on substrate 100 or material layer, have multiple depression 134 in corresponding opening 128 part.Then, dielectric layer 136 is formed on the substrate 100.The material of dielectric layer 136 is different from the material of dielectric layer 132.The dielectric constant of dielectric layer 136, lower than the dielectric constant of dielectric layer 132, to reduce parasitic capacitance, reduces the problem of reading failure that Drain Disturbance causes and bit line reciprocal effect.In addition, the ditch ability of filling out of dielectric layer 136 is greater than dielectric layer 132, and the height that can reduce substrate 100 surface rises and falls.The dielectric constant of dielectric layer 136 is such as lower than 4.The material of dielectric layer 136 comprises silica or doped silicon oxide.Silica is such as spin-on glasses, the silica that fabrication technique (High Aspect RatioProcess, HARP) is formed filled and presented by high-density electric slurry oxide silicon (HDP oxide) or high depth-width ratio ditch.Doped silicon oxide is such as phosphorosilicate glass (PSG), boron-phosphorosilicate glass (BPSG) or XX.The formation method of dielectric layer 136 can adopt rubbing method, such as method of spin coating or chemical vapour deposition technique.Chemical vapour deposition technique is such as that fabrication technique filled and presented by high density plasma enhanced chemical vapor deposition method or high depth-width ratio ditch.In one embodiment, the thickness of dielectric layer 132 is such as 10 dust to 100 dusts.The degree of depth of depression 134 is such as 2000 dusts.The thickness of dielectric layer 136 is such as 5000 dust to 10000 dusts.After formation dielectric layer 136, can optionally carry out anneal (annealing), anneal processes is such as rapid thermal annealing or furnace anneal.
Thereafter, please refer to Fig. 1 F, carry out planarization manufacturing process, remove the dielectric layer 136 beyond depression 134 and the dielectric layer 132 on cap layer 126 surface, leave dielectric layer 136a and 132a.Planarization manufacturing process can adopt cmp manufacturing process to implement.
Afterwards, please refer to Fig. 1 G, remove the conductor layer 124 of cap layer 126 and virtual self-aligning contact window connector 127, and eat-back stop-layer 116 and lining 117, to form clearance wall 116a and 117a, form the self-aligning contact window opening 143 exposing source electrode 133, the self-aligning contact window opening 145 exposing drain region 135 simultaneously and expose the self-aligning contact window opening (not illustrating) connecting Vss.And the grid contact window opening 148 be electrically connected with the metal silicide layer 113 of grid structure 110 is formed at surrounding zone 100b.Understand some at the process dielectric layer 132a removing cap layer 126 to be also consumed, and make the end face of end face lower than dielectric layer 136a of left next dielectric layer 132b.
Afterwards, please refer to Fig. 1 H, barrier layer metal level (not illustrating) and conductor metal layer (not illustrating) is inserted, to form the contact window plug 153 be electrically connected with source area 133, the contact window plug 155, the contact window plug (not illustrating) be connected with Vss and the grid contact window connector 158 be electrically connected with the metal silicide layer 113 of grid structure 110 that are electrically connected with drain region 135 in self-aligning contact window opening 143,145 and grid contact window opening 148.The material of barrier layer metal level is such as tungsten nitride, titanium nitride or tantalum nitride, and the method for formation is such as chemical vapour deposition technique, and thickness is such as 5nm to 30nm.The material of conductor metal layer is such as tungsten, and the method for formation is such as chemical vapour deposition technique, and thickness is such as 100nm to 300nm.
Please refer to Fig. 1 H, the flash memory that the embodiment of the present invention proposes comprises: substrate 100, multiple grid structure 102, source area 133 and drain region 135, multiple self-aligning contact window 143,145, dielectric layer 132b and dielectric layer 136a.Substrate 100 comprises cell region 100a and surrounding zone 100b.Grid structure 102 is positioned on the cell region 100a of substrate 100.In substrate 100 between the grid structure 102 that source area 133 and drain region 135 lay respectively at cell region 100a.Self-aligning contact window 143,145 between grid structure 102, and is positioned at source area 133 with on drain region 135.Dielectric layer 132b around self-aligning contact window 143,145, and has depression 134 at corresponding grid structure 102 place.Dielectric layer 136a is arranged in dielectric layer 132b, and fills up depression 134, and the dielectric constant of dielectric layer 136a is lower than the dielectric constant of dielectric layer 132b.The material of dielectric layer 136a is such as spin-on glasses, high-density electric slurry oxide silicon or adopt high depth than fill out ditch manufacturing process system chemical vapour deposition technique formed silica.The material of dielectric layer 132b is such as silicon nitride.In one embodiment, the end face of dielectric layer 136a is higher than the end face of dielectric layer 132b.Above-mentioned flash memory also comprises grid structure 110, and it is positioned on the surrounding zone 100b of substrate 100.In addition, grid structure 110 is also covered by dielectric layer 122.The material of dielectric layer 122 is such as spin-on glasses, high-density electric slurry oxide silicon or adopt high depth than fill out ditch manufacturing process system chemical vapour deposition technique formed silica.
In sum, the flash memory that the present invention proposes and manufacture method thereof, manufacturing process is simple, and can reduce the dielectric constant of interlayer dielectric layer, and parasitic capacitance is declined, and then the problem of the reading failure that causes of minimizing Drain Disturbance and bit line reciprocal effect.
Although the present invention discloses as above with embodiment; so itself and be not used to limit the present invention; any the technical staff in the technical field; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on the appended claim person of defining.
Claims (10)
1. a flash memory, comprising:
Substrate, described substrate comprises cell region;
Multiple first grid structure, is positioned on the described cell region of described substrate;
Plurality of source regions and multiple drain region, on the described substrate between the described first grid structure laying respectively at described cell region;
Multiple self-aligning contact window, between described first grid structure, and is positioned on described source area and described drain region;
First dielectric layer, around described self-aligning contact window, and has multiple depression at correspondence described first grid structure place; And
Second dielectric layer, is arranged in described first dielectric layer, and fills up described depression, and the dielectric constant of described second dielectric layer is lower than the dielectric constant of described first dielectric layer.
2. flash memory as claimed in claim 1, the end face of wherein said second dielectric layer is higher than the end face of described first dielectric layer.
3. flash memory as claimed in claim 2, wherein said first dielectric layer comprises silicon nitride.
4. flash memory as claimed in claim 2, wherein said second dielectric layer comprises silica.
5. flash memory as claimed in claim 4, wherein said silica comprises spin-on glasses.
6. a manufacture method for flash memory, comprising:
There is provided substrate, described substrate comprises cell region;
The described cell region of described substrate forms multiple first grid structure;
Source area and drain region is formed in described substrate between described first grid structure;
Form the conductor layer of a patterning over the substrate, cover described first grid structure and at least fill up the gap between described first grid structure;
Described substrate between described first grid structure is formed multiple virtual self-aligning contact window connector, described virtual self-aligning contact window connector is positioned on described source area and described drain region, and forms multiple opening around described virtual self-aligning contact window connector;
The first dielectric layer is formed at described virtual self-aligning contact window connector and described open surfaces;
Described first dielectric layer forms the second dielectric layer, and described second dielectric layer fills up described opening, and the dielectric constant of described second dielectric layer is lower than the dielectric constant of described first dielectric layer; And
Remove described virtual self-aligning contact window connector, form multiple self-aligning contact window.
7. the manufacture method of flash memory as claimed in claim 6, also comprises and forms stop-layer over the substrate, cover the conductor layer of described patterning and described second grid structure.
8. the manufacture method of flash memory as claimed in claim 6, wherein said first dielectric layer comprises silicon nitride.
9. the manufacture method of flash memory as claimed in claim 6, wherein said second dielectric layer comprises silica.
10. the manufacture method of flash memory as claimed in claim 9, wherein said silica comprises spin-on glasses, high-density electric slurry oxide silicon or adopts high depth the silica formed than the chemical vapour deposition technique filling out ditch manufacturing process system.
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| CN107689344A (en) * | 2016-08-05 | 2018-02-13 | 格罗方德半导体公司 | It is contact pad designed to improve the method for effective perforation spacing distance and its caused device to form high k |
| CN115662903A (en) * | 2022-11-14 | 2023-01-31 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device and semiconductor device |
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