CN1378271A - Overlapped grid flash memory unit and its producing method - Google Patents
Overlapped grid flash memory unit and its producing method Download PDFInfo
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- CN1378271A CN1378271A CN01110197.0A CN01110197A CN1378271A CN 1378271 A CN1378271 A CN 1378271A CN 01110197 A CN01110197 A CN 01110197A CN 1378271 A CN1378271 A CN 1378271A
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Abstract
The present invention is a quickly-flashing storage cell of laminated grid including an U-shape floating grid, a control grid and an oxidizing sandwich layer of internal polysilicon. Its preparing steps are as follows: depositing a tunneling oxidation layer and a first polysilicon layer on the silicon substrate, injecting into the first polysilicon layer, subsequently depositing oxidation layer, depositing nitride layer, etching lithographic printing technology (microimaging preparation process), conducting etching, flattening with chemical and mechanical grinding and etching back, the first polycrystal laminated structure being formed as well as the second polysilicon layer, polysilicon gap wall, the third polysilicon layer and the control grid being formed.
Description
The invention relates to a kind of improved overlapped grid flash memory unit (Stacked GateFlash Memory Cell) that can between floating grid (FG) and control gate (CG), increase overlapping area (Areal Overlapping), thereby can increase the coupling efficiency (Control-gate-to-floating-gate Coupling Ratio) of control gate, and improve the memory cell performance to floating grid.Be particularly to a kind of new method of making overlapped grid flash memory unit, and with the method manufacturing flash memory cell, wherein floating grid autoregistration (Self-aligned) forms in field oxide, and does not sacrifice the coupling efficiency between floating grid and the control gate.The present invention is applied in the spacing that method novel on the manufacturing process has also more been dwindled floating grid because of the limit that has surmounted traditional etching lithography process (micro-photographing process) basic technology, therefore, the present invention can make the yardstick of flash memory cell further dwindle (Scaling Down), and can not cause producing too much cost because of improvement etching lithography process.In addition, higher coupling efficiency can make memory cell operate under lower control-grid voltage; This favourable feature can be reduced in a succession of harsh standard of breakdown voltage between flash memory cell.So the size that the disclosed method of the present invention is not dwindled flash memory cell basically only also can be dwindled the voltage of floating grid.
Along with the introducing of digital camera and hand held personal computer with increase fast, the high density flash memory that has small size and can be used as the portable large capacity holder is noted widely.The cost that the size that electronics is used consumer, the most important key of flash memory to be to utilize to reduce memory cell reduces cost.In order to reduce the size of memory cell, data line line-spacing (DataLine Pitch) must be as being reduced as the grid length.The result that the floating grid size reduces can make the yardstick of flash memory cell further dwindle, and this has adverse influence for floating grid in the stack gate flash memory and the coupling efficiency between control gate.Therefore, in semi-conductor industry, the target that reaches high grid coupling efficiency and the flash memory cell yardstick can further be dwindled becomes more challenging.
In the 271st page of IEDM (1997), title for " a kind of novel high density 5F that is applicable to 256 Mbit and 1 Gbit flash memory
2NAND STI memory cell technologies ", the author is K.Shimizu, K.Narita, H.Watanabe; E.Kamiya, Takeuchi, T.Yaegashi; S.Aricome, with T.Watanabe, open source literature disclosed the 5F of a kind of low level cost (Low Bit-cost) flash memory
2NAND STI memory cell technologies.Fig. 1 a, 1b, 1c are depicted as three layers of polysilicon layer that are used for making flash memory in the Shimizu et al document.The first thin polysilicon film 22 (part of forming floating grid) provides in the forming process of shallow trench isolation (Shallow Trench Isolation), improves the function of controlled (the The Controllability of The Planarization Process) of flatening process.Second polysilicon film 24 (part of also forming floating grid) can be defined by silicon nitride cover curtain layer 26 and 28 of two nitride spacer (Spacer).Second polysilicon film 24 that nitride spacer 28 can be provided at field oxide (Field Oxide) top overlaps, to improve the coupling efficiency of memory cell.
Disclosed memory cell in Shimizu et al document, because the formation of SiN pattern (before the SiN clearance wall forms) is not the border that is self-aligned to field oxide, misalignment admissible error (MisalignmentTolerance) is subjected to significant limitation between SiN cover curtain layer on the memory cell yardstick and polysilicon layer.Moreover the interior dielectric film between control gate and floating grid is a dual space, and therefore, the improvement of coupling efficiency overlaps (utilizing nitride spacer to control) owing to the floating grid at the field oxide top entirely, so the improvement of coupling efficiency quite is restricted.
Another title for " be used for the 1-Gb flash memory a kind of isolate with 0.18-μ m width with 3-D in the 0.24-μ m of polysilicon dielectric film
2The memory cell processing procedure ", the author is T.Kobayashi, N.Matsuzaki; A.Sato, A.Katayama, H.Kurata; A.Miura, T.Mine, Y.Goto; T.Morimoto; H.Kume, T.Kure, and K.Kimura; open source literature in disclose a kind of utilization and use 0.2-μ m manufacturing technology, to make 0.24-μ m
2The method of contactless array (Contactless-array) flash memory cell.Shown in Fig. 2 a, 2b, 2c, 2d, 2e, 2f, 2g, between memory cell, utilize boron-phosphorosilicate glass (BPSG) 42 is inserted in the chase, form the wide autoregistration shallow concave groove of 0.18-μ m isolate 44 (Shallow Groove Isolation, SGI), to keep the isolation breakdown voltage.In addition, use three-dimensional space, chemical monolayer vapour deposition oxide layer to utilize the increase coupling efficiency to reduce built-in function voltage (Internal Operational Voltage) as interior polysilicon dielectric film 38 with high capacitance.
Disclosed method comprises following principal character in Kobayashi et al document: (1) first polysilicon film can be used as first floating grid 32, and is self-aligned to the border of field oxide; (2) second polysilicon films are as sacrifice layer, and can be removed subsequently, to form U-type floating grid; (3) after forming U-type floating grid and floating grid patterning, the 3rd polysilicon film can be used as second floating grid 36; (4) the 4th polysilicon films 40 can be used as the control gate pattern; (5) between control gate and floating grid, form individual layer three-dimensional space (3D) CVD oxide layer as interior dielectric film 38, with the further coupling efficiency that improves.Yet, several significant disadvantages are also arranged in the method for Kobayashi et al.Shortcoming.The first, need four layers of polysilicon film.Second, because the formation (the 3rd polysilicon) of floating grid pattern is not to be self-aligned to first poly-silicon pattern, misalignment admissible error between floating grid pattern cover curtain layer (that is, floating top) and the first poly-silicon pattern cover curtain layer (bottom of floating) can be restricted on memory cell size.Moreover the interior dielectric film between floating grid and control gate is a simple layer chemical vapour deposition (CVD) oxide layer, thereby potential data is preserved the puzzlement that (dataretention) problem will cause assembly reliability.
Therefore, a purpose of the present invention is to provide a kind of overlapped grid flash memory unit and manufacture method thereof, its high-performance, and undersized stack gate flash memory, and can increase the coupling efficiency of control gate to floating grid.Be particularly to provide a kind of improved overlapped grid flash memory unit, can between floating grid (FG) and control gate (CG), increase the overlapping area, thereby can increase the coupling efficiency of control gate floating grid.Lamination flash memory cell of the present invention can utilize the method for a novelty to make, and under the coupling efficiency of not sacrificing between control gate and floating grid, floating grid can be self-aligned to field oxide.The employed novel method of technology of the present invention can surmount the limit of traditional basic etching lithographic printing and further dwindle spacing between floating grid, therefore, the present invention can make the yardstick of flash memory cell further dwindle, and can not cause too much because of improveing the cost that the etching lithographic printing causes.The higher grid coupling efficiency that memory cell of the present invention proposed also can make memory cell operate under lower control-grid voltage.
Purpose of the present invention can reach by following measure:
A kind of overlapped grid flash memory unit manufacture method comprises the following steps:
(a) deposition one tunneling oxide layer and one first polysilicon layer on a silicon base, ion injects this first polysilicon layer then;
(b) deposition one first oxide layer on this first polysilicon layer, and then deposition mononitride layer then carries out the etching offset printing to this first polysilicon layer, to form one first polysilicon laminate structure;
(c) this silicon base is carried out etching,, then deposit one second oxide layer to fill up this shallow trench in this silicon base, to produce a shallow trench at least;
(d) carry out the cmp planarization and eat-back oxide layer, exceed this second oxide layer of this shallow trench part with removal;
(e) deposition one second polysilicon layer, ion injects this second polysilicon layer then, and this second polysilicon layer of etching, in order to form one second polysilicon gap wall on the sidewall of this first polysilicon laminate structure;
(f) remove this nitride layer with wet etching, then with wet this first oxide layer removed at this first polysilicon layer top of soaking, wherein, this second polysilicon gap wall and this first polysilicon layer form a U-type three-dimensional space floating grid; And
(g) polysilicon dielectric film and one the 3rd polysilicon layer in the deposition one then carry out the etching offset printing to the 3rd polysilicon layer, in order to form a control gate from the 3rd polysilicon layer;
(h) wherein should cooperate the U-type three-dimensional space profile of this floating grid with this control gate by interior polysilicon dielectric film, so can increase the area overlapping part between this control gate and this floating grid.
The invention still further relates to a kind of overlapped grid flash memory unit, comprising:
(a) substrate is and at this suprabasil tunneling oxide layer;
(b) the U-type floating grid on this tunneling oxide layer, this U-type floating grid comprises a base section and an alar part part; And
(c) control gate, and between this floating grid and this control gate one in polysilicon oxidation sandwich layer structure, should cooperate the U-type profile of this floating grid with this control gate by interior polysilicon oxide layer, so can be increased in the area overlapping part between this control gate and this floating grid.
In other words, the method for preparing the lamination flash memory cell of the present invention has several principal characters, it comprises: (1) first polysilicon (some of floating grid) is self-aligned to the field oxide border, and polysilicon film is quite thin, to be convenient to STI (shallow trench isolation) planarisation step; (2) oxide/nitride layer can be used as sacrifice layer, and this two-layer all removal before second polysilicon layer deposition; (3) deposition second polysilicon layer is to be formed on the polysilicon gap wall (some of floating grid) on first each limit of polysilicon layer pattern.The clearance wall that the inventive method proposes forms and can make final floating grid (Final Floating Gate) be self-aligned to field oxide.Floating grid at the field oxide top overlaps and can utilize the thickness of polysilicon gap wall to decide.Moreover the formation of polysilicon gap wall can make the scope that is limited at the more traditional etching lithographic printing of the spacing of two adjacent floating grids more dwindle.These 2 features are further dwindled the yardstick of memory cell.
Method of the present invention can the following step as summary:
(1) deposition one tunneling oxide layer (about 70-120 dust) and thin first polysilicon layer (about 300-1000 dust) on silicon base, then ion injects first polysilicon layer.
(2) oxide layer (about 100-1000 dust) that deposition one approaches in substrate, one deck nitride layer (about 3000 dusts) is followed with the little shadow of first polysilicon layer, to form the first polysilicon laminate structure then.
(3) carry out the silicon base etching, produce a shallow trench at least, then deposit an oxide layer, carry out the cmp planarization then, and oxide layer is eat-back to fill up shallow trench.This shallow trench will be isolated usefulness as the insulation between the memory cell.
(4) deposition second polysilicon layer, then ion injects second polysilicon layer, and etching second polysilicon layer is to form the second polysilicon gap wall.
(5) utilize etching that nitride layer is removed, then with wet oxide layer of soaking (Wet Dip) removal at the first polysilicon layer top.
(6) polysilicon dielectric film and the 3rd polysilicon layer in the deposition one then utilize the etching offset printing (lithography process) of the 3rd polysilicon layer, form control gate from the 3rd polysilicon layer.
The present invention proposes one of main member of lamination flash memory cell for thin first polysilicon float gate part and polysilicon gap wall floating grid part, can form the U-type three-dimensional space floating grid that is self-aligned to field oxide.This structure can be increased in the effective overlapping area between floating grid and control gate basically, therefore, is not needing to increase under the situation of memory cell area, can make memory cell reach higher grid coupling efficiency.Compare with existing 3-D floating grid structure, the present invention only needs three polysilicon films (the first floating grid part, the second floating grid part is with control gate).Moreover, in the present invention, use interior polysilicon dielectric film can reach gratifying data hold capacity with oxide layer/nitration case/oxide layer.
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Description of drawings
Fig. 1 a, 1b, 1c show existing a kind of manufacture method profile that forms flash memory cell;
Fig. 2 a, 2b, 2c, 2d, 2e, 2f, 2g show the existing another kind of manufacture method profile that forms flash memory cell;
Fig. 3 a is presented to form a tunneling oxide layer on the silicon base, first polysilicon layer that approaches, and an oxide layer and a mononitride layer that approaches then carries out the etching offset printing of first polysilicon layer, to form the first polysilicon laminate structure;
Fig. 3 b shows that silicon base is etched with the formation shallow trench, utilizes the deposition of oxide that shallow trench is filled up then, then utilizes chemical mechanical milling method and eat-backs oxide layer, and the oxide layer outside shallow trench is removed;
Fig. 3 c shows that the deposition, the ion that utilize second polysilicon layer inject and etching, form the second polysilicon layer clearance wall;
Fig. 3 d shows to utilize etching to remove nitride, utilizes wet the immersion oxide removal then, forms the tridimensional floating grid of a U-type; And
Fig. 3 e is presented at after interior polysilicon dielectric film of deposition and the 3rd polysilicon layer, carries out the etching offset printing of the 3rd polysilicon layer, with patterning control gate on the 3rd polysilicon layer, forms stack gate flash memory of the present invention.
The figure number explanation
1: tunneling oxide layer; 2: the first polysilicon layers; 3: thin oxide layer; 4: nitride layer; 5: shallow trench isolation; 6: the second polysilicon gap walls; 7: the first polysilicon laminate structures; 8:U-type floating grid; 11: interior polysilicon dielectric film; 12: control gate; 22: the first polysilicon films; 24: the second polysilicon films; 26: the silicon nitride cover curtain layer; 28: nitride spacer; 32: the first floating grids; 36: the second floating grids; 38: interior dielectric film; 40: the four polysilicon films; 42:BPSG; And 44: shallow concave groove is isolated.
The present invention discloses a kind of utilization and increases between floating grid (FG) and control gate (CG) overlapping Long-pending, increase control gate to the modified form overlapped grid flash memory unit of floating grid coupling efficiency. This The lamination flash memory cell of invention can utilize the method preparation of a novelty, and wherein floating grid has Tridimensional U-type structure, and under the coupling efficiency of not sacrificing between control gate and floating grid, Floating grid can be self-aligned to field oxide. Being applied in novel method of the present invention can make at floating grid Between the scope that limits of the more traditional basic etching lithographic printing of spacing more dwindle. Cause This, the present invention can make the yardstick of flash memory cell further dwindle, and can not cause too much Cost. The higher grid coupling efficiency that memory cell of the present invention proposes also can make memory cell exist Operate under the lower control-grid voltage.
Below for the detailed summary of key step of the present invention:
Deposition tunneling oxide layer (70-120 dust)
Deposit first polysilicon layer (300-1000 dust);
Implantation first polysilicon layer;
Deposition of thin oxide layer (300-1000 dust);
Nitride layer (～3000 dust) (as the CMP suspension layer);
Define the first polysilicon laminate structure with light shield;
The etching first polysilicon laminate structure;
The etching silicon substrate is to produce shallow trench;
Deposited oxide layer is to fill up shallow trench;
The cmp planarization with eat-back oxide layer;
Second polysilicon layer is done the cleaning of pre-deposition;
Deposit second polysilicon layer;
Implantation second polysilicon layer;
Etching second polysilicon layer is to form the second polysilicon gap wall;
Wet etching removes the nitride of sedimentary deposit;
With the wet oxide layer of removing at the first polysilicon layer top of soaking; Simultaneously, by more than first Crystal silicon layer and second polysilicon layer form U-type floating grid;
Polysilicon dielectric film in the deposition;
Deposit the 3rd polysilicon layer, the 3rd polysilicon layer subsequently can the formation control grid;
Define control gate with light shield; And
Etching control grid/floating grid is to form final memory cell.
As mentioned above, the method for preparing the lamination flash memory cell of the present invention has several Principal character comprises: (1) forms first polysilicon layer or the polycrystalline of the base section of floating grid Silicon fiml is self-aligned to the field oxide border, and first polysilicon film is quite thin, so that can use STI Planarisation step; (2) oxide and nitride layer can be used as sacrifice layer, in order to set up floating grid The height of alar part, and this two-layer all removal before second polysilicon layer deposition; (3) deposition second Polysilicon layer forms polysilicon gap wall with each border at first polysilicon layer pattern, also That is, the alar part of floating grid. The novel step that the inventive method forms polysilicon gap wall can make The floating grid that end form becomes is self-aligned to field oxide, in the overlapping section of the floating grid at field oxide top Divide the thickness that can utilize polysilicon gap wall to determine. Moreover the formation of clearance wall can make is floating The scope that the more traditional basic etching lithographic printing of spacing between grid limits is more dwindled, this 2 features will make the yardstick of flash memory further dwindle.
The present invention will utilize following embodiment to be described in more detail, but and unrestricted the present invention.
Fig. 3 a to Fig. 3 e shows according to a preferred embodiment manufacturing of the present invention, can increase the key step of the modified model stack gate flash memory of gate coupled between floating grid and control gate.
Shown in Fig. 3 a, on silicon base, form tunneling oxide layer 1, the first thin polysilicon layer 2, thin oxide layer 3 and nitride layer 4, then carry out the etching offset printing, to form the first polysilicon laminate structure 7.The thickness of oxide layer 3 can determine the final coupling efficiency between floating grid and control gate.Bigger thickness is more helpful to grid coupling efficiency, but can be increased in when forming shallow trench isolation subsequently, uses the difficulty of CMP (chemical mechanical milling method) planarization.
Shown in Fig. 3 b, utilize the silicon base etching to form shallow trench 5, deposited oxide layer is to fill up shallow trench subsequently.After this, utilize eat-backing of chemical mechanical milling method and oxide layer, remove the oxide layer outside shallow trench.
Fig. 3 c shows, on the border of the first polysilicon laminate structure 7, form the second polysilicon gap wall 6, the second polysilicon gap wall 6 at first utilizes deposition second polysilicon layer and ion to inject second polysilicon layer, forms with anisotropic etching second polysilicon layer then.
Shown in Fig. 3 d, form a U-type three-dimensional space floating grid 8, this floating grid 8 comprises from the alar part part of the base section of first polysilicon layer 2 and the second polysilicon gap wall 6.The formation of three-dimensional space U-type floating grid 8 is at first to utilize wet etching to remove nitride layer 4, then, and with the oxide layer 3 of wet immersion way removal at first polysilicon layer, 2 tops.The final height of the second polysilicon gap wall 6 can utilize the roll-in altitude of thin oxide layer, nitride layer and first polysilicon layer to decide.Wet immersion will consume the partial oxidation layer in shallow trench isolation 6, and the degree of consumption then must be looked closely the thickness of thin oxide layer 3 and be decided.Yet owing to the sidewall of the second polysilicon gap wall along tunneling oxide layer 1 exists, thereby tunneling oxide layer 1 can be protected, and can not encroached on by the HF that soaks that is not used for traditionally wetting.
Shown in Fig. 3 e, polysilicon dielectric film 11 and the 3rd polysilicon layer 12 in deposition carry out the etching offset printing to the 3rd polysilicon then, after the formation of patterning from the 3rd polysilicon layer control gate, form stack gate flash memory 10 of the present invention.Interior polysilicon dielectric film 11 all cooperates the profile of U-type three-dimensional space floating grid with the 3rd polysilicon layer 12 and forms.Therefore can be increased in the overlapping area of 12 of floating grid 8 and control gates subsequently, and increase the coupling efficiency between floating grid and control gate.Moreover because floating grid 8 also comprises formed alar part part from second polysilicon layer, the distance between therefore adjacent floating grid can shorten, so the present invention can further dwindle the yardstick of flash memory cell under the situation that does not promote the etching offset printing.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly know art technology person; without departing from the spirit and scope of the present invention; when can doing to change and retouching, so protection scope of the present invention is when looking accompanying Claim and being as the criterion in conjunction with the scope person of defining of specification and accompanying drawing.
Claims (15)
1. an overlapped grid flash memory unit manufacture method is characterized in that: comprise the following steps:
(a) deposition one tunneling oxide layer and one first polysilicon layer on a silicon base, ion injects this first polysilicon layer then;
(b) deposition one first oxide layer on this first polysilicon layer, and then deposition mononitride layer then carries out micro-photographing process to this first polysilicon layer, to form one first polysilicon laminate structure;
(c) this silicon base is carried out etching,, then deposit one second oxide layer to fill up this shallow trench in this silicon base, to produce a shallow trench at least;
(d) carry out the cmp planarization and eat-back oxide layer, exceed this second oxide layer of this shallow trench part with removal;
(e) deposition one second polysilicon layer, ion injects this second polysilicon layer then, and this second polysilicon layer of etching, in order to form one second polysilicon gap wall on the sidewall of this first polysilicon laminate structure;
(f) remove this nitride layer with wet etching, then with wet this first oxide layer removed at this first polysilicon layer top of soaking, wherein, this second polysilicon gap wall and this first polysilicon layer form a U-type three-dimensional space floating grid; And
(g) polysilicon dielectric film and one the 3rd polysilicon layer in the deposition one then carry out the etching lithography process to the 3rd polysilicon layer, in order to form a control gate from the 3rd polysilicon layer;
(h) wherein should cooperate the U-type three-dimensional space profile of this floating grid with this control gate by interior polysilicon dielectric film, so can increase the area overlapping part between this control gate and this floating grid.
2. a kind of overlapped grid flash memory unit manufacture method as claimed in claim 1 is characterized in that: wherein the thickness that this nitride layer deposited is to make this first polysilicon laminate structure consistent with the design height of this U-type floating grid.
3. a kind of overlapped grid flash memory unit manufacture method as claimed in claim 1 is characterized in that: wherein the thickness that deposited of this second polysilicon layer is consistent with the design spaces between adjacent floating grid.
4. a kind of overlapped grid flash memory unit manufacture method as claimed in claim 1, it is characterized in that: wherein this tunneling oxide layer has the thickness of one 70 dust to 100 dusts.
5. a kind of overlapped grid flash memory unit manufacture method as claimed in claim 1 is characterized in that: wherein this first polysilicon layer has the thickness of one 300 dust to 1000 dusts.
6. a kind of overlapped grid flash memory unit manufacture method as claimed in claim 1 is characterized in that: wherein this first oxide layer has the thickness of one 100 dust to 1000 dusts.
7. a kind of overlapped grid flash memory unit manufacture method as claimed in claim 1, it is characterized in that: wherein this nitride layer has the thickness of one 3000 dusts.
8. overlapped grid flash memory unit, it is characterized in that: lamination comprises:
(a) substrate is and at this suprabasil tunneling oxide layer;
(b) the U-type floating grid on this tunneling oxide layer, this U-type floating grid comprises a base section and an alar part part; And
(c) control gate, and between this floating grid and this control gate one in polysilicon oxidation sandwich layer structure, should cooperate the U-type profile of this floating grid with this control gate by interior polysilicon oxide layer, so can be increased in the area overlapping part between this control gate and this floating grid.
9. a kind of overlapped grid flash memory unit as claimed in claim 8 is characterized in that: the method for wherein making this structure comprises the following steps:
(a) deposition one tunneling oxide layer and one first polysilicon layer on a silicon base, ion injects this first polysilicon layer then;
(b) deposition one first oxide layer on this first polysilicon layer, and then deposition mononitride layer then carries out the etching offset printing to this first polysilicon layer, to form one first polysilicon laminate structure;
(c) this silicon base is carried out etching,, then deposit one second oxide layer to fill up this shallow trench in this silicon base, to produce a shallow trench at least;
(d) carry out the cmp planarization and eat-back oxide layer, exceed this second oxide layer of this shallow trench part with removal;
(e) deposition one second polysilicon layer, ion injects this second polysilicon layer then, and this second polysilicon layer of etching, in order to form one second polysilicon gap wall on the sidewall of this first polysilicon laminate structure;
(f) remove this nitride layer with wet etching, then with wet this first oxide layer removed at this first polysilicon layer top of soaking, wherein, this second polysilicon gap wall and this first polysilicon layer form a U-type three-dimensional space floating grid; And
(g) polysilicon dielectric film and one the 3rd polysilicon layer in the deposition one then carry out the etching lithography process to the 3rd polysilicon layer, in order to form a control gate from the 3rd polysilicon layer;
(h) wherein should cooperate the U-type three-dimensional space profile of this floating grid with this control gate by interior polysilicon dielectric film, so can increase the area overlapping part between this control gate and this floating grid.
10. a kind of overlapped grid flash memory unit as claimed in claim 9 is characterized in that: wherein the thickness that this nitride layer deposited is to make this first polysilicon laminate structure consistent with the design height of this U-type floating grid.
11. a kind of overlapped grid flash memory unit as claimed in claim 9 is characterized in that: wherein the thickness that deposited of this second polysilicon layer is consistent with the design spaces between adjacent floating grid.
12. a kind of overlapped grid flash memory unit as claimed in claim 9 is characterized in that: wherein this tunneling oxide layer has the thickness of one 70 dust to 100 dusts.
13. a kind of overlapped grid flash memory unit as claimed in claim 9 is characterized in that: wherein this first polysilicon layer has the thickness of one 300 dust to 1000 dusts.
14. a kind of overlapped grid flash memory unit as claimed in claim 9 is characterized in that: wherein this first oxide layer has the thickness of one 100 dust to 1000 dusts.
15. a kind of overlapped grid flash memory unit as claimed in claim 9 is characterized in that: wherein this nitride layer has the thickness of one 3000 dusts.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011101970A CN1172365C (en) | 2001-03-29 | 2001-03-29 | Overlapped grid flash memory unit and its producing method |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB011101970A CN1172365C (en) | 2001-03-29 | 2001-03-29 | Overlapped grid flash memory unit and its producing method |
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| CN1378271A true CN1378271A (en) | 2002-11-06 |
| CN1172365C CN1172365C (en) | 2004-10-20 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1324693C (en) * | 2003-07-24 | 2007-07-04 | 旺宏电子股份有限公司 | Manufacturing method of flash memory |
| WO2011134127A1 (en) * | 2010-04-28 | 2011-11-03 | 中国科学院微电子研究所 | Flash memory device and manufacturing method thereof |
| CN104795396A (en) * | 2014-01-21 | 2015-07-22 | 华邦电子股份有限公司 | Quick-flash memory and manufacture method thereof |
| CN105789212A (en) * | 2014-12-24 | 2016-07-20 | 上海格易电子有限公司 | Flash memory unit and fabrication method |
| CN106952924A (en) * | 2016-01-05 | 2017-07-14 | 台湾积体电路制造股份有限公司 | Flush memory device with high coupling ratio |
-
2001
- 2001-03-29 CN CNB011101970A patent/CN1172365C/en not_active Expired - Lifetime
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1324693C (en) * | 2003-07-24 | 2007-07-04 | 旺宏电子股份有限公司 | Manufacturing method of flash memory |
| WO2011134127A1 (en) * | 2010-04-28 | 2011-11-03 | 中国科学院微电子研究所 | Flash memory device and manufacturing method thereof |
| US8829587B2 (en) | 2010-04-28 | 2014-09-09 | Institute of Microelectronics, Chinese Academy of Sciences | Flash memory device and manufacturing method of the same |
| CN104795396A (en) * | 2014-01-21 | 2015-07-22 | 华邦电子股份有限公司 | Quick-flash memory and manufacture method thereof |
| CN104795396B (en) * | 2014-01-21 | 2018-06-22 | 华邦电子股份有限公司 | Flash memory and its manufacturing method |
| CN105789212A (en) * | 2014-12-24 | 2016-07-20 | 上海格易电子有限公司 | Flash memory unit and fabrication method |
| CN106952924A (en) * | 2016-01-05 | 2017-07-14 | 台湾积体电路制造股份有限公司 | Flush memory device with high coupling ratio |
| CN106952924B (en) * | 2016-01-05 | 2021-07-23 | 台湾积体电路制造股份有限公司 | Flash memory device with high coupling ratio |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1172365C (en) | 2004-10-20 |
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