CN1897256A - Method of manufacturing flash memory device - Google Patents
Method of manufacturing flash memory device Download PDFInfo
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- CN1897256A CN1897256A CNA2006101156370A CN200610115637A CN1897256A CN 1897256 A CN1897256 A CN 1897256A CN A2006101156370 A CNA2006101156370 A CN A2006101156370A CN 200610115637 A CN200610115637 A CN 200610115637A CN 1897256 A CN1897256 A CN 1897256A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000007667 floating Methods 0.000 claims abstract description 41
- 238000002955 isolation Methods 0.000 claims abstract description 22
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 58
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 19
- 229920005591 polysilicon Polymers 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 238000003475 lamination Methods 0.000 claims description 8
- 238000006396 nitration reaction Methods 0.000 claims description 7
- 229910052697 platinum Inorganic materials 0.000 claims description 7
- 229910052707 ruthenium Inorganic materials 0.000 claims description 7
- 229910007991 Si-N Inorganic materials 0.000 claims description 6
- 229910006294 Si—N Inorganic materials 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000010276 construction Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 229910052741 iridium Inorganic materials 0.000 claims description 4
- 238000003723 Smelting Methods 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052714 tellurium Inorganic materials 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 229910019899 RuO Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 claims 49
- 238000000231 atomic layer deposition Methods 0.000 claims 1
- 239000007792 gaseous phase Substances 0.000 claims 1
- 229910021332 silicide Inorganic materials 0.000 claims 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 1
- 239000002356 single layer Substances 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000005527 interface trap Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
Abstract
A method of manufacturing a flash memory device which can improve capacitance and can reduce the interference phenomenon. According to one embodiment, a method of manufacturing a flash memory device includes the steps of depositing a tunnel oxide layer over a semiconductor substrate having a isolation structure, depositing a conductive layers for a floating gate over the tunnel oxide layer, forming an oxide layer between the conductive layers for the floating gate, forming a recess pattern in the conductive layers for the floating gate, and depositing a dielectric layer and a conductive layer for a control gate, respectively.
Description
Technical field
The present invention relates generally to the method for making flash memory device, relate in particular to the method that wherein can insert electric capacity and can reduce the manufacturing flash memory device of interference phenomenon.
Background technology
Usually, flash memory device be meant a kind of according to electronics is injected and when not injecting floating grid variations in threshold voltage store device with reading of data.Increase along with the device integrated level needs flash memory device to possess service speed and high data reliability fast.For this purpose, be necessary to increase electric capacity.
In order to increase the electric capacity of flash memory device, proposed the high dielectric material as the method that is formed on the dielectric layer between floating grid and the control grid, reduce the method for this dielectric layer thickness, increase the method for coupling coefficient by the height that increases floating grid, or the like.
Yet, if the high dielectric material as dielectric layer owing to reduced interface trap characteristic (trap characteristic), and threshold voltage is shifted suddenly, thereby causes the low reliability of device.Therefore, be difficult to use this method.In addition, if reduced dielectric layer thickness, then can reduce puncture voltage, failure has direct influence to data for this.Therefore, there is restriction in the minimizing of dielectric layer thickness.
In addition, if increased the height of floating grid, the interference phenomenon between the then contiguous floating grid becomes more remarkable, and cell distribution is therefore extended.The result causes being difficult to guarantee the characteristic and the uniformity of device.
Summary of the invention
In one embodiment, the invention provides a kind of method of making flash memory device, this method can improve electric capacity and reduce interference phenomenon.
According to an aspect of the present invention, a kind of method of making flash memory device comprises step: deposit tunnel oxidation layer having at the semiconductor-based end of isolation structure, deposition is used for the conductive layer of floating grid on tunnel oxidation layer, be used for forming oxide layer between the conductive layer of this floating grid, form groove pattern and dielectric layer deposition and be used to control the conductive layer of grid respectively at the conductive layer that is used for this floating grid.
The conductive layer that is used for floating grid preferably can use polysilicon layer, W, WN, Ti, TiN, Pt, Ru, RuO
2, Ir, IrO
2Any one or its combination with Al.This polysilicon layer preferably can form the thickness of 100 to 5000 under 250 ℃ to 1000 ℃ temperature.
The conductive layer that is used for floating grid preferably can be formed by chemical vapor deposition (CVD) method or ald (ALD) method.
This oxide layer preferably can use high-density plasma (HDP) oxide layer, plasma enhancing-tetraethoxysilane (PE-TEOS), high-temperature oxide (HTO), senior plane layer (APL) oxide layer any one and form.
This groove pattern preferably can be etched to 100 by the conductive layer that will be used for floating grid and form to the thickness of 5000 , and this corrosion preferably utilizes Cl and F.
By utilizing ONO (oxide-nitride thing-oxide) layer, individual layer (Al for example
2O
3, HfO
2Or ZrO
2) or Al
2O
3, HfO
2Or ZrO
2In the sandwich construction that forms of two or more laminations, this dielectric layer preferably can form the thickness of 20 to 1000 .The oxide layer of this ONO preferably can form the thickness of 5 to 100 , and the nitration case of this ONO preferably forms the thickness of 10 to 100 .
The conductive layer that is used to control grid preferably can be by lamination polysilicon layer and metal level and is formed.This polysilicon layer preferably can form the thickness of 100 to 5000 , and this metal level preferably forms the thickness of 100 to 3500 , preferably uses any one of W, WN, Pt, Ir, Ru and Te.
Hard mask layer can further be formed on the conductive layer that is used to control grid.This hard mask layer preferably can utilize Si
3N
4Or Si-N and forming.This Si
3N
4Layer preferably can be formed by the smelting furnace method, and this Si-N is preferably formed by plasma method.
According to another aspect, the invention provides a kind of method of making flash memory device, comprise step: therein lamination form groove at the semiconductor-based end of tunnel oxidation layer, conductive layer and hard mask layer, form isolation structure and fill this groove to use isolated material, remove this hard mask layer exposing the top surface of this isolation structure, and form conductive layer dividing plate in each side of this isolation structure.
After forming this floating grid, this method may further include step: remove the predetermined thickness of this isolation structure, and comprising the conductive layer that forms dielectric layer on the whole surface of this floating grid and be used to control grid.
This conductive layer and conductive layer dividing plate preferably can be formed by polysilicon layer.
Depositing conducting layer on the total that removes hard mask preferably, this conductive layer of blanket etching forms the conductive layer dividing plate thus then.
This conductive layer preferably can form the thickness of 1nm to 100nm.This conductive layer dividing plate preferably can have than little 1/20 to 1/3 the width of first conductive layer.This active area preferably can have the width bigger than the field region.
Description of drawings
Complete understanding the present invention easily and attendant advantages thereof with reference to following detailed description also in conjunction with the accompanying drawings, can be understood the present invention and advantage thereof better, and identical reference symbol is represented same or analogous assembly in the accompanying drawing, wherein:
Figure 1A is the profile of method that the manufacturing flash memory device of first embodiment of the invention is shown to 1D; And
Fig. 2 A is the profile that the method for manufacturing flash memory device second embodiment of the invention is shown to 2F.
Embodiment
Describe the present invention in detail in conjunction with specific demonstration execution mode with reference to the accompanying drawings.
Figure 1A is the profile of method that the manufacturing flash memory device of first embodiment of the invention is shown to 1D.
Referring to Figure 1A, tunnel oxidation layer 104 is deposited over the semiconductor-based end 100 successively with the conductive layer 106 that is used for floating grid, has wherein formed isolation structure 102 in this semiconductor-based end 100.Conductive layer 106 can preferably use polysilicon layer, W, WN, Ti, TiN, Pt, Ru, the RuO that forms by CVD method or ALD method
2, Ir, IrO
2Any one or its combination with Al.Especially, doped polycrystalline silicon layer can form the thickness of 100 to 5000 preferably under 250 ℃ to 1000 ℃ temperature.
Referring to Figure 1B, the first photoresist figure (not shown) above formation on the conductive layer 106 is positioned at isolation structure 102.With the first photoresist figure is mask etching conductive layer 106, thereby forms conducting layer figure 106a.Peel off the first photoresist figure and then on whole surface, form oxide layer 108, buried between the conducting layer figure 106a in the middle of making.Then carry out planarization technology, 106a is exposed up to conducting layer figure.
Carry out the technology that forms oxide layer 108, to avoid the deviation of the second photoresist figure, when the core by etching conducting layer figure 106a formed groove pattern subsequently, the core of conducting layer figure 106a was exposed by this second photoresist figure.
Referring to Fig. 1 C, formed the second photoresist figure (not shown), expose the core of conducting layer figure 106a by this second photoresist figure.With this second photoresist figure is mask, and conducting layer figure 106a is by partly etching, thus formation groove pattern 110.When conducting layer figure 106a was etched, Cl and F preferably were used as etching gas.The etch depth of each conducting layer figure 106a preferably is arranged to 100 to 5000 .
After this, this second photoresist figure is peelled off, and oxide layer 108 is removed by wet etching process, forms the floating grid with conducting layer figure 106a thus, and the both sides of the edge projection of conducting layer figure 106a is higher than its core.Can guarantee to have this floating grid and have broad surface area.
Referring to Fig. 1 D, comprising formation dielectric layer 112 on the whole surface of conducting layer figure 106a.Dielectric layer 112 can have lamination wherein oxide layer, nitration case and thickness of oxide layer be preferably 20 to the ONO structure of 1000 , used such as Al
2O
3, HfO
2Or ZrO
2The high dielectric material individual layer or wherein lamination Al for example
2O
3, HfO
2And ZrO
2In two or more multilayer shape structures.
Have the situation of ONO structure for dielectric layer 112, this oxide layer can preferably form the thickness of 5 to 100 , and this nitration case can preferably form the thickness of 10 to 100 .
Polysilicon layer 114 (that is, being used to control the conductive layer of grid) and metal level 116 are formed at dielectric layer 112 successively.After forming hard mask layer 118 on the metal level 116, the laminated construction from hard mask layer 118 to conducting layer figure 106a is by graphical, to form grid.Polysilicon layer 114 preferably forms the thickness of 100 to 5000 , metal level 116 preferably use W, WN, Pt, Ir, Ru and Te any one and form the thickness of 100 to 3500 , and hard mask layer 118 is preferably by for example Si
3N
4Or the nitration case of Si-N forms.For example, can use the smelting furnace method to form Si
3N
4, can use plasma method to form Si-N.
Finished the manufacturing of the flash memory device of first embodiment of the invention thus.
Fig. 2 A to 2F is the profile that the method for manufacturing flash memory device second embodiment of the invention is shown.
Referring to Fig. 2 A, on the semiconductor-based end 20, formed tunnel oxidation layer 21 successively, be used for first conductive layer 22 and the hard mask layer 23 of floating grid.The semiconductor-based end 20 of hard mask layer 23, first conductive layer 22, tunnel oxidation layer 21 and desired depth, is etched, to form groove 24.Carry out lateral oxidation technology to eliminate the damage that during the etch process of groove 24, takes place.First conductive layer 22 can be formed by polysilicon layer, and hard mask layer 23 can be formed by nitration case.
In order to promote the etch process of groove, can further on hard mask layer 23, form hard mask layer.This hard mask layer can be by graphically, and can then utilize this patterned hard mask layer to carry out groove etching process for mask.
Referring to Fig. 2 B, on total, form oxide layer, so that bury groove 24.This oxide layer is carried out planarization technology, so that hard mask layer 23 is exposed.Therefore, in groove 24, form isolation structure 25, with definition active area and field region.
Referring to Fig. 2 C, peel off hard mask layer 23, with the top surface that exposes first polysilicon layer 22 and the side of isolation structure 25.
Referring to Fig. 2 D, on whole surface, deposited second conductive layer.Second conductive layer eat-backs (blanket etching-back) technology by the blanket formula and etched, forms conductive layer dividing plate 26 with the side at the isolation structure 25 that exposes, thereby forms the floating grid 27 with first conductive layer 22 and conductive layer dividing plate 26.
Second conductive layer preferably uses polysilicon layer and forms the thickness of 1nm to 100nm, and conductive layer dividing plate 26 preferably can have than first conductive layer, 22 little 1/20 to 1/3 width.
Referring to Fig. 2 E, the predetermined thickness of isolation structure 25 is etched by wet etching process, to reduce EFH (effective field height).Then on this whole surface, form dielectric layer 28.At this moment, can carry out wet technology, so that the top surface of isolation structure 25 is lower than the top surface of first conductive layer 22.Can use the ONO layer to form dielectric layer 28.
Referring to Fig. 2 F, lamination polysilicon layer and metal level successively on 28 layers of dielectric layers are formed for controlling the conductive layer 29 of grid.This polysilicon layer can form the thickness of 100 to 5000 , and this metal level can form the thickness of 100 to 3500 , preferably utilizes among W, WN, Pt, Ir, Ru and the Te any one.
After this, although do not illustrate in the drawings, conductive layer 29, gate dielectric layer 28 and the floating grid 27 that is used to control grid forms grid optionally by photoetching process and etched.
Finished the manufacturing of flash memory device second embodiment of the invention thus.
If (narrow technology) narrows down the distance between the conductive layer dividing plate 26 owing to narrow technology, estimate to be difficult in the conductive layer 29 that forms gate dielectric layer 28 between the conductive layer dividing plate 26 and be used to control grid.Owing to this reason, the second above-mentioned execution mode has proposed the 3rd execution mode of the present invention, wherein compares with this isolation structure, and the width of active area has significant modification.
If the width of active area increases, then increased the distance between the conductive layer dividing plate, and correspondingly formed the technology edge of dielectric layer and the conductive layer that is used to control grid.Except this active area had bigger width than the isolation structure in the 3rd execution mode, remaining technical construction was identical with second execution mode.
In the present invention, be used for the core of the conductive layer of floating grid, perhaps form the conductive layer dividing plate, make two edge protuberance of floating grid be higher than its core by both sides at the conductive layer that is used for floating grid by etching.Therefore, compare with correlation technique, coupling coefficient can increase more than 40%.Therefore, owing to can increase the electric capacity of flash memory device, thus can improve program rate, and can improve the reliability of this device.
In addition, can reduce along the cross section of the floating grid of bit line direction under the situation of electric capacity needing.Therefore this can reduce along the interference between the adjacent unit of bit line direction nearly more than 40%.In addition, because also increased, so can reduce along the interference between the adjacent unit of word-line direction along the distance between the adjacent unit of word-line direction.Therefore compare with correlation technique, this can make total interference phenomenon reduce half.
As previously mentioned, the present invention has the following advantages.
At first, because enlarged the surface area of floating grid, so can increase the area of the overlapping part between floating grid and the control grid.Therefore, can increase the electric capacity of flash memory device.
The second, because increased this electric capacity, thus can improve program rate, and reliability that can modifying device.
The 3rd, can reduce along the cross section of the floating grid of the vicinity of bit line direction, and can increase along the cross section of the floating grid of the vicinity of word-line direction.Therefore, can reduce interference phenomenon.
The 4th, owing to can reduce interference phenomenon, therefore can reduce the distribution of unit.Therefore, can more easily make high integrated equipment and multi-level unit equipment.
Although described the present invention in conjunction with practical exemplary embodiment, the present invention is not limited to disclosed these execution modes, and is opposite, can cover various modifications and equivalent feature within the spirit and scope of claims.
Claims (27)
1, a kind of method of making flash memory device comprises:
Deposit tunnel oxidation layer having at the semiconductor-based end of isolation structure;
Deposition is used for the conductive layer of floating grid on described tunnel oxidation layer;
Be used for forming oxide layer between the described conductive layer of floating grid;
Form groove pattern at the described conductive layer that is used for floating grid; And
Dielectric layer deposition and be used to control the conductive layer of grid respectively.
2, the method for claim 1 comprises: the described conductive layer that is formed for floating grid is selected from polysilicon layer, W, WN, Ti, TiN, Pt, Ru, RuO
2, Ir, IrO
2With Al or its combination.
3, method as claimed in claim 2 comprises: forming described polysilicon layer is under 250 ℃ to 1000 ℃ temperature, forms the thickness of 100 to 5000 .
4, the method for claim 1 comprises: the described conductive layer that is formed for floating grid by chemical gaseous phase depositing process or Atomic layer deposition method.
5, method as claimed in claim 1 comprises: any one that uses high-density plasma oxide layer, plasma enhancing-tetraethoxysilane, high-temperature oxide, senior plane layer oxide layer forms described oxide layer.
6, the method for claim 1 comprises: the described conductive layer that utilizes Cl and F will be used for floating grid etches into the thickness of 100 to 5000 , forms described groove pattern thus.
7, the method for claim 1 comprises: forming dielectric layer is the thickness of 20 to 1000 .
8, method as claimed in claim 1 comprises: use ONO (oxide-nitride thing-oxide) layer, by being selected from Al
2O
3, HfO
2And ZrO
2Single layer structure or Al that the composition of the group of forming forms
2O
3, HfO
2Or ZrO
2In the sandwich construction that forms of plural laminate layers form described dielectric layer.
9, method as claimed in claim 8 comprises: forming thickness is the oxide layers of 5 to the described ONO of 100 , and formation thickness is the nitration cases of 10 to the described ONO of 100 .
10, the method for claim 1 comprises: the described conductive layer that is formed for controlling grid forms by lamination polysilicon layer and metal level.
11, method as claimed in claim 10 comprises: forming thickness is the polysilicon layers of 100 to 5000 , and uses in the group of being made up of W, WN, Pt, Ir, Ru and Te any one, and forming thickness is the metal levels of 100 to 3500 .
12, the method for claim 1 further comprises: form hard mask layer being used to control on the described conductive layer of grid.
13, method as claimed in claim 12 comprises: forming described hard mask layer is to utilize Si
3N
4Perhaps Si-N forms.
14, method as claimed in claim 13 comprises: form described Si by the smelting furnace method
3N
4Layer, and form described Si-N by plasma method.
15, the method for claim 1 wherein forms described groove pattern by the core that etching is used for the described conductive layer of floating grid.
16, the method for claim 1, two edge protuberance of described floating grid are higher than its core.
17, a kind of method of making flash memory device comprises:
In the semiconductor-based end, form groove, wherein in the described semiconductor-based end lamination tunnel oxidation layer, conductive layer and hard mask layer;
Form isolation structure, fill described groove to use isolated material;
Remove described hard mask layer, to expose the top surface of described isolation structure; And
Each side at described isolation structure forms the conductive layer dividing plate.
18, method as claimed in claim 17 further comprises step:
After forming described floating grid, remove the predetermined thickness of described isolation structure; And
Comprising on the whole surface of described floating grid, forming dielectric layer and the conductive layer that is used to control grid.
19, method as claimed in claim 17 comprises: use polysilicon layer to form described conductive layer and described conductive layer dividing plate.
20, method as claimed in claim 17 comprises: by depositing conducting layer on described conductive layer and described isolation structure forming described conductive layer dividing plate, and the then described conductive layer of blanket etching.
21, method as claimed in claim 20 comprises: forming described conductive layer is the thickness of 1nm to 100nm.
22, method as claimed in claim 17, wherein said conductive layer dividing plate have than little 1/20 to 1/3 the width of described first conductive layer.
23, method as claimed in claim 17, wherein said active area have the width bigger than described field region.
24, method as claimed in claim 18, wherein said control grid are to be combined to form by metal, metal silicide and its.
25, method as claimed in claim 17, wherein said hard mask layer is to be formed by nitration case.
26, method as claimed in claim 17, wherein said hard mask layer is removed by wet etching process.
27, method as claimed in claim 18, the effective field aspect ratio floating grid of wherein said isolation structure is low.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR59855/05 | 2005-07-04 | ||
| KR1020050059855A KR100812942B1 (en) | 2005-07-04 | 2005-07-04 | Method of manufacturing a nand flash memory device |
| KR122895/05 | 2005-12-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1897256A true CN1897256A (en) | 2007-01-17 |
| CN100474569C CN100474569C (en) | 2009-04-01 |
Family
ID=37609714
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101156370A Expired - Fee Related CN100474569C (en) | 2005-07-04 | 2006-07-04 | Method of manufacturing flash memory device |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR100812942B1 (en) |
| CN (1) | CN100474569C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108133937A (en) * | 2017-12-21 | 2018-06-08 | 上海华力微电子有限公司 | Flush memory device and its manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100811472B1 (en) | 2006-10-16 | 2008-03-07 | 엘지전자 주식회사 | Plasma display apparatus |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020048260A (en) * | 2000-12-18 | 2002-06-22 | 박종섭 | Method of manufacturing a flash memory cell |
| KR100375231B1 (en) * | 2001-02-19 | 2003-03-08 | 삼성전자주식회사 | Method of fabricating non-volatile memory device |
-
2005
- 2005-07-04 KR KR1020050059855A patent/KR100812942B1/en not_active IP Right Cessation
-
2006
- 2006-07-04 CN CNB2006101156370A patent/CN100474569C/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108133937A (en) * | 2017-12-21 | 2018-06-08 | 上海华力微电子有限公司 | Flush memory device and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100474569C (en) | 2009-04-01 |
| KR20070004338A (en) | 2007-01-09 |
| KR100812942B1 (en) | 2008-03-11 |
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