CN1291491C - Polysilicon self-aligning contact plug and polysilicon sharing source electrode wire and method for making the same - Google Patents
Polysilicon self-aligning contact plug and polysilicon sharing source electrode wire and method for making the same Download PDFInfo
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- CN1291491C CN1291491C CN 02150428 CN02150428A CN1291491C CN 1291491 C CN1291491 C CN 1291491C CN 02150428 CN02150428 CN 02150428 CN 02150428 A CN02150428 A CN 02150428A CN 1291491 C CN1291491 C CN 1291491C
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Abstract
The present invention relates to a polysilicon self-aligning contact plug and a polysilicon sharing source electrode wire. The present invention is formed in a semiconductor component. The Semiconductor component comprises a first unit and a second unit, which are adjacent along the Y direction. Each unit comprises a first grid electrode structure and a second grid electrode structure, which are defined and formed on a surface of a semiconductor substrate. A side wall component is respectively formed on the side wall of the first grid electrode structure and the side wall of the second grid electrode structure. A source area is formed in a semiconductor silicon substrate between the first grid electrode structure and the second grid electrode structure. An opening is arranged. A drain electrode area is formed in the semiconductor silicon substrate. A contact hole is formed between the first unit and the second unit to expose a surface of the drain electrode area. A polysilicon self-aligning contact plug is formed in the contact hole. A polysilicon sharing source electrode wire is formed in the opening.
Description
Technical field
The present invention relates to a kind of semiconductor element and preparation method thereof, particularly a kind of polysilicon that is made in the top, drain region is aimed at contact plunger voluntarily, and a kind of polysilicon that is made in source region and top, shallow isolating trough zone is shared source electrode line.
Background technology
In the manufacturing of semiconductor element, include: the manufacturing of memory module (as: mask ROM, flash memory, can erase and programmable read only memory) and logic module (as: microprocessor, controller, CMOS inductor), all can utilize and aim at the contact plunger manufacture method voluntarily and make the position between the grid structure more close to reach the purpose of minification, and for for contact plunger that formation shop, drain region is connected, this can't make between grid structure and the contact plunger and run into problem of short-circuit.In addition, need make one along the direction of character line and share source electrode line, connect the source region in the memory cell in being used for.
United States Patent (USP) the 6th, 194 discloses a kind of contact plunger manufacture method of aiming at voluntarily, can ignore the spacing between contact plunger and grid for No. 784.See also Fig. 5 A to 5C, it shows existing generalized section along bit line direction of aiming at the contact plunger manufacture method voluntarily.Shown in Fig. 5 A, include several source regions 41 and drain region 42 in the semiconductor substrate 40, and the surperficial upward definition in the semiconductor-based ends 40 there are several grid structures 44.Each grid structure 44 is by 49 of a grid oxic horizon 45, a floating gate layer 46, a dielectric layer 47, a control grid layer 48 and tungsten silicide layers storehouse and constituting in regular turn, and the surface of each grid structure 44 can be covered by an insulating barrier 50 and an etching stopping layer 51.Aim at voluntarily in the contact plunger manufacture method existing,, go up definition then in dielectric layer 52 surfaces and form a photoresist layer 54 with an opening 55 prior to deposition one dielectric layer 52 on the whole surface at the semiconductor-based end 40.Follow-up shown in Fig. 5 B, utilize photoetching and dry ecthing manufacture method, the dielectric layer 52 and the insulating barrier 50 of opening 55 belows are removed, to form a contact hole 56, can expose the surface of drain region 42.Then photoresist layer 54 is removed.Then shown in Fig. 5 C, in contact hole 56, fill up a conductive layer 58, aim at contact plunger voluntarily to provide as one.But when definition contacted the pattern in hole 56 in dielectric layer 52, the deposition of use, photoetching diminished with the optics tolerance that the etching manufacture method can cause contacting hole 56, and can increase the manufacture method cost.
United States Patent (USP) the 6th, 294 discloses a kind of method No. 431, shares source electrode line with one and imbeds the oxide in field below, and admixture injected share source electrode line.Fig. 6 A shows the existing top view of sharing the source electrode line manufacture method, and Fig. 6 B is the existing generalized section of sharing the source electrode line manufacture method of tangent line IV-IV demonstration along Fig. 6 A.On a silicon 60 surfaces, several effective coverages 64 form with several polysilicon layers 62 and intersect vertically, and constitute isolated effect by an oxide in field 66 between the two adjacent effective coverages 64.In addition, definition has a presumptive area 68 between two adjacent polysilicon layers 62, is the position that is used for making source electrode line and source region.At first, utilize and to aim at source electrode voluntarily (definition earlier forms a photo-resistive mask 70 for self-aligned source, SAS) manufacture method, and its zone line that is parallel to two polysilicon layers 62 is to cover the drain region.Then, carry out ion injection method, can make admixture pass through oxide in field 66 and inject silicon 60, to form a flush type silicon layer 72 with high dopant concentration.Subsequently, inject, can in the effective coverage 64 of strip, form several source regions 74, and source region 74 can be electrically connected to flush type silicon layer 72 by further ion.Thus, the flush type silicon layer 72 that is positioned at oxide in field 66 belows can become one and shares source electrode line.Yet this production method can't guarantee to share the electric continuity in the source electrode line.
In addition, United States Patent (USP) the 6th, 218 discloses a kind of method No. 265, is to use SAS manufacture method collocation inclination angle type ion to inject (tilted ion implantation) manufacture method, can make a shared source electrode line in the semiconductor silicon base.But, in opening, carry out the process that etching and inclination angle type ion inject, can run into the problem on the manufacture method, still remain to be improved.
Summary of the invention
Main purpose of the present invention is to provide a polysilicon to aim at contact plunger voluntarily on the drain region, and in source region and shallow isolating trough zone (shallow trench isolation, STI) provide a polysilicon to share source electrode line on, to solve the problem that prior art was produced.
The present invention proposes in a kind of semiconductor element, includes along Y direction adjacent a first module and Unit one second, includes in each unit: a first grid structure and a second grid structure, and definition is formed on the surface of semiconductor silicon base; One sidewall is formed at respectively on the sidewall of this first grid structure and this second grid structure; The one source pole zone is formed in the semiconductor silicon substrate between this first grid structure and this second grid structure; And an opening, be formed between this first grid structure and this second grid structure, to expose the surface of this source region.One drain region is formed in the semiconductor silicon substrate between the first grid structure of the second grid structure of this first module and this Unit second.One contact hole is formed between this first module and this Unit second, to expose the surface of this drain region.One polysilicon is aimed at contact plunger voluntarily, is formed in this contact hole.One polysilicon is shared source electrode line, is formed in this opening of this first module and this Unit second.
An advantage of the present invention is, the present invention makes polysilicon and aims at voluntarily in the step of contact plunger in the contact hole, do not need additionally to carry out deposition, photoetching and the etching of a dielectric layer, just can define the pattern of finishing contact plunger, therefore can improve the optics tolerance of contact plunger.
Another advantage of the present invention is, the inventive method can be formed at the surface of shallow isolating trough zone and each source region along the shared source electrode line definition that X-direction is extended, and therefore can not run into the relevant issues of carrying out etching and the injection of inclination angle type ion in opening.
Description of drawings
Fig. 1 is the layout top view of the memory module of first embodiment of the invention;
Fig. 2 A aims at the generalized section of the manufacture method of contact plunger with 2B voluntarily for the tangent line I-I along Fig. 1 shows the polysilicon of first embodiment of the invention;
Fig. 2 C is the generalized section of arranging along X-direction along the drain region of the tangent line II-II demonstration first embodiment of the invention of Fig. 1;
Fig. 2 D is the generalized section that shows the shared source electrode line of first embodiment of the invention along the tangent line III-III of Fig. 1;
Fig. 3 is the layout top view of the memory module of second embodiment of the invention;
Fig. 4 A shows the generalized section that the polysilicon of second embodiment of the invention is aimed at contact plunger voluntarily for the tangent line I-I along Fig. 3;
Fig. 4 B is the generalized section of arranging along X-direction along the drain region of the tangent line II-II demonstration second embodiment of the invention of Fig. 3;
Fig. 4 C is the generalized section that shows the shared source electrode line of second embodiment of the invention along the tangent line III-III of Fig. 3;
Fig. 5 A to 5C is existing generalized section along bit line direction of aiming at the contact plunger manufacture method voluntarily;
Fig. 6 A is the existing top view of sharing the source electrode line manufacture method;
Fig. 6 B is the existing generalized section of sharing the source electrode line manufacture method along the tangent line IV-IV of Fig. 6 A;
Symbol description
In the prior art:
The semiconductor-based end of 40--; The 41--source region; The 42--drain region; The 44--grid structure;
The 45--grid oxic horizon; The 46--floating gate layer; The 47--dielectric layer; 48--controls grid layer;
The 49--tungsten silicide layer; The 50--insulating barrier; The 51--etching stopping layer; The 52--dielectric layer;
The 54--photoresist layer; The 55--opening; 56--contacts the hole; The 58--conductive layer; The 60--silicon;
The 62--polysilicon layer; The 66--oxide in field; The 64--effective coverage; The 68--presumptive area;
The 70--photo-resistive mask; 72--flush type silicon layer; The 74--source region.
In the technology of the present invention:
STI--shallow isolating trough zone; WL
1--first character line; WL
2--second character line;
CSL--shares source electrode line; The C--polysilicon is aimed at contact plunger voluntarily;
The substrate of 10--semiconductor silicon; 12A, 12B, 12C, 12D--gate stack structure;
The 13--grid oxic horizon; The 14--floating gate layer; The 15--ONO three-decker;
16--controls grid layer; The 17--tungsten silicide layer; 18--silicon nitride cap rock;
The 20--source region; The 22--drain region; 24--sidewall;
The 26--opening; 28--contacts the hole; The 30--polysilicon layer;
The 30A--polysilicon is aimed at contact plunger voluntarily; The 30B--polysilicon is shared source electrode line.
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and conjunction with figs. is described in detail below:
The invention provides a kind of manufacture method of semiconductor element, mainly be that polysilicon is aimed at the contact plunger manufacture method voluntarily, can make the polysilicon contact plunger be electrically connected to a polysilicon and share source electrode line, and the present invention can be applicable to include in the manufacturing of various semiconductor elements: the manufacturing of memory module (as: mask ROM, flash memory, can erase and programmable read only memory) and logic module (as: microprocessor, controller, CMOS inductor).
First embodiment
Fig. 1 is the layout top view of the memory module of first embodiment of the invention.Fig. 2 A aims at the generalized section of the manufacture method of contact plunger with 2B voluntarily for the tangent line I-I along Fig. 1 shows the polysilicon of first embodiment of the invention, Fig. 2 C is the generalized section of arranging along X-direction along the drain region of the tangent line II-II demonstration first embodiment of the invention of Fig. 1, and Fig. 2 D is the generalized section that shows the shared source electrode line of first embodiment of the invention along the tangent line III-III of Fig. 1.
As shown in Figure 1, be example with a flash memory component, several shallow isolating trough zone STI definables go out a memory cell arrays.In each memory cell, include first a character line WL along the X-direction extension
1, second a character line WL who extends along X-direction
2, the shared source electrode line CSL that extends along X-direction of a bit line that extends along Y direction and, shared source electrode line CSL wherein is arranged at the first character line WL
1With the second character line WL
2Between, and shared source electrode line CSL can be electrically connected with several source regions formation.In addition, a polysilicon is aimed at contact plunger C voluntarily and is formed at top, a drain region, and can share this drain region along two adjacent memory cell of Y direction.
Shown in Fig. 2 A, on Y direction, definition has several gate stack structures 12A, 12B, 12C, 12D on the surface of semiconductor silicon base 10, can provide as several word line architectures.Each gate stack structure 12 be by 18 on a grid oxic horizon 13, a floating gate layer 14, an ONO three-decker 15, a control grid layer 16, a tungsten silicide layer 17 and a silicon nitride cap rock in regular turn storehouse form.The making in one source pole zone 20, be that admixture is flow in the semiconductor silicon substrate 10 between two adjacent gate stack structure 12A, the 12B, in the same manner, admixture is flow in the semiconductor silicon substrate 10 between two adjacent gate stack structure 12C, the 12D, also can form another source region 20.The making of one drain region 22 is that admixture is flow in the semiconductor silicon substrate 10 between two adjacent gate stack structure 12B, the 12C.In addition, by the deposition and the anisotropic etching manufacture method of dielectric layer, can form sidewall 24 on the sidewall of each gate stack structure 12, its material can be selected oxide or nitride for use.In addition, an opening 26 be formed at respectively between two adjacent gate stack structure 12A, the 12B and two adjacent gate stack structure 12C, 12D between, in order to expose the surface of each source region 20; One contact hole 28 is formed between two adjacent gate stack structure 12B, the 12C, in order to expose drain region 22.
Aiming at voluntarily in the manufacture method of contact plunger at the polysilicon of first embodiment of the invention, shown in Fig. 2 B, is earlier a polysilicon layer 30 to be deposited on the whole surface of semiconductor silicon substrate 10, until arriving the thickness that can fill up opening 26 and contact hole 28.Then, use etching mode or cmp (chemical mechanical polishing, CMP) method, polysilicon layer 30 is carried out etch-back trim until the apical side height of apical side height that makes polysilicon layer 30 and silicon nitride cap rock 18, then residuing in polysilicon layers 30 in the contact hole 28 becomes a polysilicon and aims at contact plunger 30A voluntarily.And the polysilicon layer 30 that residues in the opening 26 becomes the shared source electrode line 30B of a polysilicon, and it can be electrically connected the source region 20 that is provided with along the character line direction.
Shown in Fig. 2 C, on X-direction, polysilicon is aimed at contact plunger 30A definition voluntarily and is formed on the surface of each drain region 22, but can expose the surface of shallow isolating trough zone STI.Shown in Fig. 2 D, on X-direction, share source electrode line 30B definition and be formed on the surface of shallow isolating trough zone STI and each source region 20.
Compared to prior art, the present invention makes polysilicon and aims at voluntarily in the step of contact plunger 30A in contact hole 28, do not need additionally to carry out deposition, photoetching and the etching of a dielectric layer, just can define the pattern of finishing contact plunger 30A, so the inventive method can improve the optics tolerance of contact plunger 30A.And, aim at source electrode (self-aligned source voluntarily compared to existing use, SAS) manufacture method or shallow isolating trough manufacture method (shallow trench isolation, STI) and the inclination angle type ion of arranging in pairs or groups inject (tilted ion implantation) manufacture method, the inventive method can be formed at the surface of shallow isolating trough zone STI and each source region 20 along the shared source electrode line 30B definition that X-direction is extended, and therefore can not run into the relevant issues of carrying out etching and the injection of inclination angle type ion in opening.
Second embodiment
Fig. 3 shows the layout top view of the memory module of second embodiment of the invention.Fig. 4 A shows the generalized section that the polysilicon of second embodiment of the invention is aimed at contact plunger voluntarily for the tangent line I-I along Fig. 3, Fig. 4 B is the generalized section of arranging along X-direction along the drain region of the tangent line II-II demonstration second embodiment of the invention of Fig. 3, and Fig. 4 C is the generalized section that shows the shared source electrode line of second embodiment of the invention along the tangent line III-III of Fig. 3.
As shown in Figure 3, be example with a flash memory component, several shallow isolating trough zone STI definables go out a memory cell arrays.In each memory cell, include first a character line WL along the X-direction extension
1, second a character line WL who extends along X-direction
2, the shared source electrode line CSL that extends along X-direction of a bit line that extends along Y direction and, shared source electrode line CSL wherein is arranged at the first character line WL
1With the second character line WL
2Between, and shared source electrode line CSL can be electrically connected with several source regions formation.In addition, a polysilicon is aimed at contact plunger C voluntarily and is formed at top, a drain region, and can share this drain region along two adjacent memory cell of Y direction.
Shown in Fig. 4 A, on Y direction, definition has several gate stack structures 12A, 12B, 12C, 12D on the surface of semiconductor silicon base 10, can provide as several word line architectures.Each gate stack structure 12 be by 18 on a grid oxic horizon 13, a floating gate layer 14, an ONO three-decker 15, a control grid layer 16, a tungsten silicide layer 17 and a silicon nitride cap rock in regular turn storehouse form.The making in one source pole zone 20, be that admixture is flow in the semiconductor silicon substrate 10 between two adjacent gate stack structure 12A, the 12B, in the same manner, admixture is flow in the semiconductor silicon substrate 10 between two adjacent gate stack structure 12C, the 12D, also can form another source region 20.The making of one drain region 22 is that admixture is flow in the semiconductor silicon substrate 10 between two adjacent gate stack structure 12B, the 12C.In addition, by the deposition and the anisotropic etching manufacture method of dielectric layer, can form sidewall 24 on the sidewall of each gate stack structure 12, its material can be selected oxide or nitride for use.In addition, an opening 26 be formed at respectively between two adjacent gate stack structure 12A, the 12B and two adjacent gate stack structure 12C, 12D between, in order to expose the surface of each source region 20; One contact hole 28 is formed between two adjacent gate stack structure 12B, the 12C, in order to expose drain region 22.
Aim at voluntarily in the manufacture method of contact plunger at the polysilicon of second embodiment of the invention, system is deposited on a polysilicon layer 30 on the whole surface of semiconductor silicon substrate 10 earlier, but its thickness is little than first embodiment, 30 of polysilicon layers can fill up opening 26 but can not fill up contact hole 28, so 30 of polysilicon layers can be deposited on the sidewall and the bottom in contact hole 28.Then, use photoetching and dry ecthing mode, 30 definition of polysilicon layer in the contact hole 28 are become a polysilicon aim at contact plunger 30A voluntarily, and with the shared source electrode line 30B of 30 definition becoming of the polysilicon layer in the opening 26 polysilicon, it can be electrically connected the source region 20 that is provided with along the character line direction.
Shown in Fig. 4 B, on X-direction, polysilicon is aimed at contact plunger 30A definition voluntarily and is formed on the surface of each drain region 22, but can expose the surface of shallow isolating trough zone STI.Shown in Fig. 4 C, on X-direction, share source electrode line 30B definition and be formed on the surface of shallow isolating trough zone STI and each source region 20.
Though the present invention with a preferred embodiment openly as above; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; change and retouching when doing some equivalences, so protection scope of the present invention is as the criterion with claim.
Claims (21)
1. a semiconductor element is characterized in that, includes:
One first module, it includes: a first grid structure and a second grid structure, definition is formed on the surface of semiconductor silicon base; One sidewall is formed at respectively on the sidewall of this first grid structure and this second grid structure; The one source pole zone is formed in the semiconductor silicon substrate between this first grid structure and this second grid structure; And an opening, be formed between this first grid structure and this second grid structure, to expose the surface of this source region;
Unit one second, and includes adjacent to this first module along Y direction: a first grid structure and a second grid structure, and definition is formed on the surface of this semiconductor silicon substrate; One sidewall is formed at respectively on the sidewall of this first grid structure and this second grid structure; The one source pole zone is formed in the semiconductor silicon substrate between this first grid structure and this second grid structure; And an opening, be formed between this first grid structure and this second grid structure, to expose the surface of this source region;
One drain region is formed in the semiconductor silicon substrate between the first grid structure of the second grid structure of this first module and this Unit second;
One contact hole is formed between this first module and this Unit second, to expose the surface of this drain region;
One polysilicon is aimed at contact plunger voluntarily, is formed in this contact hole; And
One polysilicon is shared source electrode line, is formed in this opening of this first module and this Unit second.
2. semiconductor element as claimed in claim 1 is characterized in that, it is to fill up this contact hole fully that this polysilicon is aimed at contact plunger voluntarily.
3. semiconductor element as claimed in claim 1 is characterized in that, this polysilicon is aimed at sidewall and the bottom that contact plunger is formed at this contact hole voluntarily.
4. semiconductor element as claimed in claim 1 is characterized in that, also includes:
Unit one the 3rd, and includes adjacent to this first module along X-direction: a first grid structure and a second grid structure, and definition is formed on the surface of this semiconductor silicon substrate; One sidewall is formed at respectively on the sidewall of this first grid structure and this second grid structure; The one source pole zone is formed in the semiconductor silicon substrate between this first grid structure and this second grid structure; And an opening, be formed between this first grid structure and this second grid structure, to expose the surface of this source region; And
One shallow isolating trough zone is formed in this semiconductor silicon substrate, and can completely cut off the source region of this first module and the source region of Unit the 3rd.
5. semiconductor element as claimed in claim 4 is characterized in that, it is to be formed at this shallow isolating trough zone and this first module along X-direction to this source region of Unit the 3rd that this polysilicon is shared source electrode line.
6. semiconductor element as claimed in claim 1 is characterized in that, the material of this sidewall of this first module and this Unit second is oxide or silicide.
7. semiconductor element as claimed in claim 1, it is characterized in that, this semiconductor element can be following any, includes: mask ROM, flash memory, can erase and programmable read only memory, microprocessor, controller and CMOS inductor.
8. semiconductor element as claimed in claim 1 is characterized in that, each grid structure be by a grid oxic horizon, a floating gate layer, an ONO three-decker, a control grid layer and cap rock institute in regular turn storehouse form.
9. semiconductor element as claimed in claim 8 is characterized in that each grid structure includes a tungsten silicide layer in addition, is arranged between this control grid layer and this cap rock.
10. the manufacture method of a semiconductor element is characterized in that, includes the following step:
Semiconductor element is provided, it includes along Y direction adjacent a first module and Unit one second, wherein include respectively in this first module and this Unit second: a first grid structure and a second grid structure, definition is formed on the surface of semiconductor silicon base; One sidewall is formed at respectively on the sidewall of this first grid structure and this second grid structure; The one source pole zone is formed in the semiconductor silicon substrate between this first grid structure and this second grid structure; And an opening, be formed between this first grid structure and this second grid structure, to expose the surface of this source region; And, include a drain region in the semiconductor silicon substrate between the first grid structure of the second grid structure of this first module and this Unit second; And, between this first module and this Unit second, include a contact hole, can expose the surface of this drain region;
Form a polysilicon layer, covering the whole surface of this semiconductor silicon substrate, and fill up this opening and this contact hole; And
Carry out cmp, the apical side height of this polysilicon layer and the apical side height of this grid structure are trimmed, then residuing in polysilicon layer in this contact hole becomes a polysilicon and aims at contact plunger voluntarily, becomes a polysilicon and shares source electrode line and residue in polysilicon layer in this opening.
11. the manufacture method of semiconductor element as claimed in claim 10 is characterized in that, includes in addition on this semiconductor element:
Unit one the 3rd, and includes adjacent to this first module along X-direction: a first grid structure and a second grid structure, and definition is formed on the surface of this semiconductor silicon substrate; One sidewall is formed at respectively on the sidewall of this first grid structure and this second grid structure; The one source pole zone is formed in the semiconductor silicon substrate between this first grid structure and this second grid structure; And an opening, be formed between this first grid structure and this second grid structure, to expose the surface of this source region; And
One shallow isolating trough zone is formed in this semiconductor silicon substrate, and can completely cut off the source region of this first module and the source region of Unit the 3rd.
12. the manufacture method of semiconductor element as claimed in claim 11, wherein to share source electrode line be to be formed at this shallow isolating trough zone and this first module along X-direction to this source region of Unit the 3rd to this polysilicon.
13. the manufacture method of semiconductor element as claimed in claim 10 is characterized in that, the material of this sidewall of this first module and this Unit second is oxide or silicide.
14. the manufacture method of semiconductor element as claimed in claim 10, it is characterized in that, this semiconductor element can be following any, includes: mask ROM, flash memory, can erase and programmable read only memory, microprocessor, controller and CMOS inductor.
15. the manufacture method of semiconductor element as claimed in claim 10 is characterized in that, each grid structure be by a grid oxic horizon, a floating gate layer, an ONO three-decker, a control grid layer and cap rock institute in regular turn storehouse form.
16. the manufacture method of a semiconductor element is characterized in that, includes the following step:
Semiconductor element is provided, it includes along Y direction adjacent a first module and Unit one second, wherein include respectively in this first module and this Unit second: a first grid structure and a second grid structure, definition is formed on the surface of semiconductor silicon base; One sidewall is formed at respectively on the sidewall of this first grid structure and this second grid structure; The one source pole zone is formed in the semiconductor silicon substrate between this first grid structure and this second grid structure; And an opening, be formed between this first grid structure and this second grid structure, to expose the surface of this source region; And, include a drain region in the semiconductor silicon substrate between the first grid structure of the second grid structure of this first module and this Unit second; And, between this first module and this Unit second, include a contact hole, can expose the surface of this drain region;
Form a polysilicon layer, to cover the whole surface of this semiconductor silicon substrate, make this polysilicon layer fill up this opening, but this polysilicon layer does not fill up this contact hole fully; And
The definition of polysilicon layer in this contact hole is become a polysilicon aim at contact plunger voluntarily, and the definition becoming of the polysilicon layer in this an opening polysilicon is shared source electrode line.
17. the manufacture method of semiconductor element as claimed in claim 16 is characterized in that, includes in addition on this semiconductor element:
Unit one the 3rd, and includes adjacent to this first module along X-direction: a first grid structure and a second grid structure, and definition is formed on the surface of this semiconductor silicon substrate; One sidewall is formed at respectively on the sidewall of this first grid structure and this second grid structure; The one source pole zone is formed in the semiconductor silicon substrate between this first grid structure and this second grid structure; And an opening, be formed between this first grid structure and this second grid structure, to expose the surface of this source region; And
One shallow isolating trough zone is formed in this semiconductor silicon substrate, and can completely cut off the source region of this first module and the source region of Unit the 3rd.
18. the manufacture method of semiconductor element as claimed in claim 17 is characterized in that, it is to be formed at this shallow isolating trough zone and this first module along X-direction to this source region of Unit the 3rd that this polysilicon is shared source electrode line.
19. the manufacture method of semiconductor element as claimed in claim 16 is characterized in that, the material of this sidewall of this first module and this Unit second is oxide or silicide.
20. the manufacture method of semiconductor element as claimed in claim 16, it is characterized in that, this semiconductor element can be following any, includes: mask ROM, flash memory, can erase and programmable read only memory, microprocessor, controller and CMOS inductor.
21. the manufacture method of semiconductor element as claimed in claim 16 is characterized in that, each grid structure be by a grid oxic horizon, a floating gate layer, an ONO three-decker, a control grid layer and cap rock institute in regular turn storehouse form.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02150428 CN1291491C (en) | 2002-11-12 | 2002-11-12 | Polysilicon self-aligning contact plug and polysilicon sharing source electrode wire and method for making the same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02150428 CN1291491C (en) | 2002-11-12 | 2002-11-12 | Polysilicon self-aligning contact plug and polysilicon sharing source electrode wire and method for making the same |
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| CN1291491C true CN1291491C (en) | 2006-12-20 |
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| JP5951096B1 (en) * | 2015-10-01 | 2016-07-13 | 株式会社フローディア | Nonvolatile semiconductor memory device |
| CN110718462B (en) * | 2018-07-10 | 2022-01-18 | 联华电子股份有限公司 | Method for fabricating semiconductor structure on semiconductor wafer |
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