CN1224093C - Method for making separated-grating quick-acting storage and structure thereof - Google Patents
Method for making separated-grating quick-acting storage and structure thereof Download PDFInfo
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Abstract
The present invention relates to a manufacturing method and a structure of separated grid-type flash memory. The present invention comprises a basal plate which is provided with a source region and a drain region, a floating grid structure, a control grid, a third insulation layer, a control grid sidewall layer, a second oxide layer and a contact sidewall layer. The manufacturing method mainly comprises the steps that the semiconductor basal plate is provided, and a grid oxide layer, a first conducting layer and a sacrificial layer are formed on the semiconductor basal plate; a part of the sacrificial layer is removed to form at least one groove, a first oxide layer is formed above the sacrificial layer and in the groove, and the first oxide layer is flattened until the surface of the sacrificial layer is exposed; the sacrificial layer, the partial grid oxide layer which does not cover the first oxide layer and the first conducting layer are removed to form the floating grid structure on the semiconductor basal plate.
Description
Technical field
The present invention relates to a kind of manufacture method and structure of separated-grating quick-acting storage, the multiple autoregistration of particularly a kind of use (self-alignment) technology, and the manufacture method and the structure of dwindling the separated-grating quick-acting storage of memory cell size.
Background technology
The electric memory element of formula programmable read only memory (EEPROM) of erasing for the extensive employing of information electronic product now, the slower shortcoming of access speed was arranged originally, yet along with the progress of manufacturing process, developed access speed EEPROM faster in recent years, generally be referred to as fast storage.Basically, typical fast storage is constituted with the floating grid transistor arrangement, when carrying out sequencing, when writing data, apply a high voltage in the control gate polar region, make hot electron pass tunnel oxide and inject floating grid, improve its critical voltage from gate regions; When erasing data, then apply a high voltage in source area, make the aforementioned electronics that is injected into floating grid to wear effect then by so-called Fowler-Nordheim, pass tunneling oxide layer and flow into source area, make it reply original critical voltage.Yet; in the process of erasing; in order to ensure with the complete sucking-off of injection electronics in the floating grid; usually can prolong the time of erasing; the result often causes the phenomenon of excessively erasing; make critical voltage low excessively, become depletion type (depletion) transistor of a normal open (on), destroyed the due characteristic of assembly.
In order to solve the problem of excessively erasing, so-called " separated-grating quick-acting storage " structure is suggested, and wherein each memory cell is to be in series by a floating grid transistor and a reinforced isolated transistor.Like this, even the phenomenon that the generation of floating grid transistor is excessively erased, transistor still can make whole memory keep closing state, keeps the due characteristic of assembly.
Fig. 1-1 to Fig. 1-11 be the profile of the common quick memory of separated grid formation method, the formation method and the structure of common separated-grating quick-acting storage is described by above-mentioned icon.
Open the beginning step as Figure 1-1, substrate 10 is the semi-conducting material just like silicon, germanium and so on, for simplicity, is example at this with a n type silicon substrate.
At first, on this n type substrate 10, form a grid oxic horizon 12, one first conducting shell 14 and one first insulating barrier 16 in regular turn, at first, form this grid oxic horizon 12 on these substrate 10 surfaces, about 80 dusts of the thickness of this grid oxic horizon 12, for instance, be the one silica layer that constitutes with silicon monoxide formation method.Then, first conductive layer 14 that forms about 800 dusts of thickness is on this grid oxic horizon 12, this first conductive layer 14 can be made of the polysilicon layer of chemical vapour deposition technique (CVD) deposition, for making this first conductor electricity layer have conductivity, can use for example is diffusion or ion method implanting ions, perhaps utilizes the mode of mixing synchronously to form the doping compound crystal silicon layer.Then, form this first insulating barrier 16 on these first conductive layer, 14 surfaces, the silicon nitride that this first insulating barrier 16 can low-pressure chemical vapor deposition (LPCVD) method deposit thickness be about 800 dusts constitutes.
Then, whole base plate is carried out shallow flute isolate (shallow trench isolation) manufacture craft flow process formation field insulating layer, and isolate the active region (not shown) with this field insulating layer.
Then, forming one on whole base plate 10 surfaces is made of silicon nitride, and thickness is approximately the insulating barrier of 2500A, because its material is identical with aforesaid first insulating barrier 16 on the aforesaid substrate 10, for convenience of explanation, just with one second resilient coating 18, represent aforementioned first insulating barrier 16 of this insulating barrier and same material.
Then,, remove this second resilient coating 18 of part, defining some grooves 17, and the surface of this first conductive layer 14 caused the shape of depression, shown in Fig. 1-2 with little shadow manufacture craft flow process and etching step.Then, as Figure 1-3, form one second oxide layer 20 on this second resilient coating 18 and in these grooves 17, this second oxide layer 20 can be the silica with about 3000 dusts of silica thickness that formation method is constituted.Next, flat this second oxide layer 20 of brush is until the surface of exposing this second resilient coating 18, and this step can be to finish with chemical mechanical milling method (CMP), shown in Fig. 1-4.
Then, with little shadow manufacturing process and etching step, remove this second resilient coating 18 and this first conductive layer 14 of part, to define first opening 21.Then shown in Fig. 1-5, implant p type foreign ion in semiconductor substrate 10, semiconductor substrate 10 top layers in first opening form one source pole district S.
Consult Fig. 1-6, form a buffer oxide layer 22 in this second resilient coating 18, second oxide layer, 20 surfaces, and extend in this first opening 21, cover the sidewall and the bottom of this first opening 21, this buffer oxide layer 22 is constituted with the silica that Low Pressure Chemical Vapor Deposition (LPCVD) deposits.Then, this source area of horizontal proliferation S becomes S ', remove the buffer oxide layer 22 of this second resilient coating 18, second oxide layer, 20 surfaces and these first opening, 21 bottoms then with the etching manufacturing process, sidewall at this first opening 21 forms the first buffering side wall layer 22a, this etching manufacturing process can the iso dry-etching of right and wrong, shown in Fig. 1-7.
Then, form one second conductive layer (not shown) on this second resilient coating 18, second oxide layer, 20 surfaces, this second conductive layer fills up in this first opening 21.This second conductive layer can be that the polysilicon layer that the thickness with Low Pressure Chemical Vapor Deposition (LPCVD) deposition is approximately 3000 dusts is constituted, for making this first conductor electricity layer have conductivity, can use as diffusion or ion method implanting ions, perhaps utilize the mode of mixing synchronously to form doped polysilicon layer.And remove this second conductive layer on this second resilient coating 18, second oxide layer, 20 surfaces, and only keeping part in first opening to form contact plunger 24, this step can be the planarization manufacturing process, for example finishes with cmp (CMP).Then, form on the surface of this contact plunger of one the 3rd oxide layer 26 in this first opening, this the 3rd oxide layer 26 can be the silica that is approximately 200 dusts with Low Pressure Chemical Vapor Deposition (LPCVD) deposit thickness, after being formed on this second resilient coating 18, second oxide layer 20 and contact plunger 24 surperficial going up, remove this second resilient coating 18, second oxide layer, 20 lip-deep the 3rd oxide layers 26 again, only keep the part on the contact plunger 24 in this first opening, shown in Fig. 1-8.
Then, with little shadow manufacturing process and etching step, remove this second resilient coating 18, this first conductive layer 14 and this grid oxic horizon 12 of part, to define second opening 27.Then, form one the 4th oxide layer 28 and one the 3rd conductive layer 30 in regular turn on this second oxide layer 20 and the 3rd oxide layer 26 surfaces, and extend in this second opening 27, cover the sidewall and the bottom of this second opening 27, the 4th oxide layer 28 in addition is to be the silica of 170 dusts with the thickness that the silica forming method is constituted for instance.Then, the 3rd conductive layer 30 is formed on the 3rd oxide layer 26, this the 3rd conductive layer 30 can be made of the compound crystal silicon layer of chemical vapour deposition technique (CVD) deposit thickness by 2000 dusts, for making this first conductor electricity layer have conductivity, can use as diffusion or ion method implanting ions, perhaps utilize the mode of mixing synchronously to form doped polysilicon layer, shown in Fig. 1-9.
Then, carry out the etch-back manufacturing process, remove second oxide layer 20 and the 3rd oxide layer 26 surfaces, and the 3rd conductive layer 30 of second opening, 27 bottoms, the 4th oxide layer 28 surfaces at second opening, 27 sidewalls form the conductive side parietal layer, and this conductive side parietal layer is control grid 32.Secondly, serve as that cover curtain implantation p type foreign ion enters semiconductor substrate 10 with this control grid 32,27 semiconductor substrate 10 surfaces form drain region D in second opening, shown in Fig. 1-10.
Then, comprise in this second opening that form inner-dielectric-ayer (ILD) 34, then, this inner-dielectric-ayer 34 of etching part is to define a contact hole 35 on whole surface.At last, form a metal conducting layer 36 in whole surface, and in this contact hole 35, as the intraconnections (bit lineinterconnect) of bit line, as shown in Fig. 1-11.
Because the increase rapidly of memory integrated level, for reaching the requirement of high integration, the size of all component all must be dwindled, the manufacturing process of above-mentioned common fast storage is to rely on light shield to define the size and location of assembly, because the precision of light shield has its limit, and for the less assembly of live width, the degree of difficulty that light shield is aimed at greatly improves, as long as little shadow deviation (misalign) slightly just is enough to cause the short circuit of semiconductor subassembly circuit or open circuit, make this assembly lose the function of original design.Shown in Fig. 1-11, in order to prevent as the control grid 32 of word line and metal conducting layer 36 short circuits as bit line, and the generation misoperation, so often between control grid and metal conducting layer 36, be provided with a buffer distance and this is isolated with insulating barrier, yet in semiconductor today of downsizing day by day, this buffer distance is a big obstacle for dwindling memory-size.
Summary of the invention
The objective of the invention is to propose a kind of manufacture method and structure of separated-grating quick-acting storage, its autoregistration (self-alignment) technology that can make full use of, not only be suitable for producing the fast storage manufacturing process flow process of high closeness, to make fast storage be to avoid the zone reserved because of little shadow deviation, the size that can dwindle separated-grating quick-acting storage effectively but also save tradition.
For achieving the above object, the manufacture method of separated-grating quick-acting storage provided by the invention comprises the following steps:
A: the semiconductor substrate is provided, and shape has a grid oxic horizon, one first conductive layer and a sacrifice layer thereon;
B: remove this sacrifice layer of part, and on this first conductive layer, form at least one groove;
C: forming one first oxide layer on this sacrifice layer and on the groove on this first conductive layer;
D: this first oxide layer of planarization is until the surface of exposing this sacrifice layer;
E: this grid oxic horizon of part and this first conductive layer removing this sacrifice layer and do not cover this first oxide layer, to form the floating grid structure on this semiconductor substrate, wherein this floating grid structure has one first side and with respect to one second side of this first side;
F: form one second oxide layer, one second silicon nitride layer in regular turn on whole surface;
G: remove this second silicon nitride layer of part, define first opening with first side in this floating grid structure;
H: this second silicon nitride layer and this second oxide layer of part of removing another part, define one second opening with second side in this floating grid structure, and residue another part this second oxide layer on first side of this floating grid structure, and in this second opening, on the sidewall of second side of this floating grid structure, form a contact side parietal layer;
I: the semiconductor substrate top layer in this second opening forms the one source pole district;
J: form one second conductive layer and one the 3rd silicon nitride layer in regular turn in this first opening and second opening;
K: remove this second conductive layer of part and the 3rd silicon nitride layer, define one the 3rd opening with first side in this floating grid structure, and in the 3rd opening, form the control gate electrode structure, wherein this control gate electrode structure comprises remaining this second conductive layer and the 3rd silicon nitride layer on remaining second oxide layer;
L: form one the 3rd oxide layer on whole surface and in the 3rd opening;
M: remove part the 3rd oxide layer, define one the 4th opening, and in the 4th opening, on the sidewall of this control gate electrode structure, form a control gate lateral wall layer with first side in this floating grid structure; And
N: with this control gate lateral wall layer is the cover curtain, and the semiconductor substrate top layer in the 4th opening forms the drain region.
This method comprises also that after step n one forms one the 3rd conductive layer on whole surface and in this second opening, to form the step of bit line structure.
Above-mentioned steps j: its indication forms one second conductive layer in regular turn and the step of one the 3rd silicon nitride layer in this first and second opening then also comprises:
After forming this second conductive layer, this second conductive layer that this second opening of etch-back is outer; And
Form the 3rd silicon nitride layer in this second opening, and the 3rd outer silicon nitride layer of this second opening of etch-back.
Said first, second and the 3rd conductive layer are made of polysilicon; Said sacrifice layer is one first silicon nitride layer that is made of silicon nitride; Said grid oxic horizon, first oxide layer, second oxide layer and the 3rd oxide layer are made of Si oxide;
In the said step I, comprise that one is implanted in the semiconductor substrate ion to form the step of this source region; Afterwards, also comprise the step of carrying out a tempering (anneal), wherein this tempering step is approximately in temperature under 900 ℃ the condition and carries out.
A kind of separated-grating quick-acting storage that proposes according to the present invention, comprising: a substrate has an one source pole district and a drain region;
One floating grid structure, stand on to insulation this substrate surface, this floating grid structure is made of a grid oxic horizon, a floating grid and one first oxide layer in regular turn, and has one first side and with respect to one second side of this first side, wherein this second side is positioned at this source area top;
One second oxide layer, be formed on first side of this floating grid structure, and an end of this second oxide layer extends on the upper surface of this first oxide layer, and the upper surface of this first oxide layer is partly to expose, and its other end extends on the upper surface of this substrate, and this second oxide layer has the set thickness greater than the thickness of this grid oxic horizon;
One control grid is arranged on the sidewall of this second oxide layer, and this control grid by this second oxide layer extend to the other end on this upper surface of base plate and this substrate insulate;
One silicon nitride layer is arranged on the upper surface of this control grid;
One control gate lateral wall layer is arranged on the sidewall of this control grid and this silicon nitride layer, and above the substrate between this control grid and the drain region; And
One contact side parietal layer is arranged on second side of this floating grid structure, and is positioned at the top of this source area.
Said contact side parietal layer comprises first, second sidewall, this the first side wall is to be arranged on second side of this floating grid, and this second sidewall is to be arranged on the sidewall of this first side wall, and an end of this first side wall extends between this second sidewall and this source area.
This structure also comprises one the 3rd oxide layer, forms on the whole semiconductor substrate, only the surface of exposed portions serve control grid top, this control gate lateral wall layer and this drain region.
By the present invention, autoregistration (self-alignment) technology can make full use of, not only be suitable for the fast storage manufacturing process flow process of high closeness, make the zone that fast storage is reserved in order to avoid little shadow deviation but also save tradition, thereby the size that can dwindle the separable grid fast storage effectively.
Description of drawings
Fig. 1-1 is the profile of the formation method of the quick memory of common separated grid to Fig. 1-11.
Fig. 2-1 is the profile of the manufacture method of the quick memory of separated grid of the present invention to Fig. 2-14.
Embodiment
Fig. 2-1 is the profile of the quick memory of separated grid of the present invention formation method to Fig. 2-14, and the formation method and the structure of separated-grating quick-acting storage of the present invention is described by above-mentioned accompanying drawing.
Open the beginning step shown in Fig. 2-1, substrate 110 is the semi-conducting material just like silicon, germanium and so on, for simplicity, is example at this with a n type silicon substrate.
At first, carry out step (a), on this n type substrate 110, form a grid oxic horizon 112, one first conductive layer 114 and a sacrifice layer 116 in regular turn, at first, form this grid oxic horizon 112 on these substrate 110 surfaces, this grid oxic horizon 112 can be the silica that is constituted with the silica forming method, about 80 dusts of thickness.Then, first conductive layer 114 that forms about 800 dusts of thickness is on this grid oxic horizon 112, this first conductive layer 114 can be made of the polysilicon layer of chemical vapour deposition technique (CVD) deposition, for making this first conductor electricity layer have conductivity, can use for example is diffusion or ion method implanting ions, perhaps utilizes the mode of mixing synchronously to form doped polysilicon layer.Then, form this sacrifice layer 116 on these first conductive layer, 114 surfaces, this sacrifice layer 116 (that is first silicon nitride layer) can be the silicon nitride formation that is about 1600 dusts by the thickness of low-pressure chemical vapor deposition (LPCVD) method deposition.
Then, whole base plate is carried out shallow trench isolation form field insulating layer, and isolate the active region (not shown) with this field insulating layer from (shallow trench isolation) manufacture craft flow process.
Then, on whole base plate 110 surfaces, form the silicon nitride layer that a thickness is approximately 2500 dusts, because the material of the sacrifice layer 116 on this silicon nitride layer and the aforesaid substrate is all silicon nitride, represent the aforementioned sacrifice layer 116 of aforementioned silicon nitride layer and same material for convenience of explanation with a sacrifice layer 116 '.
Then carry out step (b),, remove this sacrifice layer 116 ' of part, defining at least one groove 117, and the surface of this first conductive layer 114 caused the shape of depression, shown in Fig. 2-2 with little shadow manufacturing process and etching step.Then, carry out step (c), as shown in figure 24, upward reach formation one first oxide layer 118 in these grooves 117 at this sacrifice layer 116 ', this first oxide layer 118 is made of the silica of about 3000 dusts of thickness.
Next, carry out step (d), this first oxide layer 118 of planarization, until the surface of exposing this sacrifice layer 116 ', this step can be to finish with chemical mechanical milling method (CMP).
Then, carry out step (e),, remove this sacrifice layer with little shadow manufacturing process and etching step.116 ', and part this first conductive layer 114 and grid oxic horizon 112 ' of not covering this first oxide layer 118, to form at least one floating grid structure G1 on this semiconductor substrate, shown in Fig. 2-4.
Then, carry out step (f), form one second oxide layer 122 and one second insulating barrier 124 in regular turn on whole surface, for instance, this second oxide layer 122 can be the silica that the silica forming method is constituted, about 150 dusts of thickness.In addition, form this second insulating barrier 124 on these second oxide layer, 122 surfaces, for instance, this second insulating barrier 124 (promptly, second silicon nitride layer) can be that the silicon nitride that thickness by a low-pressure chemical vapor deposition (LPCVD) method deposition is about 350 dusts is constituted, shown in Fig. 2-5.
Then, carry out step (g),, remove this second insulating barrier 124 of part, to define first opening 121 with little shadow manufacturing process and etching step.Shown in Fig. 2-6.
Then, carry out step (h),, remove this second insulating barrier 124 of another part with little shadow manufacturing process and etching step, and this second oxide layer 122, to define second opening 123, shown in Fig. 2-7.Then, carry out step (I), sidewall at this second opening 123 forms contact side parietal layer 125, wherein this contact side parietal layer 125 has first and second sidewall 1221,1241, and this first side wall 1221 is to be formed after etching by this second oxide layer 122, in addition, this second sidewall 1241 is formed after etching by this second insulating barrier 124.Secondly, implant concentration is 15 * 10
3To 4 * 10
14Phosphorus, form one source pole district S as the p type impurity ion in semiconductor substrate 110 top layers of semiconductor substrate 110 in second opening 123.
After the above-mentioned steps (i), comprise that also one is implanted in this semiconductor substrate 110 with after forming this source region S at this ion, carry out the step of a tempering (anneal), this tempering step carries out under the condition of 900 ℃ of about temperature, as shown in Fig. 2-8.
Then, carry out step (j), form one second conductive layer 126 and one the 3rd insulating barrier 128 in regular turn in this first opening 121 and second opening 123.For instance, this second conductive layer 126 can a Low Pressure Chemical Vapor Deposition (LPCVD) the deposition one thickness polysilicon layer that is approximately 3000 dusts constitute, for making this second conductor electricity layer have conductivity, can use for example is diffusion or ion method implanting ions, perhaps utilizes the mode of mixing synchronously to form doped polysilicon layer.And remove in this second conductive layer on this floating grid structure G1 and these second oxide layer, 122 surfaces, only keep the part in first, second opening 121,123, and form a contact plunger 1261 in this second opening 123, this step is a planarization manufacturing process, for example can finish by cmp (CMP).
Then, form the 3rd insulating barrier 128 in this first and second opening 121, on the surface of second conductive layer 126 in 123, for instance, this the 3rd insulating barrier 128 (promptly, the 3rd silicon nitride layer) can be deposited on this floating grid structure G1 by the silicon nitride that the thickness with Low Pressure Chemical Vapor Deposition (LPCVD) deposition is approximately 2000 dusts, after go up on this second oxide layer 122 and this second conductive layer 126 surfaces, remove again this floating grid structure G1 and this second oxygen he the layer 122 lip-deep the 3rd insulating barrier 128, only keep this first, second opening 121, these second conductive layer, 126 lip-deep parts in 123 are shown in Fig. 2-9.
Then, carry out step (k), with little shadow manufacturing process and etching step, remove part the 3rd insulating barrier 128 and second conductive layer 126, defining the 3rd opening, and form control gate electrode structure 130, wherein in the sidewall of the 3rd opening 129, above-mentioned second conductive layer 126 in this control gate electrode structure 130 is as a control grid 1262, shown in Fig. 2-10.
Then, carry out step (1), form one the 3rd oxide layer 132 on whole surface and in the 3rd opening 129, for instance, this the 3rd oxide layer 132 can be that the silicon nitride that the thickness with a low-pressure chemical vapor deposition (LPCVD) method deposition is about 500 dusts is constituted, shown in Fig. 2-11.
Afterwards, carry out step (m), remove this second oxide layer of part, defining the 4th opening, and form a control gate side wall layer in the 4th opening.Shown in Fig. 2-12, with little shadow manufacturing process and etch-back step, remove part the 3rd oxide layer 132, defining the 4th opening 133, and form conductive side parietal layers 134 in control gate electrode structure 130 surfaces of the 4th opening 133 sidewalls.
At last, carrying out step (n), serves as the cover curtain with this control gate lateral wall layer 134, and implant concentration is 60K to 4 * 10
14Arsenic, enter semiconductor substrate 110 as p type foreign ion, 133 semiconductor substrate, 110 surfaces form drain region D in the 4th opening, so far promptly finish the manufacturing of the memory cell of grid separate type fast storage, shown in Fig. 2-13.
In addition, the manufacture method of this grid separate type fast storage more is included in whole surface and comprises in the 4th opening 133, forms a polysilicon conducting layers 136 with as line within the bit line (bitline interconnect), shown in Fig. 2-14.
The structure of the separated-grating quick-acting storage that the present invention proposes, as shown in Fig. 2-13, comprise semiconductor substrate 110, a floating grid structure G1, a control grid 1262, one the 3rd insulating barrier 128, control gate lateral wall layer 134, one second oxide layer 122 and a contact side parietal layer 125.
Above-mentioned semiconductor substrate 110 has an one source pole district S and a drain region D on its top layer; And this floating grid structure G1, insulation ground stands on these semiconductor substrate 110 surfaces and is positioned at above the side of this source S.Secondly, this controls grid 1262, is coated on to insulation on the semiconductor substrate 110 between this source S and drain D.
In addition, this second insulating barrier 128 is formed on these control grid 1262 surfaces; And this control gate side wall layer 134 is formed on the sidewall of this control grid 1262 and the 3rd insulating barrier 128, and is positioned at semiconductor substrate 110 tops between this control grid 1262 and this drain D.
In addition, this second oxide layer 122 is formed between control grid 1262 and the floating grid structure G1, and an end extends to the top of this floating grid structure G1, and the other end extends to the below of this control grid 1262; And this contact side parietal layer 125, be formed on the sidewall of this floating grid structure G1, and be positioned at the top of this source S.
This floating grid structure G1, by first oxide layer 118 ', a floating grid 114 ' and a grid oxic horizon 112 ' with overlap mode, be formed at the side top of source S in this semiconductor substrate 110, grid oxic horizon 112 ' is positioned between floating grid 114 ' and this substrate, and this first oxide layer 118 ' is formed at the top of this floating grid.
In addition, this contact side parietal layer 125 comprises that by this second oxide layer 122 and this second insulating barrier 124 via etch-back formed one first, second sidewall 1221,1241, an end of this first side wall 1221 also extends between this second sidewall 1241 and this source S.
Also have the 3rd oxide layer 132, be formed on the whole semiconductor substrate 110, only the surface of exposed portions serve control grid 1262 tops, this control gate side wall layer 134 and this drain region D.
At last, can also shown in Fig. 2-14, on the surface of this drain region, form a polysilicon conducting layers 136 with intraconnections (bit line interconnect) as bit line.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; anyly have the knack of this operator; without departing from the spirit and scope of the present invention; can do some and change and retouching, so protection scope of the present invention should be as the criterion with the scope that extremely sharp claim was defined of present patent application.
Claims (10)
1. the manufacture method of a separated-grating quick-acting storage, this method comprises the following steps:
A: provide the semiconductor substrate, on it and be formed with a grid oxic horizon, one first conductive layer and a sacrifice layer;
B: remove this sacrifice layer of part, and on this first conductive layer, form at least one groove;
C: forming one first oxide layer on this sacrifice layer and on the groove on this first conductive layer;
D: this first oxide layer of planarization is until the surface of exposing this sacrifice layer;
E: this grid oxic horizon of part and this first conductive layer removing this sacrifice layer and do not cover this first oxide layer, to form the floating grid structure on this semiconductor substrate, wherein this floating grid structure has one first side and with respect to one second side of this first side;
F: form one second oxide layer, one second silicon nitride layer in regular turn on whole surface;
G: remove this second silicon nitride layer of part, define first opening with first side in this floating grid structure;
H: this second silicon nitride layer of removing another part, and this second oxide layer of part, define one second opening with second side in this floating grid structure, and residue another part this second oxide layer on first side of this floating grid structure, and in this second opening, on the sidewall of second side of this floating grid structure, form a contact side parietal layer;
I: the semiconductor substrate top layer in this second opening forms the one source pole district;
J: form one second conductive layer and one the 3rd silicon nitride layer in regular turn in this first opening and second opening;
K: remove this second conductive layer of part and the 3rd silicon nitride layer, define one the 3rd opening with first side in this floating grid structure, and in the 3rd opening, form the control gate electrode structure, wherein this control gate electrode structure comprises remaining this second conductive layer and the 3rd silicon nitride layer on remaining second oxide layer;
L: form one the 3rd oxide layer on whole surface and in the 3rd opening;
M: remove part the 3rd oxide layer, define one the 4th opening, and in the 4th opening, on the sidewall of this control gate electrode structure, form a control gate lateral wall layer with first side in this floating grid structure; And
N: with this control gate lateral wall layer is the cover curtain, and the semiconductor substrate top layer in the 4th opening forms the drain region.
2. the manufacture method of separated-grating quick-acting storage as claimed in claim 1 is characterized in that, after step n, comprises that also a formation one the 3rd conductive layer reaches in the 4th opening to form the step of bit line structure on whole surface.
3. the manufacture method of separated-grating quick-acting storage as claimed in claim 1 is characterized in that, described step j: form one second conductive layer in regular turn and the step of one the 3rd silicon nitride layer in this first and second opening comprises:
After forming this second conductive layer, this second conductive layer that this second opening of etch-back is outer; And
Form the 3rd silicon nitride layer in this second opening, and the 3rd outer silicon nitride layer of this second opening of etch-back.
4. the manufacture method of separated-grating quick-acting storage as claimed in claim 2 is characterized in that, described first, second and the 3rd conductive layer are made of polysilicon.
5. the manufacture method of separated-grating quick-acting storage as claimed in claim 1 is characterized in that, described sacrifice layer is one first silicon nitride layer that is made of silicon nitride.
6. the manufacture method of separated-grating quick-acting storage as claimed in claim 1 is characterized in that, described grid oxic horizon, first oxide layer, second oxide layer and the 3rd oxide layer are made of Si oxide.
7. the manufacture method of separated-grating quick-acting storage as claimed in claim 1 is characterized in that, in described step I, comprises that one is implanted in ion in the semiconductor substrate, to form the step of this source area.
8. the manufacture method of separated-grating quick-acting storage as claimed in claim 7, it is characterized in that, be implanted in this semiconductor substrate with after forming this source area at described ion, also comprise the step of a tempering, this tempering step carries out under the about 900 ℃ condition of temperature.
9. separated-grating quick-acting storage comprises:
One substrate has an one source pole district and a drain region;
One floating grid structure, stand on to insulation this substrate surface, this floating grid structure is made of a grid oxic horizon, a floating grid and one first oxide layer in regular turn, and has one first side and with respect to one second side of this first side, wherein this second side is positioned at this source area top;
One second oxide layer, be formed on first side of this floating grid structure, and an end of this second oxide layer extends on the upper surface of this first oxide layer, and the upper surface of this first oxide layer is partly to expose, and its other end extends on the upper surface of this substrate, and this second oxide layer has the set thickness greater than the thickness of this grid oxic horizon;
One control grid is arranged on the sidewall of this second oxide layer, and this control grid by this second oxide layer extend to the other end on this upper surface of base plate and this substrate insulate;
One silicon nitride layer is arranged on the upper surface of this control grid;
One control gate lateral wall layer is arranged on the sidewall of this control grid and this silicon nitride layer, and above the substrate between this control grid and the drain region; And
One contact side parietal layer is arranged on second side of this floating grid structure, and is positioned at the top of this source area.
10. separated-grating quick-acting storage as claimed in claim 9, it is characterized in that, described contact side parietal layer comprises first, second sidewall, this the first side wall is to be arranged on second side of this floating grid, and this second sidewall is to be arranged on the sidewall of this first side wall, and an end of this first side wall extends between this second sidewall and this source area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02105016.3A CN1224093C (en) | 2002-02-10 | 2002-02-10 | Method for making separated-grating quick-acting storage and structure thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02105016.3A CN1224093C (en) | 2002-02-10 | 2002-02-10 | Method for making separated-grating quick-acting storage and structure thereof |
Publications (2)
| Publication Number | Publication Date |
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| CN1438694A CN1438694A (en) | 2003-08-27 |
| CN1224093C true CN1224093C (en) | 2005-10-19 |
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| CN02105016.3A Expired - Lifetime CN1224093C (en) | 2002-02-10 | 2002-02-10 | Method for making separated-grating quick-acting storage and structure thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010066126A1 (en) * | 2008-12-10 | 2010-06-17 | 上海宏力半导体制造有限公司 | Method for manufacturing split gate type flash memory |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6416595B2 (en) * | 2014-11-14 | 2018-10-31 | ラピスセミコンダクタ株式会社 | Semiconductor device and manufacturing method of semiconductor device |
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2002
- 2002-02-10 CN CN02105016.3A patent/CN1224093C/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010066126A1 (en) * | 2008-12-10 | 2010-06-17 | 上海宏力半导体制造有限公司 | Method for manufacturing split gate type flash memory |
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| Publication number | Publication date |
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| CN1438694A (en) | 2003-08-27 |
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