CN1279619C - Vertical ROM and its making process - Google Patents
Vertical ROM and its making process Download PDFInfo
- Publication number
- CN1279619C CN1279619C CN02101573.2A CN02101573A CN1279619C CN 1279619 C CN1279619 C CN 1279619C CN 02101573 A CN02101573 A CN 02101573A CN 1279619 C CN1279619 C CN 1279619C
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- substrate
- layer
- memory
- read
- rectilinear
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 229920005591 polysilicon Polymers 0.000 claims abstract description 21
- 239000004020 conductor Substances 0.000 claims description 37
- 230000002262 irrigation Effects 0.000 claims description 25
- 238000003973 irrigation Methods 0.000 claims description 25
- 150000002500 ions Chemical class 0.000 claims description 21
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 238000005468 ion implantation Methods 0.000 claims description 14
- 238000002347 injection Methods 0.000 claims description 13
- 239000007924 injection Substances 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 13
- 238000009792 diffusion process Methods 0.000 claims description 12
- 230000000994 depressogenic effect Effects 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 229910021332 silicide Inorganic materials 0.000 claims description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 4
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 claims description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 108091026890 Coding region Proteins 0.000 abstract 1
- 238000004140 cleaning Methods 0.000 description 5
- 239000007943 implant Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- -1 boron difluoride ion Chemical class 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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Abstract
The present invention relates to a vertical ROM and a making process thereof. A channel is formed in a substrate, a source electrode/drain electrode is made on the bottom of the channel, and a grid electrode is formed on the surface of the substrate; a polysilicon bit line electrically connected with the source electrode/drain electrode is arranged in the channel, polysilicon and the substrate at the side wall of the channel are isolated by a dielectric layer, and the side wall of the channel is used as a coding region.
Description
Technical field
The invention relates to a kind of semiconductor subassembly and technology thereof, and particularly relevant for a kind of rectilinear read-only memory (vertical read-only memory) and technology thereof.
Background technology
Each memory cell of known read-only memory only can store data (1 cell 1bit), and the limited size of memory cell is in the technological ability of live width, and therefore, assembly is difficult for miniaturization.In addition, because the mode of coding is to inject and source/different high concentration ion of drain electrode dopant profile in raceway groove, to reach the purpose that improves starting voltage, and will be because of the factor of CONCENTRATION DISTRIBUTION in the mode of implanting ions, and make starting voltage that the difference that just differs be arranged, cause the phenomenon of assembly generation leakage current.
Summary of the invention
Purpose of the present invention just provides a kind of rectilinear read-only memory and technology thereof, has the starting voltage better than known read-only memory and distributes.
Another object of the present invention just provides a kind of rectilinear read-only memory and technology thereof, can reduce the phenomenon of leakage current.
According to above-mentioned and other purpose, the present invention proposes a kind of rectilinear read-only memory, and it forms irrigation canals and ditches in substrate, and makes source/drain in the bottom of irrigation canals and ditches, and forms grid on the surface of substrate; Establish the polysilicon bit line that electrically connects with source/drain in the irrigation canals and ditches, the substrate of polysilicon and trench sidewall is completely cut off with dielectric layer, and with the sidewall of irrigation canals and ditches as the code area.
As mentioned above, because the trench sidewall of the source side of read-only memory of the present invention and the trench sidewall of drain side are all as the code area, so each memory cell can store the data (1 cell, 2 bit) of two positions, and the data storing of memory cell is in the direction perpendicular to chip surface, there is no direct relation with the live width technological ability, so assembly is easy to miniaturization.In addition, decide because the starting voltage of source/drain is a thickness by dielectric layer, and the thickness of dielectric layer is easily controlled by the condition that forms, therefore, the present invention can have preferably that starting voltage distributes, and reduces the phenomenon of leakage current.
Description of drawings
Figure 1 shows that a kind of rectilinear read-only memory schematic diagram of first embodiment of the invention;
Fig. 2 A to Fig. 2 Q is depicted as the manufacturing process generalized section of a kind of rectilinear read-only memory of second embodiment of the invention.
100,200: substrate
102: projection area
104,204: gate conductor layer
106a/106b, 230: source/drain
108: the depressed area
110: the code area
112,202: gate oxide
114,232: conductor layer
116: character line
118,234: insulating barrier
120,211: silicon oxide layer
206: cap layer
208: gate stack
210: irrigation canals and ditches
212: high starting voltage gate dielectric layer
214,236: polysilicon layer
214a: polysilicon gap wall
216: high starting voltage ion implantation technology
218a, 218b: mask layer
220,224: the code area ion implantation technology
222,226: the code area
228: flush type diffusion ion injection technology
232a: bit line
238: metal silicide layer
Embodiment
First embodiment
Figure 1 shows that a kind of rectilinear read-only memory schematic diagram of first embodiment of the invention.
Please refer to Fig. 1, rectilinear read-only memory of the present invention comprises the gate conductor layer 104 that is disposed on the substrate 100 with projection area 102 and depressed area 108, conductor layer 114 and the character line 116 used as bit line, and source/drain 106a/106b and code area 110 in the substrate 100, its configuration mode is that gate conductor layer 104 is disposed on the projection area 102 of substrate 100, and conductor layer 114 is disposed on the depressed area 108 of substrate 100, and electrically connect with source/drain 106a/106b, and source/drain 106a/106b is arranged in the depressed area 108 of substrate 100,110 two sides that are positioned at projection area 102, code area, character line 116 is disposed on the substrate 100, and electrically connects with gate conductor layer 104.In addition, also have a gate oxide 112 to be disposed between gate conductor layer 104 and the substrate 100,118 of one insulating barriers are disposed between the substrate 100 of conductor layer 114 and depressed area 108 sidewalls, and have a silicon oxide layer 120 to be disposed between conductor layer 114 and the character line 116.Wherein, conductor layer 114 is a polysilicon for example with the material of character line 116.And, on character line 116, can also comprise one deck metal silicide layer (not drawing), its material can be a tungsten silicide.
What should be specified is herein, has second conductivity for forming the employed ion of ion implantation technology that carries out code area 110, it is different with the first conductivity admixture that originally is present in herein, but doping content is then lower, make the code area 110 (negative sign "-" sign place among Fig. 1) that is injected into--have first conductivity of lighter doping content, and therefore have lower starting voltage.
In reading of data, earlier grid 104 is opened, and applied a high voltage at drain electrode 106b, apply a low-voltage at source electrode 106a.Will form an inversion layer in the substrate 100 on conductor layer 114 sides of grid 104 belows and drain electrode 106b side.If the code area 110 of source electrode 106a side has the ion that coding injects, then because the starting voltage of this code area 110 is lower, the low-voltage that is applied on the source electrode 106a is enough to produce inversion layer in source electrode 106a side, therefore, grid 104 belows, drain electrode 106b side and source electrode 106a side can form raceway groove, and are detected electric current.Otherwise, if being subjected to coding, the code area 110 of source electrode 106a side do not inject, then because these code area 110 its starting voltages are higher, the low-voltage that is applied on the source electrode 106a is not enough to produce inversion layer in source electrode 106a side, therefore, source electrode 106a side can't generally produce raceway groove with grid 104 belows, drain electrode 106b side, so can't detect electric current.For describing the manufacture method with semiconductor subassembly of embedded type bit line of the present invention in detail, please refer to shown in Fig. 2 A to Fig. 2 Q.
Second embodiment
Fig. 2 A to Fig. 2 Q is depicted as the manufacturing process generalized section of a kind of rectilinear read-only memory of second embodiment of the invention.
Please refer to Fig. 2 A, form a gate oxide 202 on a substrate 200, its thickness is about 30 dusts, forms one deck gate conductor layer 204 again on substrate 200, and its thickness is about 1500 dusts.
Then, please refer to Fig. 2 B, form one deck cap layer (Cap Layer) 206 and cover gate conductor layer 204 on substrate 200, its thickness is about 600 dusts.In addition, before this technology, can also carry out a preceding cleaning (Pre-clean), and after this technology, more can carry out a back cleaning (Post clean).
Then, please refer to Fig. 2 C, patterning cap layer 206 and gate conductor layer 204 are to form the gate stack of being made up of gate conductor layer 204a and cap layer 206a (Gate Stack) 208 on substrate 200.
Then, please refer to Fig. 2 D, is etching mask with cap layer 206a, and the gate oxide 202 that exposes is removed in etching, and continues to be etched to substrate 200, to form irrigation canals and ditches 210.The silicon etching of its etch process (Si Etch) speed for example be 1500 ± 150 dusts/minute.
, please refer to Fig. 2 E, form the silicon oxide layer 211 of about 50 dusts in irrigation canals and ditches 210 sidewalls thereafter, also can comprise one before this technology before cleaning.This silicon oxide layer 211 will be in removing after a while.Technology main purpose shown in this figure is to repair the infringement that etch process caused of irrigation canals and ditches 210, is to belong to the step that can select (Optional) to carry out.
Then, please refer to Fig. 2 F, remove silicon oxide layer 211, form a high starting voltage gate dielectric layer (High Vt Gate Oxide) 212 in irrigation canals and ditches 210 surfaces again, its formation method for example is thermal oxidation method (thermal oxidation), and its thickness is about 15 dusts～100 dusts.Then, also be included in the thin polysilicon layer 214 of deposition one deck on the substrate 200, about 100 dusts of its thickness, and the effect of this polysilicon layer 214 is to protect high starting voltage gate dielectric layer 212, makes it can not suffer the destruction of follow-up ion implantation technology.
Then, please refer to Fig. 2 G, substrate 200 is carried out a high starting voltage ion implantation technology (High Vt I/I) 216, it injects ion for example is boron difluoride ion (BF
2 +); Implant angle is about 15 degree.
Subsequently, please refer to Fig. 2 H, form mask layer 218a in part irrigation canals and ditches 210, in order to the mask as read-only memory first coding (ROM code 1) technology, its material comprises photoresistance, and thickness is about 1000 dusts.
Then, please refer to Fig. 2 I, carry out one first code area ion implantation technology (Code1 I/I) 220, in substrate 200, to form a read-only memory first code area 222.Wherein, it is 216 different that the conductivity of the injection ion of the first code area ion implantation technology 220 and high starting voltage ion inject, and it for example is arsenic (As) ion; Implant angle is 20 degree.
Then, please refer to Fig. 2 J, remove mask layer 218a, in part irrigation canals and ditches 210, form mask layer 218b again, in order to mask as read-only memory second coding (ROM code 2) technology.Then, carry out one second code area ion implantation technology (Code2 I/I) 224, in substrate 200, to form a read-only memory second code area 226.Wherein, the injection ion of the second code area ion implantation technology 224 for example is an arsenic; Implant angle is 20 degree.
Then, please refer to Fig. 2 K, remove mask layer 218b, eat-back unkind polysilicon layer 214 again, make that irrigation canals and ditches 210 sidewalls are residual thin polysilicon gap wall 214a, and expose the high starting voltage gate dielectric layer 212 of irrigation canals and ditches 210 bottoms.
Thereafter, please refer to Fig. 2 L, substrate 200 is carried out flush type diffusion ion injection technology (Buried Diffusion I/I) 228, in irrigation canals and ditches 210 substrate of bottom portion 200, to form source/drain 230, wherein, the injection ion of flush type diffusion ion injection technology 228 for example is an arsenic ion; Inject energy and be about 10KeV; Implantation dosage is about 1 * 10
14Ions/cm
2In addition, can comprise also before flush type diffusion ion injection technology 228 and carry out flush type diffusion pocket ion implantation technology (Buried Diffusion Pocket I/I) that it injects ion for example is boron difluoride; Implant angle is about 20 degree.
Subsequently, please refer to Fig. 2 M, the high starting voltage gate dielectric layer 212 on the source/drain 230 of removal irrigation canals and ditches 210 bottoms; Its method for example is a Wet-type etching.Then, carry out a preceding cleaning, deposit a conductor layer 232 again on substrate 200, its thickness is about 3000 dusts, and its material for example is a polysilicon.
Then, please refer to Fig. 2 N, etch-back conductor layer 232 is to form the bit line 232a on the source/drain 230 in irrigation canals and ditches 210.
Then, please refer to Fig. 2 O, form a layer insulating 234 in bit line 232a surface, its thickness is about 200 dusts, and its material comprises silica.
Then, please refer to Fig. 2 P, remove cap layer 206a, the method for removal comprises utilizes hot phosphoric acid (Hot H
3PO
4) remove, and gate conductor layer 204a is come out.
Thereafter, please refer to Fig. 2 Q, carry out a preceding cleaning earlier, then, form the metal silicide layer 238 on one deck polysilicon layer 236 and its upper strata on substrate 200, its material for example is a tungsten silicide.
So the data storing that the invention is characterized in memory cell of the present invention in the direction perpendicular to chip surface, there is no direct relation with the live width technological ability, so assembly is easy to miniaturization.
In addition, because being the thickness by high starting voltage gate dielectric layer 212, the starting voltage of source/drain 230 decides, and the thickness of high starting voltage gate dielectric layer 212 is easily controlled (for example being the time that the control thermal oxidation method carries out) by the condition that forms, therefore, the present invention can have starting voltage distribution preferably, and reduces the phenomenon of leakage current.
Claims (20)
1, a kind of rectilinear read-only memory is characterized in that, its structure comprises:
One substrate, this substrate have a projection area and a depressed area that replaces mutually;
One gate conductor layer, it is disposed on this projection area of this substrate;
Source, it is arranged in this depressed area of this substrate;
One code area, it is arranged in this substrate of this depressed area sidewall;
One gate dielectric layer, it is disposed between this gate conductor layer and this substrate;
One conductor layer, it is disposed on the depressed area of this substrate substrate, and electrically connects with this source/drain;
One character line, it is disposed on this substrate, and electrically connects with this gate conductor layer;
One insulating barrier, it is disposed between this substrate of this conductor layer and this depressed area sidewall.
2, rectilinear read-only memory as claimed in claim 1 is characterized in that, its structure more comprises a silicon oxide layer, between this character line and this conductor layer.
3, rectilinear read-only memory as claimed in claim 1 is characterized in that, the material of this conductor layer comprises polysilicon.
4, rectilinear read-only memory as claimed in claim 1 is characterized in that, the material of this character line comprises polysilicon.
5, rectilinear read-only memory as claimed in claim 1 is characterized in that, comprises that more a metal silicide layer is positioned on this character line.
6, rectilinear read-only memory as claimed in claim 5 is characterized in that, the material of this metal silicide layer comprises tungsten silicide.
7, a kind of manufacture method of rectilinear read-only memory is characterized in that, this method comprises:
One substrate is provided;
On this substrate, form a first grid dielectric layer;
On this substrate, form a gate conductor layer;
On this substrate, form a cap layer, cover this gate conductor layer;
This cap layer of patterning and this gate conductor layer are to form a gate stack of being made up of this gate conductor layer and this cap layer on this substrate;
With this cap layer is etching mask, and this first grid dielectric layer that exposes is removed in etching, and continues to be etched in this substrate, to form irrigation canals and ditches;
Form one second gate dielectric layer in this trench sidewall;
This substrate is carried out a high starting voltage ion implantation technology;
In this substrate of this trench sidewall of part, form a plurality of code areas;
Carry out a flush type diffusion ion injection technology, in this substrate of this irrigation canals and ditches bottom, to form source;
In these irrigation canals and ditches, form a conductor layer;
Form an insulating barrier in this conductor layer surface;
Remove this cap layer, to expose this gate conductor layer; And
On this substrate, form a polysilicon layer.
8, the manufacture method of rectilinear read-only memory as claimed in claim 7 is characterized in that, form this step of these irrigation canals and ditches after, more comprise:
Form an oxide layer in this trench sidewall; And
Remove this oxide layer.
9, the manufacture method of rectilinear read-only memory as claimed in claim 7 is characterized in that, the thickness of this second gate dielectric layer is between 15 dusts～100 dusts.
10, the manufacture method of rectilinear read-only memory as claimed in claim 7 is characterized in that, form this step of this second gate dielectric layer after, more be included on this substrate deposition one polysilicon layer, this polysilicon layer is protected this second gate dielectric layer.
11, the manufacture method of rectilinear read-only memory as claimed in claim 7 is characterized in that, the injection ion of this high starting voltage ion implantation technology comprises boron difluoride.
12, the manufacture method of rectilinear read-only memory as claimed in claim 7 is characterized in that, the injection ion of this flush type diffusion ion injection technology comprises arsenic.
13, the manufacture method of rectilinear read-only memory as claimed in claim 7 is characterized in that, should more comprise and carry out flush type diffusion pocket ion implantation technology before this flush type diffusion ion injection technology.
14, the manufacture method of rectilinear read-only memory as claimed in claim 13 is characterized in that, the injection ion of this flush type diffusion pocket ion implantation technology comprises boron difluoride.
15, the manufacture method of rectilinear read-only memory as claimed in claim 7 is characterized in that, the material of this conductor layer comprises polysilicon.
16, the manufacture method of rectilinear read-only memory as claimed in claim 7 is characterized in that, this step that forms this conductor layer in these irrigation canals and ditches comprises:
Deposition one conductor material is to insert this irrigation canals and ditches on this substrate; And
This conductor material of etch-back.
17, the manufacture method of rectilinear read-only memory as claimed in claim 7 is characterized in that, this step of removing this cap layer comprises utilizes hot phosphoric acid.
18, the manufacture method of rectilinear read-only memory as claimed in claim 7 is characterized in that, more is included in after this step that forms this polysilicon layer on this substrate and forms a metal silicide layer on this polysilicon layer.
19, the manufacture method of rectilinear read-only memory as claimed in claim 18 is characterized in that, the material of this metal silicide layer comprises tungsten silicide.
20, a kind of manufacture method of rectilinear read-only memory comprises:
Form a grid in a substrate surface;
In this substrate, form irrigation canals and ditches;
Bottom in these irrigation canals and ditches makes source;
On substrate, form a dielectric layer, to cover this grid and this trench sidewall;
Form a code area in this trench sidewall; And
Form a bit line in these irrigation canals and ditches, this bit line and this source/drain electrically connect.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02101573.2A CN1279619C (en) | 2002-01-10 | 2002-01-10 | Vertical ROM and its making process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02101573.2A CN1279619C (en) | 2002-01-10 | 2002-01-10 | Vertical ROM and its making process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1433079A CN1433079A (en) | 2003-07-30 |
| CN1279619C true CN1279619C (en) | 2006-10-11 |
Family
ID=27627340
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN02101573.2A Expired - Fee Related CN1279619C (en) | 2002-01-10 | 2002-01-10 | Vertical ROM and its making process |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1326233C (en) * | 2003-08-22 | 2007-07-11 | 南亚科技股份有限公司 | Multi-element vertical memory and its manufacture |
| DE102004047655A1 (en) * | 2004-09-14 | 2006-04-06 | Infineon Technologies Ag | Charge-trapping semiconductor memory device |
| CN101707213B (en) * | 2009-01-23 | 2011-05-25 | 旺宏电子股份有限公司 | Memory and preparation method thereof |
| US8786014B2 (en) * | 2011-01-18 | 2014-07-22 | Powerchip Technology Corporation | Vertical channel transistor array and manufacturing method thereof |
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2002
- 2002-01-10 CN CN02101573.2A patent/CN1279619C/en not_active Expired - Fee Related
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| Publication number | Publication date |
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| CN1433079A (en) | 2003-07-30 |
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Granted publication date: 20061011 Termination date: 20210110 |