KR20070004338A - Method of manufacturing a nand flash memory device - Google Patents

Method of manufacturing a nand flash memory device Download PDF

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KR20070004338A
KR20070004338A KR1020050059855A KR20050059855A KR20070004338A KR 20070004338 A KR20070004338 A KR 20070004338A KR 1020050059855 A KR1020050059855 A KR 1020050059855A KR 20050059855 A KR20050059855 A KR 20050059855A KR 20070004338 A KR20070004338 A KR 20070004338A
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South Korea
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film
flash memory
memory device
nand flash
layer
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KR1020050059855A
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Korean (ko)
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KR100812942B1 (en
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김남경
최은석
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주식회사 하이닉스반도체
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Priority to KR1020050059855A priority Critical patent/KR100812942B1/en
Priority to US11/479,285 priority patent/US20070004141A1/en
Priority to CNB2006101156370A priority patent/CN100474569C/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate

Abstract

A method for fabricating a NAND flash memory device is provided to broaden the surface area on a dielectric layer formed on a floating gate by forming a three-dimensional floating gate so that the surface area of the floating gate is extended. After a tunnel oxide layer(104) and a conductive layer are deposited on a semiconductor substrate(100) having an isolation layer, the conductive layer is etched. The conductive layer may be made of a doped polysilicon layer, W, WN, Ti, TiN, Pt, Ruby, RuO2, Ir, IrO2, or Al. After an oxide layer is formed to fill a gap between the conductive layers, a polishing process is performed until the conductive layer is exposed. After the center part of the conductive layer is etched to form a recess pattern(110), the oxide layer is removed to form a three-dimensional floating gate. After a dielectric layer is formed on the resultant structure and a polysilicon layer, a metal layer and a hard mask layer are sequentially formed, a patterning process is performed to form a contact gate.

Description

낸드 플래쉬 메모리 소자의 제조방법{Method of manufacturing a nand flash memory device}Method of manufacturing a NAND flash memory device

도 1a 내지 도 1d는 본 발명의 일 실시예에 따른 낸드 플래쉬 메모리 소자의 제조방법을 설명하기 위해 도시한 소자의 단면도이다.1A to 1D are cross-sectional views illustrating a device for manufacturing a NAND flash memory device according to an embodiment of the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

100 : 반도체 기판 102 : 소자분리막100 semiconductor substrate 102 device isolation film

104 : 터널 산화막 106 : 도전막104 tunnel oxide film 106 conductive film

108 : 산화막 110 : 리세스 패턴108: oxide film 110: recess pattern

112 : 유전체막 114 : 폴리실리콘막112: dielectric film 114: polysilicon film

116 : 메탈막 118 : 하드 마스크막116: metal film 118: hard mask film

본 발명은 낸드 플래쉬 메모리 소자의 제조방법에 관한 것으로, 특히, 플로 팅 게이트의 정전용량을 증가시켜 프로그램 속도를 향상시키기 위한 낸드 플래쉬 메모리 소자의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a NAND flash memory device, and more particularly, to a method of manufacturing a NAND flash memory device for increasing a program speed by increasing capacitance of a floating gate.

비휘발성의 플래쉬 메모리 소자는 플로팅 게이트와 컨트롤 게이트의 2개의 게이트로 형성되어 있고, 플로팅 게이트의 하단엔 터널 산화막이, 상단엔 유전체막이 각각 형성되어 있다. 소자의 집적도가 높아짐에 따라 소자 동작 중의 빠른 라이트 타임(write time)과 높은 데이터 신뢰도가 요구되는데, 이를 위해 플로팅 게이트의 정전용량을 증가시켜야 한다.The nonvolatile flash memory device is formed of two gates, a floating gate and a control gate. A tunnel oxide film is formed at the bottom of the floating gate and a dielectric film is formed at the top thereof. As the device density increases, fast write time and high data reliability during device operation are required. For this purpose, the capacitance of the floating gate needs to be increased.

그러나, 고유전 물질을 적용하여 정전용량을 증가 시키면, 열악한 인터페이스 트랩(interface trap) 특성과 급격한 문턱전압(vt)의 변화(shift)등으로 소자의 신뢰성을 저하시켜 적용이 어렵다. 또한, 유전체막 두께를 감소시켜 플로팅 게이트의 정전용량을 증가 시키면, 파괴전압(breakdown)의 감소로 데이터 페일에 직접적인 영향을 주기 때문에 유전체막의 두께를 감소시키는데는 한계가 있다.However, if the capacitance is increased by applying a high dielectric material, it is difficult to apply the device due to poor interface trap characteristics and sudden shifts in threshold voltage (vt). In addition, increasing the capacitance of the floating gate by reducing the thickness of the dielectric film has a limitation in reducing the thickness of the dielectric film because it directly affects data failure due to a decrease in breakdown voltage.

상술한 문제점을 해결하기 위해 안출된 본 발명의 목적은 플로팅 게이트의 정전 용량을 증가시켜 소자의 신뢰도를 향상시키기 위한 낸드 플래쉬 메모리 소자의 제조방법을 제공하는데 있다.An object of the present invention devised to solve the above problems is to provide a method of manufacturing a NAND flash memory device for increasing the capacitance of the floating gate to improve the reliability of the device.

본 발명의 일 실시예에 따른 낸드 플래쉬 메모리 소자의 제조방법은, 소자분 리막이 형성된 반도체 기판 상부에 터널 산화막, 도전막을 증착 시킨 후, 상기 도전막을 식각하는 단계와, 상기 도전막 사이가 매립되도록 산화막을 형성한 후, 상기 도전막이 노출될 때까지 연마하여 평탄화시키는 단계와, 상기 도전막 중심 부분을 식각하여 리세스 패턴을 형성한 후, 상기 산화막을 제거하여 3차원의 플로팅 게이트를 형성하는 단계와, 전체 구조 상부에 유전체막을 형성하고, 폴리실리콘막, 메탈막 및 하드 마스크막을 순차적으로 형성한 후, 패터닝하여 컨트롤 게이트를 형성하는 단계를 포함하는 낸드 플래쉬 메모리 소자의 제조방법을 제공한다.According to an embodiment of the present invention, a method of manufacturing a NAND flash memory device includes depositing a tunnel oxide film and a conductive film on an upper surface of a semiconductor substrate on which a device isolation film is formed, and then etching the conductive film and filling the gap between the conductive films. Forming an oxide film, polishing and planarizing the conductive film until the conductive film is exposed, etching a center portion of the conductive film to form a recess pattern, and then removing the oxide film to form a three-dimensional floating gate And forming a dielectric film over the entire structure, and sequentially forming a polysilicon film, a metal film, and a hard mask film, and then patterning the control gate to form a control gate.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1d는 본 발명의 일 실시예에 따른 낸드 플래쉬 메모리 소자의 제조방법을 설명하기 위해 순차적으로 도시한 소자의 단면도이다.1A to 1D are cross-sectional views sequentially illustrating devices for manufacturing a NAND flash memory device according to an exemplary embodiment of the present invention.

도 1a를 참조하면, 소자분리막(102)이 형성된 반도체 기판(100) 상부에 터널 산화막(104), 도전막(106)을 증착한다. 이때, 도전막(106)은 CVD(Chemical Vapor Deposition) 방식 및 ALD(Atomic Layer Deposition)방식을 적용하여 도프트된 폴리실리콘막, W, WN, Ti, TiN, Pt, Ru, RuO2, Ir, IrO2, Al등으로 형성한다. 여기서, 도프트된 폴리실리콘막은 100Å 내지 5000Å의 두께, 250℃ 내지 1000℃의 온도로 형성한다. Referring to FIG. 1A, a tunnel oxide film 104 and a conductive film 106 are deposited on the semiconductor substrate 100 on which the device isolation film 102 is formed. At this time, the conductive film 106 is a polysilicon film doped by applying a chemical vapor deposition (CVD) method and an atomic layer deposition (ALD) method, W, WN, Ti, TiN, Pt, Ru, RuO 2 , Ir, It is formed of IrO 2 , Al and the like. Here, the doped polysilicon film is formed at a thickness of 100 kPa to 5000 kPa and a temperature of 250C to 1000C.

도 1b를 참조하면, 도전막(106) 상부에 감광막 패턴을 형성한 후, 이를 마스 크로 도전막(106)을 식각하여 도전막 패턴(106a)을 형성한다. 이후, 도전막 패턴(106a)사이가 매립되도록 산화막(108)을 형성한 후, 도전막 패턴(106a)이 노출될때까지 CMP 공정을 실시하여 평탄화 시킨다. 이때, 산화막(108)은 HDP, PE-TEOS, HTO, APL등을 사용하여 형성한다. Referring to FIG. 1B, after the photoresist pattern is formed on the conductive layer 106, the mask layer is etched to form the conductive layer pattern 106a. Thereafter, the oxide film 108 is formed to fill the gap between the conductive film patterns 106a, and then planarized by performing a CMP process until the conductive film pattern 106a is exposed. At this time, the oxide film 108 is formed using HDP, PE-TEOS, HTO, APL and the like.

도 1c를 참조하면, 전체 구조 상부에 감광막 패턴을 형성한 후, 도전막 패턴(106a) 중심 부분을 부분적으로 식각하여 리세스 패턴(110)을 형성한다. 리세스 패턴(110)은 Cl 및 F 가스를 사용하여 100Å 내지 5000Å의 두께로 식각한다. 습식 식각으로 산화막(108)을 제거하여 3차원의 플로팅 게이트를 형성함으로써, 플로팅 게이트의 표면적을 넓게 확보한다. 여기서, 산화막(108) 형성 공정은 도전막 패턴(106a) 중심 부분을 식각하여 리세스 패턴(110)을 형성 할 때, 전체 구조 상부에 감광막 패턴을 형성하는데, 이 감광막 패턴 형성이 미스얼라인(misalign) 되는 것을 방지하기 위해 실시한다.Referring to FIG. 1C, after the photoresist pattern is formed over the entire structure, the recess pattern 110 is formed by partially etching the center portion of the conductive layer pattern 106a. The recess pattern 110 is etched to a thickness of 100 kPa to 5000 kPa using Cl and F gases. The oxide film 108 is removed by wet etching to form a three-dimensional floating gate, thereby securing a large surface area of the floating gate. Here, in the forming process of the oxide film 108, when the recess pattern 110 is formed by etching the center portion of the conductive film pattern 106a, the photoresist film pattern is formed on the entire structure. to prevent misalignment.

도 1d를 참조하면, 플로팅 게이트 상부에 유전체막(112)을 형성함으로써, 유전체막(112)의 표면적이 넓어지게 되어 플로팅 게이트의 정전용량을 증가시킨다. 유전체막(112)은 20Å 내지 1000Å 두께의 산화막, 질화막, 산화막이 적층된 구조로 형성한다. 이때, 산화막은 5Å 내지 100Å의 두께로, 질화막은 10Å 내지 100Å의 두께로 형성된다. 또한, 유전체막(112)은 고유전 물질인 Al2O3, HfO2, ZrO2를 단독으로 형성하거나, HfO2 및 ZrO2를 혼합하여 형성한다. 전체 구조 상부에 폴리실리콘막(114), 메탈막(116) 및 하드 마스크막(118)을 순차적으로 형성한 후, 패터닝하 여 컨트롤 게이트를 형성한다. 폴리실리콘막(114)은 100Å 내지 5000Å의 두께로 형성하고, 메탈막(116)은 100Å 내지 3500Å 두께의 W, WN, Pt, Ir, Ru, Te등으로 형성하며, 하드 마스크막(118)은 질화막인 Si3N4 및 Si-N으로 형성한다. 여기서, Si3N4는 퍼니스(furnace) 방식을 적용하고, Si-N는 플라즈마 방식을 적용한다.Referring to FIG. 1D, by forming the dielectric film 112 over the floating gate, the surface area of the dielectric film 112 is increased to increase the capacitance of the floating gate. The dielectric film 112 is formed in a structure in which an oxide film, a nitride film, and an oxide film having a thickness of 20 kV to 1000 kV are stacked. At this time, the oxide film is formed to a thickness of 5 kPa to 100 kPa, and the nitride film is formed to a thickness of 10 kPa to 100 kPa. In addition, the dielectric film 112 is formed by forming Al 2 O 3 , HfO 2 , ZrO 2 , which are high dielectric materials, or by mixing HfO 2 and ZrO 2 . The polysilicon film 114, the metal film 116, and the hard mask film 118 are sequentially formed on the entire structure, and then patterned to form a control gate. The polysilicon film 114 is formed to a thickness of 100 kPa to 5000 kPa, the metal film 116 is formed of W, WN, Pt, Ir, Ru, Te, or the like having a thickness of 100 kPa to 3500 kPa, and the hard mask film 118 is It is formed of Si 3 N 4 and Si-N which are nitride films. Here, Si 3 N 4 applies a furnace method, and Si-N applies a plasma method.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주지하여야 한다. 또한, 본 발명의 기술 분야에서 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 바와 같이 본 발명에 의하면, 3차원 플로팅 게이트를 형성하여 플로팅 게이트의 표면적을 넓힘으로써, 플로팅 게이트 상부에 형성되는 유전체막의 표면적이 넓어지게 되어 정전 용량을 증가시킨다. 이로 인해, 프로그램 속도가 향상 되고, 소자의 신뢰도가 높아지는 효과가 있다.As described above, according to the present invention, by forming a three-dimensional floating gate to increase the surface area of the floating gate, the surface area of the dielectric film formed on the floating gate is increased to increase the capacitance. As a result, the program speed is improved, and the reliability of the device is increased.

Claims (13)

소자분리막이 형성된 반도체 기판 상부에 터널 산화막, 도전막을 증착 시킨 후, 상기 도전막을 식각하는 단계;Etching the conductive film after depositing a tunnel oxide film and a conductive film on the semiconductor substrate on which the device isolation film is formed; 상기 도전막 사이가 매립되도록 산화막을 형성한 후, 상기 도전막이 노출될 때까지 연마하여 평탄화시키는 단계; Forming an oxide film so as to fill the space between the conductive films, and then polishing and planarizing the conductive film until the conductive film is exposed; 상기 도전막 중심 부분을 식각하여 리세스 패턴을 형성한 후, 상기 산화막을 제거하여 3차원의 플로팅 게이트를 형성하는 단계; 및Etching the center portion of the conductive layer to form a recess pattern, and then removing the oxide layer to form a three-dimensional floating gate; And 전체 구조 상부에 유전체막을 형성하고, 폴리실리콘막, 메탈막 및 하드 마스크막을 순차적으로 형성한 후, 패터닝하여 컨트롤 게이트를 형성하는 단계를 포함하는 낸드 플래쉬 메모리 소자의 제조방법.A method of manufacturing a NAND flash memory device, comprising: forming a dielectric film over an entire structure, and sequentially forming a polysilicon film, a metal film, and a hard mask film, and then patterning a control gate. 제1항에 있어서, 상기 도전막은 도프트된 폴리실리콘막, W, WN, Ti, TiN, Pt, Ru, RuO2, Ir, IrO2, Al등으로 형성하는 것을 포함하는 낸드 플래쉬 메모리 소자의 제조방법.The NAND flash memory device of claim 1, wherein the conductive film is formed of a doped polysilicon film, W, WN, Ti, TiN, Pt, Ru, RuO 2, Ir, IrO 2, Al, or the like. 제2항에 있어서, 상기 도프트된 폴리실리콘막은 100Å 내지 5000Å의 두께, 250℃ 내지 1000℃의 온도로 형성하는 것을 포함하는 낸드 플래쉬 메모리 소자의 제조방법.The NAND flash memory device of claim 2, wherein the doped polysilicon film is formed at a thickness of 100 ° C. to 5000 ° C. and a temperature of 250 ° C. to 1000 ° C. 4. 제1항에 있어서, 상기 도전막은 CVD 방식 및 ALD 방식을 적용하여 형성하는 것을 포함하는 낸드 플래쉬 메모리 소자의 제조방법.The NAND flash memory device of claim 1, wherein the conductive film is formed by applying a CVD method and an ALD method. 제1항에 있어서, 상기 산화막은 HDP, PE-TEOS, HTO, APL등을 사용하여 형성하는 것을 포함하는 낸드 플래쉬 메모리 소자의 제조방법.The NAND flash memory device of claim 1, wherein the oxide film is formed using HDP, PE-TEOS, HTO, APL, or the like. 제1항에 있어서, 상기 리세스 패턴은 Cl 및 F 가스를 사용하여 100Å 내지 5000Å의 두께로 식각하는 것을 포함하는 낸드 플래쉬 메모리 소자의 제조방법.The NAND flash memory device of claim 1, wherein the recess pattern is etched to a thickness of 100 μs to 5000 μs using Cl and F gases. 제1항에 있어서, 상기 유전체막은 20Å 내지 1000Å 두께의 산화막, 질화막, 산화막이 적층된 구조로 형성하는 것을 포함하는 낸드 플래쉬 메모리 소자의 제조방법.The NAND flash memory device of claim 1, wherein the dielectric film has a structure in which an oxide film, a nitride film, and an oxide film are stacked in a thickness of 20 μs to 1000 μs. 제7항에 있어서, 상기 산화막은 5Å 내지 100Å의 두께로, 질화막은 10Å 내지 100Å의 두께로 형성하는 것을 포함하는 낸드 플래쉬 메모리 소자의 제조방법.The NAND flash memory device of claim 7, wherein the oxide film has a thickness of 5 kPa to 100 kPa and the nitride film has a thickness of 10 kPa to 100 kPa. 제1항에 있어서, 상기 유전체막은 고유전 물질인 Al2O3, HfO3 및 ZrO2를 단독으로 사용하거나, HfO3 및 ZrO2를 혼합하여 사용하는 것을 포함하는 낸드 플래쉬 메모리 소자의 제조방법.The NAND flash memory device of claim 1, wherein the dielectric layer includes Al 2 O 3 , HfO 3, and ZrO 2 , which are high dielectric materials, or a mixture of HfO 3 and ZrO 2 . 제1항에 있어서, 상기 폴리실리콘막는 100Å 내지 5000Å의 두께로 형성하는 것을 포함하는 낸드 플래쉬 메모리 소자의 제조방법.The NAND flash memory device of claim 1, wherein the polysilicon film is formed to a thickness of about 100 μs to about 5000 μs. 제1항에 있어서, 상기 메탈막은 100Å 내지 3500Å 두께의 W, WN, Pt, Ir, Ru, Te등으로 형성하는 것을 포함하는 낸드 플래쉬 메모리 소자의 제조방법.The NAND flash memory device of claim 1, wherein the metal layer is formed of W, WN, Pt, Ir, Ru, Te, or the like having a thickness of about 100 to 3500 microns. 제1항에 있어서, 상기 하드 마스크막은 질화막인 Si3N4 및 Si-N으로 형성하 는 것을 포함하는 낸드 플래쉬 메모리 소자의 제조방법.The NAND flash memory device of claim 1, wherein the hard mask layer is formed of Si 3 N 4 and Si-N, which are nitride films. 제12항에 있어서, 상기 Si3N4는 퍼니스 방식을, Si-N은 플라즈마 방식을 적용하는 것을 포함하는 낸드 플래쉬 메모리 소자의 제조방법.The NAND flash memory device of claim 12, wherein the Si 3 N 4 is a furnace type and the Si-N is a plasma type.
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